// mi_iram.v v1 Frank Berndt
// mi boot sram;
// :set tabstop=4

module mi_iram (
	sysclk,
	iram_ena, iram_addr, iram_di, iram_we, iram_do
);

`include "define.vh"

	input sysclk;				// system clock;
	input iram_ena;				// ram enable;
	input [14:2] iram_addr;		// address;
	input [31:0] iram_di;		// write data;
	input [3:0] iram_we;		// byte write enables;
	output [31:0] iram_do;		// read data;

`ifdef	NEC_IRAM

	// instantiate two 4kx32 with byte enables;
	// memory compiler is limited to 4k words;

	wire [1:0] iram_cs;			// ram selects;
	reg iram1_sel;				// ram output data mux;
	wire [31:0] iram0_do;		// iram0 read data;
	wire [31:0] iram1_do;		// iram1 read data;
	wire [1:0] iram_csb;		// active-0 chip selects;
	wire [3:0] iram_web;		// active-0 write enables;

	assign iram_cs[0] = iram_ena & ~iram_addr[14];
	assign iram_cs[1] = iram_ena & iram_addr[14];
	assign iram_csb = ~iram_cs;
	assign iram_web = ~iram_we;

	always @(posedge sysclk)
	begin
		iram1_sel <= iram_cs[1];
	end

	WBSRAMSHS4096W32C4B8 iram0 (
		.DO31(iram0_do[31]),
		.DO30(iram0_do[30]),
		.DO29(iram0_do[29]),
		.DO28(iram0_do[28]),
		.DO27(iram0_do[27]),
		.DO26(iram0_do[26]),
		.DO25(iram0_do[25]),
		.DO24(iram0_do[24]),
		.DO23(iram0_do[23]),
		.DO22(iram0_do[22]),
		.DO21(iram0_do[21]),
		.DO20(iram0_do[20]),
		.DO19(iram0_do[19]),
		.DO18(iram0_do[18]),
		.DO17(iram0_do[17]),
		.DO16(iram0_do[16]),
		.DO15(iram0_do[15]),
		.DO14(iram0_do[14]),
		.DO13(iram0_do[13]),
		.DO12(iram0_do[12]),
		.DO11(iram0_do[11]),
		.DO10(iram0_do[10]),
		.DO9(iram0_do[9]),
		.DO8(iram0_do[8]),
		.DO7(iram0_do[7]),
		.DO6(iram0_do[6]),
		.DO5(iram0_do[5]),
		.DO4(iram0_do[4]),
		.DO3(iram0_do[3]),
		.DO2(iram0_do[2]),
		.DO1(iram0_do[1]),
		.DO0(iram0_do[0]),
		.DI31(iram_di[31]),
		.DI30(iram_di[30]),
		.DI29(iram_di[29]),
		.DI28(iram_di[28]),
		.DI27(iram_di[27]),
		.DI26(iram_di[26]),
		.DI25(iram_di[25]),
		.DI24(iram_di[24]),
		.DI23(iram_di[23]),
		.DI22(iram_di[22]),
		.DI21(iram_di[21]),
		.DI20(iram_di[20]),
		.DI19(iram_di[19]),
		.DI18(iram_di[18]),
		.DI17(iram_di[17]),
		.DI16(iram_di[16]),
		.DI15(iram_di[15]),
		.DI14(iram_di[14]),
		.DI13(iram_di[13]),
		.DI12(iram_di[12]),
		.DI11(iram_di[11]),
		.DI10(iram_di[10]),
		.DI9(iram_di[9]),
		.DI8(iram_di[8]),
		.DI7(iram_di[7]),
		.DI6(iram_di[6]),
		.DI5(iram_di[5]),
		.DI4(iram_di[4]),
		.DI3(iram_di[3]),
		.DI2(iram_di[2]),
		.DI1(iram_di[1]),
		.DI0(iram_di[0]),
		.A11(iram_addr[13]),
		.A10(iram_addr[12]),
		.A9(iram_addr[11]),
		.A8(iram_addr[10]),
		.A7(iram_addr[9]),
		.A6(iram_addr[8]),
		.A5(iram_addr[7]),
		.A4(iram_addr[6]),
		.A3(iram_addr[5]),
		.A2(iram_addr[4]),
		.A1(iram_addr[3]),
		.A0(iram_addr[2]),
		.WEB3(iram_web[3]),
		.WEB2(iram_web[2]),
		.WEB1(iram_web[1]),
		.WEB0(iram_web[0]),
		.CSB(iram_csb[0]),
		.BE(sysclk),
		.TBE(1'b0),
		.TEST(1'b0),
		.BUB(1'b1)
	);

	WBSRAMSHS4096W32C4B8 iram1 (
		.DO31(iram1_do[31]),
		.DO30(iram1_do[30]),
		.DO29(iram1_do[29]),
		.DO28(iram1_do[28]),
		.DO27(iram1_do[27]),
		.DO26(iram1_do[26]),
		.DO25(iram1_do[25]),
		.DO24(iram1_do[24]),
		.DO23(iram1_do[23]),
		.DO22(iram1_do[22]),
		.DO21(iram1_do[21]),
		.DO20(iram1_do[20]),
		.DO19(iram1_do[19]),
		.DO18(iram1_do[18]),
		.DO17(iram1_do[17]),
		.DO16(iram1_do[16]),
		.DO15(iram1_do[15]),
		.DO14(iram1_do[14]),
		.DO13(iram1_do[13]),
		.DO12(iram1_do[12]),
		.DO11(iram1_do[11]),
		.DO10(iram1_do[10]),
		.DO9(iram1_do[9]),
		.DO8(iram1_do[8]),
		.DO7(iram1_do[7]),
		.DO6(iram1_do[6]),
		.DO5(iram1_do[5]),
		.DO4(iram1_do[4]),
		.DO3(iram1_do[3]),
		.DO2(iram1_do[2]),
		.DO1(iram1_do[1]),
		.DO0(iram1_do[0]),
		.DI31(iram_di[31]),
		.DI30(iram_di[30]),
		.DI29(iram_di[29]),
		.DI28(iram_di[28]),
		.DI27(iram_di[27]),
		.DI26(iram_di[26]),
		.DI25(iram_di[25]),
		.DI24(iram_di[24]),
		.DI23(iram_di[23]),
		.DI22(iram_di[22]),
		.DI21(iram_di[21]),
		.DI20(iram_di[20]),
		.DI19(iram_di[19]),
		.DI18(iram_di[18]),
		.DI17(iram_di[17]),
		.DI16(iram_di[16]),
		.DI15(iram_di[15]),
		.DI14(iram_di[14]),
		.DI13(iram_di[13]),
		.DI12(iram_di[12]),
		.DI11(iram_di[11]),
		.DI10(iram_di[10]),
		.DI9(iram_di[9]),
		.DI8(iram_di[8]),
		.DI7(iram_di[7]),
		.DI6(iram_di[6]),
		.DI5(iram_di[5]),
		.DI4(iram_di[4]),
		.DI3(iram_di[3]),
		.DI2(iram_di[2]),
		.DI1(iram_di[1]),
		.DI0(iram_di[0]),
		.A11(iram_addr[13]),
		.A10(iram_addr[12]),
		.A9(iram_addr[11]),
		.A8(iram_addr[10]),
		.A7(iram_addr[9]),
		.A6(iram_addr[8]),
		.A5(iram_addr[7]),
		.A4(iram_addr[6]),
		.A3(iram_addr[5]),
		.A2(iram_addr[4]),
		.A1(iram_addr[3]),
		.A0(iram_addr[2]),
		.WEB3(iram_web[3]),
		.WEB2(iram_web[2]),
		.WEB1(iram_web[1]),
		.WEB0(iram_web[0]),
		.CSB(iram_csb[1]),
		.BE(sysclk),
		.TBE(1'b0),
		.TEST(1'b0),
		.BUB(1'b1)
	);

	assign iram_do = iram1_sel? iram1_do : iram0_do;

`else	// NEC_IRAM

	// behavioral model;
	// simulate no write-through;

	reg [7:0] iram0 [0:8191];
	reg [7:0] iram1 [0:8191];
	reg [7:0] iram2 [0:8191];
	reg [7:0] iram3 [0:8191];
	reg iram_xena;
	reg [14:2] iram_xaddr;
	reg [31:0] iram_xdi;
	reg [3:0] iram_xwe;

	initial
		$display("%M: behavioral iram");

	always @(posedge sysclk)
	begin
		iram_xaddr <= iram_addr[14:2];
		iram_xena <= iram_ena;
		iram_xdi <= iram_di;
		iram_xwe <= iram_we;
		if(iram_xena & iram_xwe[3])
			iram3[iram_xaddr] <= iram_xdi[31:24];
		if(iram_xena & iram_xwe[2])
			iram2[iram_xaddr] <= iram_xdi[23:16];
		if(iram_xena & iram_xwe[1])
			iram1[iram_xaddr] <= iram_xdi[15:8];
		if(iram_xena & iram_xwe[0])
			iram0[iram_xaddr] <= iram_xdi[7:0];
	end

	assign iram_do = iram_xena? { iram3[iram_xaddr], iram2[iram_xaddr],
		iram1[iram_xaddr], iram0[iram_xaddr] } : 32'bx;

`endif	// NEC_IRAM

endmodule