// ms_spanbuf.v v1 Frank Berndt
// wrapper for ms span buffers;
// :set tabstop=4

module ms_spanbuf (
	clk, a, di, wen, dout
);
	input clk;			// sync clock;
	input [3:0] a;			// address;
	input [71:0] di;		// write data;
	input wen;			// write enable;
	output [71:0] dout;		// read data;


	// instantiate NEC model;
	// single-port 16x72 SRAM;
	// port A is write, port B is read;


	reg  [4:0] wa;		// port A write address (delayed one clock)
	wire  [71:0] wdata;	// port A write data    (delayed one clock prior to block)
	wire [4:0] ra;		// port B read address;
	wire  csa;		// write port A         (delayed one clock)
	wire  csb;		// read  port B;
	wire clkb;		// invert clock to sram

	reg   WE;		// write enable port A  (delayed one clock)

	always @(posedge clk) begin
		wa    <= {1'b0,a};
		WE    <=  wen;
//		wdata <=  di;
	end

	assign wdata = di;
	assign ra = {1'b0,a};
	assign csa = ~WE;
	assign csb = 1'b0;
	assign clkb = ~clk;

`ifdef	NEC_SPANBUF_BEHAVIORAL

	// behavioral 
	// sram has combinatorial read access
	// and writes occur and end of cycle on the rising edge

	wire	[15:0]	WEnable;

	assign	WEnable[0]  = WE & (wa==4'b0000);
	assign	WEnable[1]  = WE & (wa==4'b0001);
	assign	WEnable[2]  = WE & (wa==4'b0010);
	assign	WEnable[3]  = WE & (wa==4'b0011);
	assign	WEnable[4]  = WE & (wa==4'b0100);
	assign	WEnable[5]  = WE & (wa==4'b0101);
	assign	WEnable[6]  = WE & (wa==4'b0110);
	assign	WEnable[7]  = WE & (wa==4'b0111);
	assign	WEnable[8]  = WE & (wa==4'b1000);
	assign	WEnable[9]  = WE & (wa==4'b1001);
	assign	WEnable[10] = WE & (wa==4'b1010);
	assign	WEnable[11] = WE & (wa==4'b1011);
	assign	WEnable[12] = WE & (wa==4'b1100);
	assign	WEnable[13] = WE & (wa==4'b1101);
	assign	WEnable[14] = WE & (wa==4'b1110);
	assign	WEnable[15] = WE & (wa==4'b1111);

	reg	[71:0]	entry0;
	reg	[71:0]	entry1;
	reg	[71:0]	entry2;
	reg	[71:0]	entry3;
	reg	[71:0]	entry4;
	reg	[71:0]	entry5;
	reg	[71:0]	entry6;
	reg	[71:0]	entry7;
	reg	[71:0]	entry8;
	reg	[71:0]	entry9;
	reg	[71:0]	entry10;
	reg	[71:0]	entry11;
	reg	[71:0]	entry12;
	reg	[71:0]	entry13;
	reg	[71:0]	entry14;
	reg	[71:0]	entry15;
	reg	[71:0]	rdata;

	wire	[71:0]	nxt_entry0  = WEnable[0]   ? wdata : entry0;
	wire	[71:0]	nxt_entry1  = WEnable[1]   ? wdata : entry1;
	wire	[71:0]	nxt_entry2  = WEnable[2]   ? wdata : entry2;
	wire	[71:0]	nxt_entry3  = WEnable[3]   ? wdata : entry3;
	wire	[71:0]	nxt_entry4  = WEnable[4]   ? wdata : entry4;
	wire	[71:0]	nxt_entry5  = WEnable[5]   ? wdata : entry5;
	wire	[71:0]	nxt_entry6  = WEnable[6]   ? wdata : entry6;
	wire	[71:0]	nxt_entry7  = WEnable[7]   ? wdata : entry7;
	wire	[71:0]	nxt_entry8  = WEnable[8]   ? wdata : entry8;
	wire	[71:0]	nxt_entry9  = WEnable[9]   ? wdata : entry9;
	wire	[71:0]	nxt_entry10 = WEnable[10]  ? wdata : entry10;
	wire	[71:0]	nxt_entry11 = WEnable[11]  ? wdata : entry11;
	wire	[71:0]	nxt_entry12 = WEnable[12]  ? wdata : entry12;
	wire	[71:0]	nxt_entry13 = WEnable[13]  ? wdata : entry13;
	wire	[71:0]	nxt_entry14 = WEnable[14]  ? wdata : entry14;
	wire	[71:0]	nxt_entry15 = WEnable[15]  ? wdata : entry15;

	wire	[71:0]	nxt_rdata = {72{(a==4'b0000)}} & entry0
				  | {72{(a==4'b0001)}} & entry1
				  | {72{(a==4'b0010)}} & entry2
				  | {72{(a==4'b0011)}} & entry3
				  | {72{(a==4'b0100)}} & entry4
				  | {72{(a==4'b0101)}} & entry5
				  | {72{(a==4'b0110)}} & entry6
				  | {72{(a==4'b0111)}} & entry7
				  | {72{(a==4'b1000)}} & entry8
				  | {72{(a==4'b1001)}} & entry9
				  | {72{(a==4'b1010)}} & entry10
				  | {72{(a==4'b1011)}} & entry11
				  | {72{(a==4'b1100)}} & entry12
				  | {72{(a==4'b1101)}} & entry13
				  | {72{(a==4'b1110)}} & entry14
				  | {72{(a==4'b1111)}} & entry15;

	always @(posedge clkb) begin
		entry0  <= nxt_entry0;
		entry1  <= nxt_entry1;
		entry2  <= nxt_entry2;
		entry3  <= nxt_entry3;
		entry4  <= nxt_entry4;
		entry5  <= nxt_entry5;
		entry6  <= nxt_entry6;
		entry7  <= nxt_entry7;
		entry8  <= nxt_entry8;
		entry9  <= nxt_entry9;
		entry10 <= nxt_entry10;
		entry11 <= nxt_entry11;
		entry12 <= nxt_entry12;
		entry13 <= nxt_entry13;
		entry14 <= nxt_entry14;
		entry15 <= nxt_entry15;
		rdata   <= nxt_rdata;
	end

	assign	dout = rdata;

`else
	WBSRAMDHDWR32W72C2 ram (
		.DO71(dout[71]),
		.DO70(dout[70]),
		.DO69(dout[69]),
		.DO68(dout[68]),
		.DO67(dout[67]),
		.DO66(dout[66]),
		.DO65(dout[65]),
		.DO64(dout[64]),
		.DO63(dout[63]),
		.DO62(dout[62]),
		.DO61(dout[61]),
		.DO60(dout[60]),
		.DO59(dout[59]),
		.DO58(dout[58]),
		.DO57(dout[57]),
		.DO56(dout[56]),
		.DO55(dout[55]),
		.DO54(dout[54]),
		.DO53(dout[53]),
		.DO52(dout[52]),
		.DO51(dout[51]),
		.DO50(dout[50]),
		.DO49(dout[49]),
		.DO48(dout[48]),
		.DO47(dout[47]),
		.DO46(dout[46]),
		.DO45(dout[45]),
		.DO44(dout[44]),
		.DO43(dout[43]),
		.DO42(dout[42]),
		.DO41(dout[41]),
		.DO40(dout[40]),
		.DO39(dout[39]),
		.DO38(dout[38]),
		.DO37(dout[37]),
		.DO36(dout[36]),
		.DO35(dout[35]),
		.DO34(dout[34]),
		.DO33(dout[33]),
		.DO32(dout[32]),
		.DO31(dout[31]),
		.DO30(dout[30]),
		.DO29(dout[29]),
		.DO28(dout[28]),
		.DO27(dout[27]),
		.DO26(dout[26]),
		.DO25(dout[25]),
		.DO24(dout[24]),
		.DO23(dout[23]),
		.DO22(dout[22]),
		.DO21(dout[21]),
		.DO20(dout[20]),
		.DO19(dout[19]),
		.DO18(dout[18]),
		.DO17(dout[17]),
		.DO16(dout[16]),
		.DO15(dout[15]),
		.DO14(dout[14]),
		.DO13(dout[13]),
		.DO12(dout[12]),
		.DO11(dout[11]),
		.DO10(dout[10]),
		.DO9(dout[9]),
		.DO8(dout[8]),
		.DO7(dout[7]),
		.DO6(dout[6]),
		.DO5(dout[5]),
		.DO4(dout[4]),
		.DO3(dout[3]),
		.DO2(dout[2]),
		.DO1(dout[1]),
		.DO0(dout[0]),
		.DI71(wdata[71]),
		.DI70(wdata[70]),
		.DI69(wdata[69]),
		.DI68(wdata[68]),
		.DI67(wdata[67]),
		.DI66(wdata[66]),
		.DI65(wdata[65]),
		.DI64(wdata[64]),
		.DI63(wdata[63]),
		.DI62(wdata[62]),
		.DI61(wdata[61]),
		.DI60(wdata[60]),
		.DI59(wdata[59]),
		.DI58(wdata[58]),
		.DI57(wdata[57]),
		.DI56(wdata[56]),
		.DI55(wdata[55]),
		.DI54(wdata[54]),
		.DI53(wdata[53]),
		.DI52(wdata[52]),
		.DI51(wdata[51]),
		.DI50(wdata[50]),
		.DI49(wdata[49]),
		.DI48(wdata[48]),
		.DI47(wdata[47]),
		.DI46(wdata[46]),
		.DI45(wdata[45]),
		.DI44(wdata[44]),
		.DI43(wdata[43]),
		.DI42(wdata[42]),
		.DI41(wdata[41]),
		.DI40(wdata[40]),
		.DI39(wdata[39]),
		.DI38(wdata[38]),
		.DI37(wdata[37]),
		.DI36(wdata[36]),
		.DI35(wdata[35]),
		.DI34(wdata[34]),
		.DI33(wdata[33]),
		.DI32(wdata[32]),
		.DI31(wdata[31]),
		.DI30(wdata[30]),
		.DI29(wdata[29]),
		.DI28(wdata[28]),
		.DI27(wdata[27]),
		.DI26(wdata[26]),
		.DI25(wdata[25]),
		.DI24(wdata[24]),
		.DI23(wdata[23]),
		.DI22(wdata[22]),
		.DI21(wdata[21]),
		.DI20(wdata[20]),
		.DI19(wdata[19]),
		.DI18(wdata[18]),
		.DI17(wdata[17]),
		.DI16(wdata[16]),
		.DI15(wdata[15]),
		.DI14(wdata[14]),
		.DI13(wdata[13]),
		.DI12(wdata[12]),
		.DI11(wdata[11]),
		.DI10(wdata[10]),
		.DI9(wdata[9]),
		.DI8(wdata[8]),
		.DI7(wdata[7]),
		.DI6(wdata[6]),
		.DI5(wdata[5]),
		.DI4(wdata[4]),
		.DI3(wdata[3]),
		.DI2(wdata[2]),
		.DI1(wdata[1]),
		.DI0(wdata[0]),
		.AA4(wa[4]),
		.AA3(wa[3]),
		.AA2(wa[2]),
		.AA1(wa[1]),
		.AA0(wa[0]),
		.AB4(ra[4]),
		.AB3(ra[3]),
		.AB2(ra[2]),
		.AB1(ra[1]),
		.AB0(ra[0]),
		.CSA(csa),
		.CSB(csb),
		.BEA(clkb),
		.BEB(clkb),
		.TBEA(1'b0),
		.TBEB(1'b0),
		.TEST(1'b0),
		.BUB(1'b1)
		);

`endif

endmodule