// $Id: cg.v,v 1.1 2002/05/21 23:55:43 berndt Exp $

`timescale 1ns/100ps

module cg(clock, reset_l);

`include "reality.vh"

// clock generator controls
parameter RAMBUS_CLOCK_PERIOD	= 16.0;  // 250 MHz Rambus
// parameter RAMBUS_CLOCK_PERIOD	= 5.0;  // 200 MHz Rambus
parameter RESET_ACTIVE_DELAY	= 20; // system clocks
parameter RESET_IDLE_DELAY	= 2000; // system clocks

output clock;
output reset_l;

reg reset_l;
reg bus_clk;
integer clock_count;

always #(RAMBUS_CLOCK_PERIOD / 2) bus_clk = ~bus_clk;

assign clock = bus_clk;
always @(posedge clock) clock_count <= reset_l ? clock_count + 1 : 0;

initial begin
$dumpvars;
	// wait for clock
	bus_clk <= HIGH;
	reset_l <= LOW;
	wait (clock)

	repeat (RESET_ACTIVE_DELAY) @(posedge clock);
	reset_l <= HIGH;
	repeat (RESET_IDLE_DELAY) @(posedge clock);
//$finish;
	reset_l <= LOW;
	repeat (RESET_ACTIVE_DELAY) @(posedge clock);
	reset_l <= HIGH;
	end

endmodule