// $Id: cgg.v,v 1.1 2002/05/21 23:55:43 berndt Exp $

`timescale 1ns/100ps

module cgg(stopgclk, clk, gclk, reset_l);

`include "reality.vh"

// clock generator controls
parameter CLOCK_PERIOD = 16;

input stopgclk;
output clk;
output gclk;
output reset_l;

reg clk;
reg gclk;
reg reset_l;
reg mclk;

always #(CLOCK_PERIOD / 2) mclk = ~mclk;

initial mclk = HIGH;

initial begin
	reset_l = LOW;
	repeat (10) @(posedge mclk);
	reset_l <= HIGH;
	end

always @(mclk) begin
	if (mclk) begin
		clk = HIGH;
		gclk = ~stopgclk;
		end
	else begin
		clk = LOW;
		gclk = LOW;
		end
	end
endmodule