rdp_dummy.v
1.45 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
// rdp_dummy.v v1 Frank Berndt
// rdp dummy for speeding up the simulator;
// using rdp_dummy will hang the simulator;
// :set tabstop=4
`timescale 1ns/1ns
module rdp_dummy (
clk, gclk, reset_l,
cbus_read_enable, cbus_write_enable,
cbus_select, cbus_command,
xbus_cs_data, xbus_cs_valid,
flush, freeze, unfreeze,
grant, start, finish, read_grant,
dma_write_enable, dma_read_enable,
cs_xbus_req, start_gclk,
rdramreq, read_request,
cmd_busy, pipe_busy, tmem_busy,
cbus_din, dbus_din, ebus_din,
cbus_dout, dbus_dout, ebus_dout
);
input clk;
input gclk;
input reset_l;
input cbus_read_enable;
input cbus_write_enable;
input [1:0] cbus_select;
input [2:0] cbus_command;
input [63:0] xbus_cs_data;
input xbus_cs_valid;
input flush;
input freeze;
input unfreeze;
input grant;
input start;
input finish;
input read_grant;
input dma_write_enable;
input dma_read_enable;
output cs_xbus_req;
output start_gclk;
output rdramreq;
output read_request;
output cmd_busy;
output pipe_busy;
output tmem_busy;
output [31:0] cbus_dout;
output [63:0] dbus_dout;
output [7:0] ebus_dout;
input [31:0] cbus_din;
input [63:0] dbus_din;
input [7:0] ebus_din;
initial
$display("%M: rdp not compiled in");
assign cs_xbus_req = 0;
assign start_gclk = 0;
assign rdramreq = 0;
assign read_request = 0;
assign cmd_busy = 0;
assign pipe_busy = 0;
assign tmem_busy = 0;
assign cbus_dout = 32'b0;
assign dbus_dout = 64'b0;
assign ebus_dout = 8'b0;
endmodule