module AddrOut (
	memclk,
	Reset,
	Bk0WCAS,
	Bk0RCAS,
	Bk0PRAS,
	Bk0APCAS,
	Bk0RAS,
	Bk0D,
	Bk0I,
	Bk0XCnt,
	Bk0Addr,
	Bk0M36,
	Bk1WCAS,
	Bk1RCAS,
	Bk1PRAS,
	Bk1APCAS,
	Bk1RAS,
	Bk1D,
	Bk1I,
	Bk1XCnt,
	Bk1Addr,
	Bk1M36,
	Bk2WCAS,
	Bk2RCAS,
	Bk2PRAS,
	Bk2APCAS,
	Bk2RAS,
	Bk2D,
	Bk2I,
	Bk2XCnt,
	Bk2Addr,
	Bk2M36,
	Bk3WCAS,
	Bk3RCAS,
	Bk3PRAS,
	Bk3APCAS,
	Bk3RAS,
	Bk3D,
	Bk3I,
	Bk3XCnt,
	Bk3Addr,
	Bk3M36,
	StR1,
	Init_Ref,
	Init_Pre,
	Init_Mod,
	CDataIn,
	XMem,

	RA,
	BA,
	CS,
	RAS,
	CAS,
	WE
	);

	input		memclk;
	input		Reset;

	input		Bk0WCAS;
	input		Bk0RCAS;
	input		Bk0PRAS;
	input		Bk0APCAS;
	input		Bk0RAS;
	input		Bk0D;
	input		Bk0I;
	input	[3:0]	Bk0XCnt;
	input	[27:0]	Bk0Addr;
	input		Bk0M36;

	input		Bk1WCAS;
	input		Bk1RCAS;
	input		Bk1PRAS;
	input		Bk1APCAS;
	input		Bk1RAS;
	input		Bk1D;
	input		Bk1I;
	input	[3:0]	Bk1XCnt;
	input	[27:0]	Bk1Addr;
	input		Bk1M36;

	input		Bk2WCAS;
	input		Bk2RCAS;
	input		Bk2PRAS;
	input		Bk2APCAS;
	input		Bk2RAS;
	input		Bk2D;
	input		Bk2I;
	input	[3:0]	Bk2XCnt;
	input	[27:0]	Bk2Addr;
	input		Bk2M36;

	input		Bk3WCAS;
	input		Bk3RCAS;
	input		Bk3PRAS;
	input		Bk3APCAS;
	input		Bk3RAS;
	input		Bk3D;
	input		Bk3I;
	input	[3:0]	Bk3XCnt;
	input	[27:0]	Bk3Addr;
	input		Bk3M36;
	input		StR1;
	input		Init_Ref;
	input		Init_Pre;
	input		Init_Mod;
	input	[14:0]	CDataIn;
	input		XMem;

	output	[12:0]	RA;
	output	[1:0]	BA;
	output		CS;
	output		RAS;
	output		CAS;
	output		WE;

	wire	Bk0Sel = Bk0WCAS | Bk0RCAS | Bk0PRAS | Bk0RAS;
	wire	Bk1Sel = Bk1WCAS | Bk1RCAS | Bk1PRAS | Bk1RAS;
	wire	Bk2Sel = Bk2WCAS | Bk2RCAS | Bk2PRAS | Bk2RAS;
	wire	Bk3Sel = Bk3WCAS | Bk3RCAS | Bk3PRAS | Bk3RAS;

	wire	[27:0]	Addr   = {28{Bk0Sel}} & Bk0Addr
			       | {28{Bk1Sel}} & Bk1Addr
			       | {28{Bk2Sel}} & Bk2Addr
			       | {28{Bk3Sel}} & Bk3Addr;

	wire	[3:0]	XCnt   = {4{Bk0Sel}} & Bk0XCnt
			       | {4{Bk1Sel}} & Bk1XCnt
			       | {4{Bk2Sel}} & Bk2XCnt
			       | {4{Bk3Sel}} & Bk3XCnt;

	wire		D      = Bk0Sel & Bk0D
			       | Bk1Sel & Bk1D
			       | Bk2Sel & Bk2D
			       | Bk3Sel & Bk3D;

	wire		I      = Bk0Sel & Bk0I
			       | Bk1Sel & Bk1I
			       | Bk2Sel & Bk2I
			       | Bk3Sel & Bk3I;

	wire		M36    = Bk0Sel & Bk0M36
			       | Bk1Sel & Bk1M36
			       | Bk2Sel & Bk2M36
			       | Bk3Sel & Bk3M36;

	wire		PRAS = Bk3PRAS | Bk2PRAS | Bk1PRAS | Bk0PRAS;

	wire		CS =  Bk3Sel | Bk2Sel | Bk1Sel | Bk0Sel | StR1;

	wire		RAS = Bk3RAS | Bk2RAS | Bk1RAS | Bk0RAS | PRAS | StR1;

	wire		RCAS = Bk3RCAS | Bk2RCAS | Bk1RCAS | Bk0RCAS;

	wire		WCAS = Bk3WCAS | Bk2WCAS | Bk1WCAS | Bk0WCAS;

	wire		APCAS = Bk3APCAS | Bk2APCAS | Bk1APCAS | Bk0APCAS;

	wire		CAS = RCAS | WCAS | StR1 & ~Init_Pre;

	wire		WE = WCAS |  PRAS | StR1 & (Init_Mod | Init_Pre);


	wire	[6:4]	M36DWAddr = I ? (Addr[6:4] ^ XCnt[2:0])
				      : (D ? ({1'b0,Addr[6:4]} - XCnt) 
				           : ({1'b0,Addr[6:4]} + XCnt));

	wire	[6:3]	M64DWAddr = I ? (Addr[6:3] ^ XCnt[3:0])
				      : (D ? ({1'b0,Addr[6:3]} - XCnt) 
				           : ({1'b0,Addr[6:3]} + XCnt));

	wire	[6:3]	DWAddr = M36 ? {M36DWAddr,1'b0}
				     :  M64DWAddr;

	wire		AutoPrecharge = APCAS;

	wire	[12:0]	RowAddr = StR1 ? (Init_Pre ? {13{1'b1}}
					 	   : CDataIn[12:0])
				       : PRAS ? {13{1'b0}} : {XMem & Addr[25],
							      Addr[23:22], 
							      Addr[20:11]};

	wire	[12:0]	ColAddr = XMem ? {1'b0,			
				   	  Addr[27],		//Col A11
				   	  AutoPrecharge,	//Col A10
				   	  Addr[26],		//Col A9
					  Addr[24],		//Col A8
				   	  Addr[10:8],
				   	  DWAddr,
				   	  1'b0}
				       : {4'b0000,
				   	  AutoPrecharge,	//Col A8
				   	  Addr[10:8],
				   	  DWAddr,
				   	  1'b0};

	wire	[1:0]	BA = StR1 ? CDataIn[14:13]
				  : {(Bk3Sel | Bk2Sel),(Bk3Sel | Bk1Sel)};

	wire	[12:0]	RA = {13{ RAS}} & RowAddr
			   | {13{RCAS}} & ColAddr
			   | {13{WCAS}} & ColAddr;


endmodule