module ByteMask (
	memclk,
	Reset,
	CBusMask,
	Bk0WCAS,
	Bk0M,
	Bk0D,
	Bk0Length,
	Bk0Addr,
	Bk0XCnt,
	Bk1WCAS,
	Bk1M,
	Bk1D,
	Bk1Length,
	Bk1Addr,
	Bk1XCnt,
	Bk2WCAS,
	Bk2M,
	Bk2D,
	Bk2Length,
	Bk2Addr,
	Bk2XCnt,
	Bk3WCAS,
	Bk3M,
	Bk3D,
	Bk3Length,
	Bk3Addr,
	Bk3XCnt,
	M36WD0,
	
	MaskOut
	);

	input		memclk;
	input		Reset;
	input	[63:0]	CBusMask;
	input		Bk0WCAS;
	input		Bk0M;
	input		Bk0D;
	input	[6:0]	Bk0Length;
	input	[3:0]	Bk0Addr;
	input	[3:0]	Bk0XCnt;
	input		Bk1WCAS;
	input		Bk1M;
	input		Bk1D;
	input	[6:0]	Bk1Length;
	input	[3:0]	Bk1Addr;
	input	[3:0]	Bk1XCnt;
	input		Bk2WCAS;
	input		Bk2M;
	input		Bk2D;
	input	[6:0]	Bk2Length;
	input	[3:0]	Bk2Addr;
	input	[3:0]	Bk2XCnt;
	input		Bk3WCAS;
	input		Bk3M;
	input		Bk3D;
	input	[6:0]	Bk3Length;
	input	[3:0]	Bk3Addr;
	input	[3:0]	Bk3XCnt;
	input		M36WD0;

	output	[7:0]	MaskOut;

	wire	WCAS0	= Bk3WCAS | Bk2WCAS | Bk1WCAS | Bk0WCAS;

	reg	WCAS1;

	always @(posedge memclk)
			WCAS1 <= WCAS0;

	wire	[6:0]	Length = {7{Bk0WCAS}} & Bk0Length
			       | {7{Bk1WCAS}} & Bk1Length
			       | {7{Bk2WCAS}} & Bk2Length
			       | {7{Bk3WCAS}} & Bk3Length;

	wire	[2:0]	Addr   
		       = {3{ M36WD0 & Bk0WCAS}} & {Bk0Addr[3],Bk0Addr[1:0]}
		       | {3{ M36WD0 & Bk1WCAS}} & {Bk1Addr[3],Bk1Addr[1:0]}
		       | {3{ M36WD0 & Bk2WCAS}} & {Bk2Addr[3],Bk2Addr[1:0]}
		       | {3{ M36WD0 & Bk3WCAS}} & {Bk3Addr[3],Bk3Addr[1:0]}
		       | {3{~M36WD0 & Bk0WCAS}} & {Bk0Addr[2:0]}
		       | {3{~M36WD0 & Bk1WCAS}} & {Bk1Addr[2:0]}
		       | {3{~M36WD0 & Bk2WCAS}} & {Bk2Addr[2:0]}
		       | {3{~M36WD0 & Bk3WCAS}} & {Bk3Addr[2:0]};

	wire	[3:0]	XCnt   = {4{Bk0WCAS}} & Bk0XCnt
			       | {4{Bk1WCAS}} & Bk1XCnt
			       | {4{Bk2WCAS}} & Bk2XCnt
			       | {4{Bk3WCAS}} & Bk3XCnt;

	wire		M      = Bk0WCAS & Bk0M
			       | Bk1WCAS & Bk1M
			       | Bk2WCAS & Bk2M
			       | Bk3WCAS & Bk3M;

	wire		D      = Bk0WCAS & Bk0D
			       | Bk1WCAS & Bk1D
			       | Bk2WCAS & Bk2D
			       | Bk3WCAS & Bk3D;

	reg	[7:0]	up_FirstMask;
	reg	[7:0]	up_LastMask;

	reg	[7:0]	dn_FirstMask;
	reg	[7:0]	dn_LastMask;

	wire	[7:0]	FirstMask = up_FirstMask;
	wire	[7:0]	LastMask  = up_LastMask;
//	wire	[7:0]	FirstMask = D ? dn_FirstMask : up_FirstMask;
//	wire	[7:0]	LastMask  = D ? dn_LastMask  : up_LastMask;

	wire	[7:0]	Only1Mask = FirstMask & LastMask;

	wire	OnlyOne = (Length[6:3]==4'b0);

	wire	First   =~OnlyOne &  (XCnt==4'b0);

	wire	Last    =~OnlyOne &  (XCnt==Length[6:3]);

	wire	Full	=~OnlyOne & ~(First | Last);

	reg	[7:0]	up_VecMask;
	reg	[7:0]	dn_VecMask;

//	wire	[7:0]	VecMask = D ? dn_VecMask : up_VecMask;
	wire	[7:0]	VecMask = up_VecMask;

	wire	[7:0]	DWMask  = {8{OnlyOne &  M}} &      VecMask// & Only1Mask
				| {8{First   &  M}} &      VecMask// & FirstMask
				| {8{Last    &  M}} &      VecMask// & LastMask
				| {8{Full    &  M}} &      VecMask 
			        | {8{OnlyOne & ~M}} &    Only1Mask
			        | {8{First   & ~M}} &    FirstMask
			        | {8{Last    & ~M}} &     LastMask
			        | {8{Full    & ~M}} &  8'b11111111;

	reg	[7:0]	W1Mask;

	wire	[7:0]	    W0Mask  = WCAS0 ? (M36WD0 ? {2{DWMask[7:4]}}
						      :     DWMask[7:0]) 
					    : 8'h00;

	wire	[7:0]	nxt_W1Mask  = WCAS0 ? (M36WD0 ? {2{DWMask[3:0]}} 
						      :    8'h00)
					    : W1Mask;

	always @(posedge memclk)
			W1Mask <= nxt_W1Mask;

	wire	[7:0]	nxt_MaskOut = WCAS1 ? W1Mask : W0Mask;

	reg	[7:0]	MaskOut;	// Invert mask to match
					// dram defination 

	always @(posedge memclk)
			MaskOut <= ~nxt_MaskOut;

	always @(Addr)
	casex(Addr)		// 
	3'h0:	up_FirstMask = 8'b11111111;
	3'h1:	up_FirstMask = 8'b01111111;
	3'h2:	up_FirstMask = 8'b00111111;
	3'h3:	up_FirstMask = 8'b00011111;
	3'h4:	up_FirstMask = 8'b00001111;
	3'h5:	up_FirstMask = 8'b00000111;
	3'h6:	up_FirstMask = 8'b00000011;
	3'h7:	up_FirstMask = 8'b00000001;
	endcase

	always @(Length)
	casex(Length[2:0])	// 
	4'h0:	up_LastMask = 8'b10000000;
	4'h1:	up_LastMask = 8'b11000000;
	4'h2:	up_LastMask = 8'b11100000;
	4'h3:	up_LastMask = 8'b11110000;
	4'h4:	up_LastMask = 8'b11111000;
	4'h5:	up_LastMask = 8'b11111100;
	4'h6:	up_LastMask = 8'b11111110;
	4'h7:	up_LastMask = 8'b11111111;
	endcase

	always @(Addr)
	casex(Addr)		// 
	4'h0:	dn_FirstMask = 8'b10000000;
	4'h1:	dn_FirstMask = 8'b11000000;
	4'h2:	dn_FirstMask = 8'b11100000;
	4'h3:	dn_FirstMask = 8'b11110000;
	4'h4:	dn_FirstMask = 8'b11111000;
	4'h5:	dn_FirstMask = 8'b11111100;
	4'h6:	dn_FirstMask = 8'b11111110;
	4'h7:	dn_FirstMask = 8'b11111111;
	endcase

	always @(Length)
	casex(Length[2:0])	// 
	3'h0:	dn_LastMask = 8'b11111111;
	3'h1:	dn_LastMask = 8'b01111111;
	3'h2:	dn_LastMask = 8'b00111111;
	3'h3:	dn_LastMask = 8'b00011111;
	3'h4:	dn_LastMask = 8'b00001111;
	3'h5:	dn_LastMask = 8'b00000111;
	3'h6:	dn_LastMask = 8'b00000011;
	3'h7:	dn_LastMask = 8'b00000001;
	endcase

	always @(CBusMask or XCnt[2:0])
	casex(XCnt[2:0])	// 
	3'h0:	up_VecMask = {CBusMask[56],CBusMask[57],CBusMask[58],CBusMask[59],
			   CBusMask[60],CBusMask[61],CBusMask[62],CBusMask[63]};
	3'h1:	up_VecMask = {CBusMask[48],CBusMask[49],CBusMask[50],CBusMask[51],
			   CBusMask[52],CBusMask[53],CBusMask[54],CBusMask[55]};
	3'h2:	up_VecMask = {CBusMask[40],CBusMask[41],CBusMask[42],CBusMask[43],
			   CBusMask[44],CBusMask[45],CBusMask[46],CBusMask[47]};
	3'h3:	up_VecMask = {CBusMask[32],CBusMask[33],CBusMask[34],CBusMask[35],
			   CBusMask[36],CBusMask[37],CBusMask[38],CBusMask[39]};
	3'h4:	up_VecMask = {CBusMask[24],CBusMask[25],CBusMask[26],CBusMask[27],
			   CBusMask[28],CBusMask[29],CBusMask[30],CBusMask[31]};
	3'h5:	up_VecMask = {CBusMask[16],CBusMask[17],CBusMask[18],CBusMask[19],
			   CBusMask[20],CBusMask[21],CBusMask[22],CBusMask[23]};
	3'h6:	up_VecMask = {CBusMask[ 8],CBusMask[ 9],CBusMask[10],CBusMask[11],
			   CBusMask[12],CBusMask[13],CBusMask[14],CBusMask[15]};
	3'h7:	up_VecMask = {CBusMask[ 0],CBusMask[ 1],CBusMask[ 2],CBusMask[ 3],
			   CBusMask[ 4],CBusMask[ 5],CBusMask[ 6],CBusMask[ 7]};
	endcase

	always @(CBusMask or XCnt[2:0])
	casex(XCnt[2:0])	// 
	3'h0:	dn_VecMask = {CBusMask[63:56]};
	3'h1:	dn_VecMask = {CBusMask[55:48]};
	3'h2:	dn_VecMask = {CBusMask[47:40]};
	3'h3:	dn_VecMask = {CBusMask[39:32]};
	3'h4:	dn_VecMask = {CBusMask[31:24]};
	3'h5:	dn_VecMask = {CBusMask[23:16]};
	3'h6:	dn_VecMask = {CBusMask[15:8]};
	3'h7:	dn_VecMask = {CBusMask[7:0]};
	endcase

endmodule