rspWrap.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: rspWrap.v,v 1.3 2002/11/17 19:55:48 berndt Exp $
// rspWrap.v: the world outside the rsp.
`timescale 1ns / 10ps
module clock(clk);
output clk;
reg clk;
initial
#2 clk = 1;
always
#8 clk = ~ clk;
endmodule
module rspWrap();
reg reset_l;
wire clk;
integer cycleCount;
integer i;
// DMA-related IO
reg frozen;
reg sp_cbus_read_enable;
reg sp_cbus_write_enable;
reg mem_cbus_write_enable; // *** Use for CPU read of mems
reg cmd_cbus_read_enable;
reg cmd_cbus_write_enable;
reg [1:0] cbus_select;
reg [2:0] cbus_command;
reg dma_start;
reg dma_last;
reg sp_dma_grant;
reg sp_read_grant;
reg cmd_dma_grant;
reg cmd_read_grant;
reg sp_dbus_read_enable;
reg sp_dbus_write_enable;
reg cbuf_ready;
reg cmd_busy; // DP CMDBUF is not empty
reg pipe_busy; // DP pipeline is active
reg tmem_busy; // DP TMEM is loading
wire [31:0] cbus_data;
wire [63:0] dbus_data;
wire [63:0] xbus_data;
wire sp_dma_request;
wire cmd_dma_request;
wire cmd_read_request;
wire sp_read_request;
wire mem_read_request;
wire cbuf_write;
task initDMA;
begin
frozen = 1'b0;
sp_cbus_read_enable = 1'b1;
sp_cbus_write_enable = 1'b0;
mem_cbus_write_enable = 1'b0;
cmd_cbus_read_enable = 1'b1;
cmd_cbus_write_enable = 1'b0;
cbus_select = 2'b0;
cbus_command = 3'b0;
dma_start = 0;
dma_last = 0;
sp_dma_grant = 0;
sp_read_grant = 0;
cmd_dma_grant = 0;
cmd_read_grant = 0;
sp_dbus_read_enable = 0;
sp_dbus_write_enable = 0;
cbuf_ready = 0;
cmd_busy = 0;
pipe_busy = 0;
tmem_busy = 0;
end
endtask
task initSURFile;
begin
for (i=0; i<16; i=i+1) begin
rsp.su.sudp.suRFile_i.mem[i] = i;
end
rsp.su.sudp.suRFile_i.mem[0] = 32'hb00b0094;
end
endtask
task initVURFile;
begin
for (i=0; i<32; i=i+1) begin
rsp.vu.vusl01.vudp0.vdpregfile_i.mem[i] = i*16;
rsp.vu.vusl01.vudp1.vdpregfile_i.mem[i] = (i*16)+1;
rsp.vu.vusl23.vudp0.vdpregfile_i.mem[i] = (i*16)+2;
rsp.vu.vusl23.vudp1.vdpregfile_i.mem[i] = (i*16)+3;
rsp.vu.vusl45.vudp0.vdpregfile_i.mem[i] = (i*16)+4;
rsp.vu.vusl45.vudp1.vdpregfile_i.mem[i] = (i*16)+5;
rsp.vu.vusl67.vudp0.vdpregfile_i.mem[i] = (i*16)+6;
rsp.vu.vusl67.vudp1.vdpregfile_i.mem[i] = (i*16)+7;
end
end
endtask
task initIMem;
begin
$readmemh("idata", rsp.imem.sram.memory., 0);
end
endtask
// ddata 16 byte word is numbered MSB to LSB: ddata0, ddata1, ... ddata15
// dmem model 16 byte word is numbered MSB to LSB:
// high.prim7, high.prim6, ... high.prim0, low.prim7, ... low.prim0
task initDMem;
begin
/* $readmemh("d_0.dhex", rsp.dmemx2.dmemHigh.ram_prim7, 0);
$readmemh("d_1.dhex", rsp.dmemx2.dmemHigh.ram_prim6, 0);
$readmemh("d_2.dhex", rsp.dmemx2.dmemHigh.ram_prim5, 0);
$readmemh("d_3.dhex", rsp.dmemx2.dmemHigh.ram_prim4, 0);
$readmemh("d_4.dhex", rsp.dmemx2.dmemHigh.ram_prim3, 0);
$readmemh("d_5.dhex", rsp.dmemx2.dmemHigh.ram_prim2, 0);
$readmemh("d_6.dhex", rsp.dmemx2.dmemHigh.ram_prim1, 0);
$readmemh("d_7.dhex", rsp.dmemx2.dmemHigh.ram_prim0, 0);
$readmemh("d_8.dhex", rsp.dmemx2.dmemLow.ram_prim7, 0);
$readmemh("d_9.dhex", rsp.dmemx2.dmemLow.ram_prim6, 0);
$readmemh("d_a.dhex", rsp.dmemx2.dmemLow.ram_prim5, 0);
$readmemh("d_b.dhex", rsp.dmemx2.dmemLow.ram_prim4, 0);
$readmemh("d_c.dhex", rsp.dmemx2.dmemLow.ram_prim3, 0);
$readmemh("d_d.dhex", rsp.dmemx2.dmemLow.ram_prim2, 0);
$readmemh("d_e.dhex", rsp.dmemx2.dmemLow.ram_prim1, 0);
$readmemh("d_f.dhex", rsp.dmemx2.dmemLow.ram_prim0, 0); */
end
endtask
clock clock(clk);
rsp rsp(
.clk (clk),
.reset_l (reset_l),
// DMA-related IO
.frozen (frozen),
.sp_cbus_read_enable (sp_cbus_read_enable),
.sp_cbus_write_enable (sp_cbus_write_enable),
.mem_cbus_write_enable (mem_cbus_write_enable),
.cmd_cbus_read_enable (cmd_cbus_read_enable),
.cmd_cbus_write_enable (cmd_cbus_write_enable),
.cbus_select (cbus_select),
.cbus_command (cbus_command),
.dma_start (dma_start),
.dma_last (dma_last),
.sp_dma_grant (sp_dma_grant),
.sp_read_grant (sp_read_grant),
.cmd_dma_grant (cmd_dma_grant),
.cmd_read_grant (cmd_read_grant),
.cbuf_ready (cbuf_ready),
.sp_dma_request (sp_dma_request),
.sp_read_request (sp_read_request),
.mem_read_request (mem_read_request),
.cmd_dma_request (cmd_dma_request),
.cmd_read_request (cmd_read_request),
.sp_dbus_read_enable (sp_dbus_read_enable),
.sp_dbus_write_enable (sp_dbus_write_enable),
.cbuf_write (cbuf_write),
.cbus_data (cbus_data),
.dbus_data (dbus_data),
.xbus_data (xbus_data)
);
initial begin
/* $write ("dmem[16]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[1], rsp.dmemx2.dmemHigh.ram_prim6[1],
rsp.dmemx2.dmemHigh.ram_prim5[1], rsp.dmemx2.dmemHigh.ram_prim4[1],
rsp.dmemx2.dmemHigh.ram_prim3[1], rsp.dmemx2.dmemHigh.ram_prim2[1],
rsp.dmemx2.dmemHigh.ram_prim1[1], rsp.dmemx2.dmemHigh.ram_prim0[1],
rsp.dmemx2.dmemLow.ram_prim7[1], rsp.dmemx2.dmemLow.ram_prim6[1],
rsp.dmemx2.dmemLow.ram_prim5[1], rsp.dmemx2.dmemLow.ram_prim4[1],
rsp.dmemx2.dmemLow.ram_prim3[1], rsp.dmemx2.dmemLow.ram_prim2[1],
rsp.dmemx2.dmemLow.ram_prim1[1], rsp.dmemx2.dmemLow.ram_prim0[1] */
);
initDMA;
initSURFile;
initVURFile;
initDMem;
initIMem;
reset_l = 0;
// force rsp.io_mem_dma.single_step = 0;
$dumpvars;
#30 reset_l = 1; // *** need setup time on reset_l!
end // initial
always @(posedge clk) begin
if (!reset_l) begin
cycleCount = 0;
end
else begin
cycleCount = cycleCount+1;
end
end
always @(negedge clk) begin
#2 $write ("time: %0t\tinst: %h\n", $time, rsp.su.suctl.su_inst);
/* $write ("imem[0]: %h \n",
rsp.imem.ram_prim[0]);
$write ("dmem[0]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[0], rsp.dmemx2.dmemHigh.ram_prim6[0],
rsp.dmemx2.dmemHigh.ram_prim5[0], rsp.dmemx2.dmemHigh.ram_prim4[0],
rsp.dmemx2.dmemHigh.ram_prim3[0], rsp.dmemx2.dmemHigh.ram_prim2[0],
rsp.dmemx2.dmemHigh.ram_prim1[0], rsp.dmemx2.dmemHigh.ram_prim0[0],
rsp.dmemx2.dmemLow.ram_prim7[0], rsp.dmemx2.dmemLow.ram_prim6[0],
rsp.dmemx2.dmemLow.ram_prim5[0], rsp.dmemx2.dmemLow.ram_prim4[0],
rsp.dmemx2.dmemLow.ram_prim3[0], rsp.dmemx2.dmemLow.ram_prim2[0],
rsp.dmemx2.dmemLow.ram_prim1[0], rsp.dmemx2.dmemLow.ram_prim0[0]
);
$write ("dmem[16]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[1], rsp.dmemx2.dmemHigh.ram_prim6[1],
rsp.dmemx2.dmemHigh.ram_prim5[1], rsp.dmemx2.dmemHigh.ram_prim4[1],
rsp.dmemx2.dmemHigh.ram_prim3[1], rsp.dmemx2.dmemHigh.ram_prim2[1],
rsp.dmemx2.dmemHigh.ram_prim1[1], rsp.dmemx2.dmemHigh.ram_prim0[1],
rsp.dmemx2.dmemLow.ram_prim7[1], rsp.dmemx2.dmemLow.ram_prim6[1],
rsp.dmemx2.dmemLow.ram_prim5[1], rsp.dmemx2.dmemLow.ram_prim4[1],
rsp.dmemx2.dmemLow.ram_prim3[1], rsp.dmemx2.dmemLow.ram_prim2[1],
rsp.dmemx2.dmemLow.ram_prim1[1], rsp.dmemx2.dmemLow.ram_prim0[1]
);
$write ("dmem[32]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[2], rsp.dmemx2.dmemHigh.ram_prim6[2],
rsp.dmemx2.dmemHigh.ram_prim5[2], rsp.dmemx2.dmemHigh.ram_prim4[2],
rsp.dmemx2.dmemHigh.ram_prim3[2], rsp.dmemx2.dmemHigh.ram_prim2[2],
rsp.dmemx2.dmemHigh.ram_prim1[2], rsp.dmemx2.dmemHigh.ram_prim0[2],
rsp.dmemx2.dmemLow.ram_prim7[2], rsp.dmemx2.dmemLow.ram_prim6[2],
rsp.dmemx2.dmemLow.ram_prim5[2], rsp.dmemx2.dmemLow.ram_prim4[2],
rsp.dmemx2.dmemLow.ram_prim3[2], rsp.dmemx2.dmemLow.ram_prim2[2],
rsp.dmemx2.dmemLow.ram_prim1[2], rsp.dmemx2.dmemLow.ram_prim0[2]
);
$write ("dmem[48]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[3], rsp.dmemx2.dmemHigh.ram_prim6[3],
rsp.dmemx2.dmemHigh.ram_prim5[3], rsp.dmemx2.dmemHigh.ram_prim4[3],
rsp.dmemx2.dmemHigh.ram_prim3[3], rsp.dmemx2.dmemHigh.ram_prim2[3],
rsp.dmemx2.dmemHigh.ram_prim1[3], rsp.dmemx2.dmemHigh.ram_prim0[3],
rsp.dmemx2.dmemLow.ram_prim7[3], rsp.dmemx2.dmemLow.ram_prim6[3],
rsp.dmemx2.dmemLow.ram_prim5[3], rsp.dmemx2.dmemLow.ram_prim4[3],
rsp.dmemx2.dmemLow.ram_prim3[3], rsp.dmemx2.dmemLow.ram_prim2[3],
rsp.dmemx2.dmemLow.ram_prim1[3], rsp.dmemx2.dmemLow.ram_prim0[3]
);*/
$write ("\n");
for (i=0; i<8; i=i+1) begin // display su rfile state
$write ("R%0d: %h\t R%0d: %h\t R%0d: %h\t R%0d: %h\n",
(i*4), rsp.su.sudp.suRFile_i.mem[(i*4)],
(i*4)+1, rsp.su.sudp.suRFile_i.mem[(i*4)+1],
(i*4)+2, rsp.su.sudp.suRFile_i.mem[(i*4)+2],
(i*4)+3, rsp.su.sudp.suRFile_i.mem[(i*4)+3]);
end
$write ("\n");
/*
for (i=0; i<32; i=i+1) begin // display vu rfile state
$write ("V%0d: %h %h %h %h %h %h %h %h\n",
i, rsp.vu.vudp0.vdpregfile_i.mem[i],
rsp.vu.vudp1.vdpregfile_i.mem[i],
rsp.vu.vudp2.vdpregfile_i.mem[i],
rsp.vu.vudp3.vdpregfile_i.mem[i],
rsp.vu.vudp4.vdpregfile_i.mem[i],
rsp.vu.vudp5.vdpregfile_i.mem[i],
rsp.vu.vudp6.vdpregfile_i.mem[i],
rsp.vu.vudp7.vdpregfile_i.mem[i]);
end
$write ("\n");
*/
/*
$write("vector comp code reg: %h\t vector carry out reg: %h\n",
{rsp.vu.vuctl1.vct_cmpcdhi7_ac,rsp.vu.vuctl1.vct_cmpcdhi6_ac,
rsp.vu.vuctl1.vct_cmpcdhi5_ac,rsp.vu.vuctl1.vct_cmpcdhi4_ac,
rsp.vu.vuctl1.vct_cmpcdhi3_ac,rsp.vu.vuctl1.vct_cmpcdhi2_ac,
rsp.vu.vuctl1.vct_cmpcdhi1_ac,rsp.vu.vuctl1.vct_cmpcdhi0_ac,
rsp.vu.vuctl1.vct_cmpcdlo7_ac,rsp.vu.vuctl1.vct_cmpcdlo6_ac,
rsp.vu.vuctl1.vct_cmpcdlo5_ac,rsp.vu.vuctl1.vct_cmpcdlo4_ac,
rsp.vu.vuctl1.vct_cmpcdlo3_ac,rsp.vu.vuctl1.vct_cmpcdlo2_ac,
rsp.vu.vuctl1.vct_cmpcdlo1_ac,rsp.vu.vuctl1.vct_cmpcdlo0_ac},
{rsp.vu.vuctl1.vct_opdneql7_ac,rsp.vu.vuctl1.vct_opdneql6_ac,
rsp.vu.vuctl1.vct_opdneql5_ac,rsp.vu.vuctl1.vct_opdneql4_ac,
rsp.vu.vuctl1.vct_opdneql3_ac,rsp.vu.vuctl1.vct_opdneql2_ac,
rsp.vu.vuctl1.vct_opdneql1_ac,rsp.vu.vuctl1.vct_opdneql0_ac,
rsp.vu.vuctl1.vct_cryout7_ac,rsp.vu.vuctl1.vct_cryout6_ac,
rsp.vu.vuctl1.vct_cryout5_ac,rsp.vu.vuctl1.vct_cryout4_ac,
rsp.vu.vuctl1.vct_cryout3_ac,rsp.vu.vuctl1.vct_cryout2_ac,
rsp.vu.vuctl1.vct_cryout1_ac,rsp.vu.vuctl1.vct_cryout0_ac});
$write ("\n");
*/
$write("dma dmem address: %h\n", rsp.io_mem_dma.master_address);
$write("dma rdram address: %h\n", rsp.io_mem_dma.slave_address);
$write("dma read length: %h\n", rsp.io_mem_dma.length);
end
endmodule