// si.v v1 Frank Berndt
// si top level;
// :set tabstop=4

module si (
	sysclk, reset_l,
	cbus_din, cbus_dout, cbus_select, cbus_command, cbus_write_enable, 
	cbus_read_request, cbus_read_grant,
	dbus_din, dbus_dout, dbus_enable,
	dma_request, dma_grant, dma_start, dma_last, dma_intr,
	jchan_clk, jchan_in, jchan_ena, jchan_oe,
	lctrl_req, lctrl_val, lctrl_but,
	lctrl_x, lctrl_y
);

`include "cbus.vh"

	// module io ports;

	input sysclk;				// system clock;
	input reset_l;				// system reset;

	input [31:0] cbus_din;		// cbus data;
	output [31:0] cbus_dout;	// cbus data;
	input [1:0] cbus_select;	// cbus phase;
	input [2:0] cbus_command;	// cbus command;
	input cbus_write_enable;	// enable cbus drivers;
	output cbus_read_request;	// request cbus response cycle;
	input cbus_read_grant;		// response cycle granted;

	input [63:0] dbus_din;		// dbus data;
	output [63:0] dbus_dout;	// dbus data;
	input dbus_enable;			// enable dbus drivers;
	output dma_request;			// dma request;
	input dma_grant;			// dma granted;
	input dma_start;			// first dbus word valid;
	input dma_last;				// last dbus word valid;
	output dma_intr;			// dma interrupt;

	output jchan_clk;			// joychannel to mi button timer;
	input [3:1] jchan_in;		// joychannel ctrl inputs;
	output [3:1] jchan_ena;		// enable joychannel input regs;
	output [3:1] jchan_oe;		// enable joychannel drivers;
	output lctrl_req;			// request button sample;
	input lctrl_val;			// button sample valid;
	input [13:0] lctrl_but;		// button sample;
	input [1:0] lctrl_x;		// joystick x inputs;
	input [1:0] lctrl_y;		// joystick y inputs;

`define	JCHAN_DIV	7'd31		// default jchan divider, divide by 32;
`define	BCLK_DIV	6'd2		// default button sample clock divider, 1msec;

	// buffer reset for si;

	reg si_reset_l;				// si reset;

	always @(posedge sysclk)
	begin
		si_reset_l <= reset_l;
	end

	// cbus interface;
	// cbus interface controls;
	// decode cbus commands;

	reg [2:0] cbus_cmd;			// cbus cmd register;
	reg [31:0] cbus_in;			// cbus input register;
	wire [31:0] cbus_out;		// cbus output data;
	reg [31:0] cbus_dout;		// cbus output register;
	wire cbus_read;				// cbus read request;
	wire cbus_write;			// cbus write request;

	always @(posedge sysclk)
	begin
		cbus_cmd <= cbus_command;
		cbus_in <= cbus_din;
		cbus_dout <= {32{cbus_write_enable}} & cbus_out;
	end

	assign cbus_read = (cbus_cmd == `CBUS_CMD_READ);
	assign cbus_write = (cbus_cmd == `CBUS_CMD_WRITE);

	// si only responds in si register space;
	// mi intercepts boot space accesses;
	// mi optionally traps on pif ram space;
	// stop access if reset interfered;

	wire [11:0] cbus_id;	// cbus space id;
	wire cbus_si;			// si pio access;
	wire si_read;			// si read request;
	wire si_write;			// si write request;

	assign cbus_id = cbus_in[31:20];
	assign cbus_si = si_reset_l & (cbus_id == `CBUS_SI);

	assign si_read = cbus_si & cbus_read;
	assign si_write = cbus_si & cbus_write;

	// hold on to pio reg or ram address;
	// reset stops any register op in progress;

	reg [4:2] reg_addr;			// register address;
	reg reg_write;				// write to register;
	wire [31:0] reg_wrdata;		// register write data;

	always @(posedge sysclk)
	begin
		if(si_read | si_write)
			reg_addr <= cbus_in[4:2];
		reg_write <= si_write;
	end

	assign reg_wrdata = cbus_in;

	// decode register addresses;

	wire ra_dma_addr;			// access SI_DMA_ADDR;
	wire ra_dma_read;			// access SI_DMA_READ;
	wire ra_dma_write;			// access SI_DMA_WRITE;
	wire ra_status;				// access SI_STATUS;
	wire ra_config;				// acces SI_CONFIG;
	wire ra_ctrl;				// acces SI_CTRL;

	assign ra_dma_addr = (reg_addr == 3'h0);
	assign ra_dma_read = (reg_addr == 3'h1);
	assign ra_ctrl = (reg_addr == 3'h3);
	assign ra_dma_write = (reg_addr == 3'h4);
	assign ra_status = (reg_addr == 3'h6);
	assign ra_config = (reg_addr == 3'h7);

	// decode register reads/writes;

	wire wr_config;			// write SI_CONFIG;
	wire wr_ctrl;			// write SI_CTRL;

	assign wr_config = reg_write & ra_config;
	assign wr_ctrl = reg_write & ra_ctrl;

	// request cbus for response;
	// clear on grant and reset;

	wire si_rrclr;				// read request clear;
	reg cbus_read_request;		// request cbus response;

	assign si_rrclr = si_reset_l & ~cbus_read_grant;

	always @(posedge sysclk)
	begin
		cbus_read_request <= si_rrclr & (cbus_read_request | si_read);
	end

	// compatible si registers;

	reg [25:3] dma_addr;	// dma address;
	reg dma_busy;			// dma busy, status[0];
	reg dma_err;			// dma error, status[3];
	reg dma_intr;			// dma interrupt, status[12];

	// new si registers;

	// joychannel clock divider;
	// programmable divider from sysclk;
	// reset defaults set for N64 compatibility;

	reg [6:0] jchan_div;	// divide configuration;
	reg jchan_slave;		// joychannel slave mode;
	reg [6:0] jchan_cnt;	// counter;
	wire jchan_cntz;		// jchan_cnt is 0;
	reg jchan_clk;			// receive clock (x4 over-sampling);

	assign jchan_cntz = (jchan_cnt == 7'd0);

	always @(posedge sysclk)
	begin
		if(~si_reset_l) begin
			jchan_div <= `JCHAN_DIV;
			jchan_slave <= 0;
		end else if(wr_config) begin
			jchan_div <= reg_wrdata[30:24];
			jchan_slave <= reg_wrdata[31];
		end
		if(~si_reset_l | jchan_cntz)
			jchan_cnt <= jchan_div;
		else
			jchan_cnt <= jchan_cnt - 1;
		jchan_clk <= jchan_cntz;
	end

	// joychannel control register;
	// software must ensure ctrl_rst timing of at least 800usec;
	// keep ctrl #2 and #3 in reset in slave mode;

	reg [1:0] ctrl_rst;		// controller & joychannel bus reset;

	always @(posedge sysclk)
	begin
		if(~si_reset_l)
			ctrl_rst[0] <= 1'b1;
		else if(wr_ctrl)
			ctrl_rst[0] <= reg_wrdata[0];
		ctrl_rst[1] <= ctrl_rst[0] | jchan_slave;
	end

	// local controller registers;

	reg sgl_mode;			// single command error detection mode;
	reg bsmp_en;			// enable button sampling;
	reg [5:0] bclk_div;		// button sample clock divider;

	always @(posedge sysclk)
	begin
		if(~si_reset_l) begin
			sgl_mode <= 1;
			bsmp_en <= 0;
			bclk_div <= `BCLK_DIV;
		end else if(wr_config) begin
			sgl_mode <= reg_wrdata[23];
			bsmp_en <= reg_wrdata[22];
			bclk_div <= reg_wrdata[21:16];
		end
	end

	// cbus write data mux;
	// selects dma address, read length, write length or response data;
	// default to response data, because they toggle the least;
	// si dma now does single dma burst of 32 bytes;

	wire cbus_sel_addr;		// cbus wants dma address;
	wire cbus_sel_len;		// cbus wants dma length;
	wire cbus_sel_data;		// cbus wants response data;
	wire cbus_out_addr;		// cbus wants response data;
	reg dma_read;			// dma read request;
	reg [31:0] rsp_data;	// read response data;
	wire [7:0] dma_delay;	// fixed in ri;

	assign cbus_sel_addr = (cbus_select == `CBUS_SEL_ADDR);
	assign cbus_sel_len = (cbus_select == `CBUS_SEL_LEN);
	assign cbus_sel_data = (cbus_select == `CBUS_SEL_DATA);
	assign cbus_out_addr = cbus_sel_addr | (cbus_sel_data & ra_dma_addr);
	assign dma_delay = 8'd0;

	assign cbus_out = cbus_out_addr? { 6'd0, dma_addr, 3'b000 }
			: cbus_sel_len? { `CBUS_DEV_SI, dma_delay, dma_read, 7'd31 }
			: rsp_data;

	// register and dma control;

	// writes to SI_DMA_READ or SI_DMA_WRITE start si dma;
	// if dma is busy then let the current dma complete and set dma error;
	// keep dma error status across reset for debug;
	// write to status register (any data) clears interrupt and dma error;

	wire dma_set_addr;		// write to dma address reg;
	wire dma_xread;			// execute read dma;
	wire dma_xwrite;		// execute write dma;
	wire dma_x;				// execute dma;
	wire dma_stop;			// stop dma;
	wire dma_over;			// attempt to overwrite busy dma;
	wire dma_conflict;		// dma conflict;
	wire dma_done;			// dma has finished;
	wire clr_sts;			// clear int & error status;
	wire ctrl_sltx;			// start slave transmit;

	assign dma_set_addr = reg_write & ra_dma_addr;
	assign dma_xread = reg_write & ra_dma_read;
	assign dma_xwrite = reg_write & ra_dma_write;
	assign dma_x = dma_xread | dma_xwrite;
	assign dma_stop = ~si_reset_l | dma_done;
	assign dma_over = dma_busy & (dma_set_addr | dma_x);
	assign dma_conflict = dma_busy;
	assign clr_sts = ~si_reset_l | (reg_write & ra_status);
	assign ctrl_sltx = wr_ctrl & reg_wrdata[2] & jchan_slave;

	always @(posedge sysclk)
	begin
		dma_busy <= ~dma_stop & (dma_busy | dma_x);
		dma_err <= ~clr_sts & (dma_err | dma_over);
		dma_intr <= ~clr_sts & (dma_intr | dma_done);
		if( ~dma_conflict & dma_set_addr)
			dma_addr <= reg_wrdata[25:3];
		if( ~dma_conflict & dma_x)
			dma_read <= ra_dma_write;
		else if(ctrl_sltx)
			dma_read <= 1'b0;
	end

	// the controller fsms start on a dma read;
	// the cbus dma is requested when the fsms are done;
	// dma_rel takes care of clearing during reset;
	// do not start controllers on single command error;

	wire sgl_err;			// single command error;
	wire do_start;			// controller start;
	reg ctrl_start;			// start controller fsms;
	wire [3:0] ctrl_busy;	// individual controller busy;
	reg [1:0] any_busy;		// sum of all controller busy;

	assign do_start = ~dma_conflict & dma_xread;

	always @(posedge sysclk)
	begin
		ctrl_start <= ~sgl_err & do_start;
		any_busy[0] <= |ctrl_busy;
		any_busy[1] <= any_busy[0];
	end

	// dbus interface;

	// request cbus dma;
	// request immediately for dram->si dma;
	// request when controller fsms are finished for dram<-si;
	// request immediatedly for single command error response;
	// release request on reset or grant;

	wire dma_req_read;		// request read dma;
	wire dma_req_write;		// request write dma;
	reg dma_request;		// request cbus dma;
	wire dma_rel;			// release dma request;

	assign dma_req_read = (any_busy == 2'b10) | (sgl_err & do_start);
	assign dma_req_write = ~dma_conflict & dma_xwrite;
	assign dma_rel = ~si_reset_l | dma_grant;

	always @(posedge sysclk)
	begin
		dma_request <= ~dma_rel & (dma_request | dma_req_write | dma_req_read);
	end

	// dbus driver interface;

	reg [63:0] dbus_reg;	// dbus input/output register;

	wire [63:0] dbus_dout = dbus_enable ? dbus_reg : 32'b0;

	// dbus interface controls;

	wire [63:0] dbus_out;	// dbus output data;
	reg dbus_read;			// hold dma read data in dbus_reg;
	reg [3:0] dbus_val;		// dbus data valids, burst of 4;

	always @(posedge sysclk)
	begin
		dbus_read <= dma_read;
		dbus_reg <= dbus_read? dbus_din : dbus_out;
		dbus_val[3:0] <= {4{si_reset_l}} & {dbus_val[2:0], dma_start};
	end

	assign dma_done = dbus_val[2];

	// controller dma read data mux;
	// upper byte is 0xff for compatibility with block cmds;
	// return all 1s for single command error;

	wire [55:0] ctrl_rdata, ctrl0_rdata, ctrl1_rdata, ctrl2_rdata, ctrl3_rdata;

	assign ctrl_rdata = {56{sgl_err}}
			| ({56{dbus_val[0]}} & ctrl0_rdata)
			| ({56{dbus_val[1]}} & ctrl1_rdata)
			| ({56{dbus_val[2]}} & ctrl2_rdata)
			| ({56{dbus_val[3]}} & ctrl3_rdata);
	assign dbus_out = { 8'hff, ctrl_rdata };

	// controller dma write enables;

	wire [3:0] ctrl_wrena;	// write to controller;
	wire ctrl_slreq;		// slave request pending;

	assign ctrl_wrena = {4{dma_read}} & dbus_val;

	// instantiate local controller;

	si_lctrl si_ctrl0 (
		.sysclk(sysclk),
		.reset(ctrl_rst[0]),
		.write_data(dbus_reg),
		.write_enable(ctrl_wrena[0]),
		.read_data(ctrl0_rdata),
		.clk(jchan_clk),
		.start(ctrl_start),
		.busy(ctrl_busy[0]),
		.sgl_mode(sgl_mode),
		.sgl_err(sgl_err),
		.b_req(lctrl_req),
		.b_val(lctrl_val),
		.b_but(lctrl_but),
		.b_x(lctrl_x),
		.b_y(lctrl_y),
		.bclk_div(bclk_div),
		.bsmp_en(bsmp_en)
	);

	// instantiate three joychannel controllers;
	// ctrl #2 and #3 are never used as slaves;

	si_jctrl si_ctrl1 (
		.sysclk(sysclk),
		.reset(ctrl_rst[0]),
		.write_data(dbus_reg),
		.write_enable(ctrl_wrena[1]),
		.read_data(ctrl1_rdata),
		.slave(jchan_slave),
		.start(ctrl_start),
		.sltx(ctrl_sltx),
		.slreq(ctrl_slreq),
		.busy(ctrl_busy[1]),
		.jchan_clk(jchan_clk),
		.jchan_in(jchan_in[1]),
		.jchan_ena(jchan_ena[1]),
		.jchan_oe(jchan_oe[1])
	);

	si_jctrl si_ctrl2 (
		.sysclk(sysclk),
		.reset(ctrl_rst[1]),
		.write_data(dbus_reg),
		.write_enable(ctrl_wrena[2]),
		.read_data(ctrl2_rdata),
		.slave(1'b0),
		.start(ctrl_start),
		.sltx(1'b0),
		.slreq(),
		.busy(ctrl_busy[2]),
		.jchan_clk(jchan_clk),
		.jchan_in(jchan_in[2]),
		.jchan_ena(jchan_ena[2]),
		.jchan_oe(jchan_oe[2])
	);

	si_jctrl si_ctrl3 (
		.sysclk(sysclk),
		.reset(ctrl_rst[1]),
		.write_data(dbus_reg),
		.write_enable(ctrl_wrena[3]),
		.read_data(ctrl3_rdata),
		.slave(1'b0),
		.start(ctrl_start),
		.sltx(1'b0),
		.slreq(),
		.busy(ctrl_busy[3]),
		.jchan_clk(jchan_clk),
		.jchan_in(jchan_in[3]),
		.jchan_ena(jchan_ena[3]),
		.jchan_oe(jchan_oe[3])
	);

	// cbus response data mux;

	wire [23:0] rsp_config;		// SI_CONFIG response bits;
	wire [7:0] rsp_ctrl;		// SI_CTRL response bits;
	wire [31:0] rsp_status;		// SI_STATUS response bits;

	assign rsp_config = { jchan_slave, jchan_div, sgl_mode, bsmp_en, bclk_div, 8'h00 };
	assign rsp_ctrl = { 5'b00000, ctrl_busy[1], ctrl_slreq, ctrl_rst[0] };
	assign rsp_status = { 16'h0000, 3'b000, dma_intr, 8'h00, dma_err, 2'b00, dma_busy };

	always @(posedge sysclk)
	begin
		rsp_data <= ra_status? rsp_status : { rsp_config, rsp_ctrl };
	end

endmodule