// Module instances modified by /home/rws/workarea/rf/sw/bbplayer/tools/necprimfix 
//
//    32 instances of in01d5 changed to j_in01.
//    16 instances of nd02d2 changed to j_nd02.
//

/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: tc_tilemem.v,v 1.4 2002/11/22 00:34:20 rws Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	tc_tilemem
// description:	Tile Memory module. 8 words x 95 bits
//
// designer:	Tony DeLaurier
// date:	7/22/94
//
////////////////////////////////////////////////////////////////////////


module tc_tilemem (clk, start_gclk, tile_adrs, tile_data, we_tile_size, we_tile_attr, 
		   l_tile, tex_type_2d, tex_size_2d, line_2d, tmem_adrs_2d, 
		   palette_4d, clamp_t_1d, mir_t_1d, mask_t_1d, shift_t, 
		   clamp_s_1d, mir_s_1d, mask_s_1d, shift_s, sl, sh, tl, th);

  input clk, start_gclk;			// RDP gated clock
  input [2:0] tile_adrs;        // tile write address
  input [47:0] tile_data;       // tile input data
  input we_tile_size;           // write enable for tile size data
  input we_tile_attr;           // write enable for tile attribute data
  input [2:0] l_tile;           // tile index into tile memory

  output [2:0] tex_type_2d;   	// tile texel type
  output [1:0] tex_size_2d;   	// tile texel size
  output [8:0] line_2d;         // line width in 64-bit words
  output [8:0] tmem_adrs_2d;    // tmem start address
  output [3:0] palette_4d;      // palette for 4-bit color index
  output clamp_t_1d;            // coord. clamp enabled
  output mir_t_1d;              // enable mirror
  output [3:0] mask_t_1d;       // coord. mask
  output [3:0] shift_t;         // right shift
  output clamp_s_1d;            // coord. clamp enabled
  output mir_s_1d;              // enable mirror
  output [3:0] mask_s_1d;       // coord. mask
  output [3:0] shift_s;         // right shift
  output [11:0] sl;             // tile offset in image space
  output [11:0] sh;             // tile end in image space
  output [11:0] tl;             // tile offset in image space
  output [11:0] th;             // tile end in image space

  reg [2:0] tex_type, 		// tile texel type
	    tex_type_1d, 
	    tex_type_2d;
  reg [1:0] tex_size, 		// tile texel size
	    tex_size_1d, 
	    tex_size_2d;
  reg [8:0] line,		// line width in 64-bit words
	    line_1d, 
	    line_2d;
  reg [8:0] tmem_adrs, 		// tmem start address
	    tmem_adrs_1d, 
	    tmem_adrs_2d;
  reg [3:0] palette, 		// palette for 4-bit color index
	    palette_1d, 
	    palette_2d, 
	    palette_3d, 
	    palette_4d; 
  reg clamp_t, clamp_t_1d;      // coord. clamp enabled
  reg mir_t, mir_t_1d;          // enable mirror
  reg [3:0] mask_t, mask_t_1d;  // coord. mask
  reg [3:0] shift_t;         	// right shift
  reg clamp_s, clamp_s_1d;      // coord. clamp enabled
  reg mir_s, mir_s_1d;          // enable mirror
  reg [3:0] mask_s, mask_s_1d;  // coord. mask
  reg [3:0] shift_s;         	// right shift
  reg [11:0] sl;             	// tile offset in image space
  reg [11:0] sh;             	// tile end in image space
  reg [11:0] tl;             	// tile offset in image space
  reg [11:0] th;             	// tile end in image space

  reg [22:0] memory_attr_msb0;	// attribute memory msb's
  reg [22:0] memory_attr_msb1;
  reg [22:0] memory_attr_msb2;
  reg [22:0] memory_attr_msb3;
  reg [22:0] memory_attr_msb4;
  reg [22:0] memory_attr_msb5;
  reg [22:0] memory_attr_msb6;
  reg [22:0] memory_attr_msb7;

  reg [23:0] memory_attr_lsb0;	// attribute memory lsb's
  reg [23:0] memory_attr_lsb1;
  reg [23:0] memory_attr_lsb2;
  reg [23:0] memory_attr_lsb3;
  reg [23:0] memory_attr_lsb4;
  reg [23:0] memory_attr_lsb5;
  reg [23:0] memory_attr_lsb6;
  reg [23:0] memory_attr_lsb7;

  reg [23:0] memory_size_msb0;	// size memory msb's
  reg [23:0] memory_size_msb1;
  reg [23:0] memory_size_msb2;
  reg [23:0] memory_size_msb3;
  reg [23:0] memory_size_msb4;
  reg [23:0] memory_size_msb5;
  reg [23:0] memory_size_msb6;
  reg [23:0] memory_size_msb7;

  reg [23:0] memory_size_lsb0;	// size memory lsb's
  reg [23:0] memory_size_lsb1;
  reg [23:0] memory_size_lsb2;
  reg [23:0] memory_size_lsb3;
  reg [23:0] memory_size_lsb4;
  reg [23:0] memory_size_lsb5;
  reg [23:0] memory_size_lsb6;
  reg [23:0] memory_size_lsb7;

  // tilemem array internal variables  (MR)
  reg [2:0] tile_adrs_l1;       // tile write address registers
  reg [47:0] tile_data_ireg;    // tile input data registers
  reg  we_tile_attr_l1, we_tile_size_l1; // we registers

  wire [22:0] tile_data_ireg_msb_at;  // tile input data (23-bit)
  wire [23:0] tile_data_ireg_msb_sz;  // tile input data (24-bit)
  wire [23:0] tile_data_ireg_lsb;     // tile input data (24-bit)

  reg [7:0] decode;		// address decode
  wire [7:0] ta_wrd;		// word select tile attribute mem
  wire [7:0] ta_en;		// after gating with gclk

  wire [7:0] ts_wrd;		// word select tile size mem
  wire [7:0] ts_en;		// after gating with gclk

  reg [22:0] rd_data_attr_msb;	// attribute msb's read data
  reg [23:0] rd_data_attr_lsb;	// attribute lsb's read data
  reg [23:0] rd_data_size_msb;	// size msb's read data
  reg [23:0] rd_data_size_lsb;	// size lsb's read data

  // memory data input register
  always @(posedge clk)
   if (start_gclk) begin

      tile_data_ireg <= tile_data;

  end // always

  assign tile_data_ireg_msb_at = tile_data_ireg[46:24];
  assign tile_data_ireg_msb_sz = tile_data_ireg[47:24];
  assign tile_data_ireg_lsb = tile_data_ireg[23:0];

// we and address input latches
// always @(gclk or we_tile_attr or we_tile_size or tile_adrs)
// begin

///   if (!gclk) begin
//     tile_adrs_l1 = tile_adrs;
//     we_tile_attr_l1 = we_tile_attr;
//     we_tile_size_l1 = we_tile_size;
//   end
//
// end // always

//above latches replaced with flops
  always @(negedge clk) begin
   if (start_gclk) begin
      tile_adrs_l1 <= tile_adrs;
      we_tile_attr_l1 <= we_tile_attr;
      we_tile_size_l1 <= we_tile_size;
   end
  end

  // decode the tile address
  always @(tile_adrs_l1)
  begin
    case (tile_adrs_l1[2:0])
      3'h0: decode[7:0] = 8'h01;
      3'h1: decode[7:0] = 8'h02;
      3'h2: decode[7:0] = 8'h04;
      3'h3: decode[7:0] = 8'h08;
      3'h4: decode[7:0] = 8'h10;
      3'h5: decode[7:0] = 8'h20;
      3'h6: decode[7:0] = 8'h40;
      3'h7: decode[7:0] = 8'h80;
      default: decode[7:0] = 8'hx;
    endcase
  end

  assign ta_wrd[7:0] = {8{we_tile_attr_l1}} & decode[7:0];

  j_nd02 ta_nd7 (.a1(1'b1), .a2(ta_wrd[7]), .zn(ta_en[7]));
  j_nd02 ta_nd6 (.a1(1'b1), .a2(ta_wrd[6]), .zn(ta_en[6]));
  j_nd02 ta_nd5 (.a1(1'b1), .a2(ta_wrd[5]), .zn(ta_en[5]));
  j_nd02 ta_nd4 (.a1(1'b1), .a2(ta_wrd[4]), .zn(ta_en[4]));
  j_nd02 ta_nd3 (.a1(1'b1), .a2(ta_wrd[3]), .zn(ta_en[3]));
  j_nd02 ta_nd2 (.a1(1'b1), .a2(ta_wrd[2]), .zn(ta_en[2]));
  j_nd02 ta_nd1 (.a1(1'b1), .a2(ta_wrd[1]), .zn(ta_en[1]));
  j_nd02 ta_nd0 (.a1(1'b1), .a2(ta_wrd[0]), .zn(ta_en[0]));

  j_in01 ta_msb_in7 (.i(ta_en[7]), .zn(ta_en_msb7));
  j_in01 ta_msb_in6 (.i(ta_en[6]), .zn(ta_en_msb6));
  j_in01 ta_msb_in5 (.i(ta_en[5]), .zn(ta_en_msb5));
  j_in01 ta_msb_in4 (.i(ta_en[4]), .zn(ta_en_msb4));
  j_in01 ta_msb_in3 (.i(ta_en[3]), .zn(ta_en_msb3));
  j_in01 ta_msb_in2 (.i(ta_en[2]), .zn(ta_en_msb2));
  j_in01 ta_msb_in1 (.i(ta_en[1]), .zn(ta_en_msb1));
  j_in01 ta_msb_in0 (.i(ta_en[0]), .zn(ta_en_msb0));

  j_in01 ta_lsb_in7 (.i(ta_en[7]), .zn(ta_en_lsb7));
  j_in01 ta_lsb_in6 (.i(ta_en[6]), .zn(ta_en_lsb6));
  j_in01 ta_lsb_in5 (.i(ta_en[5]), .zn(ta_en_lsb5));
  j_in01 ta_lsb_in4 (.i(ta_en[4]), .zn(ta_en_lsb4));
  j_in01 ta_lsb_in3 (.i(ta_en[3]), .zn(ta_en_lsb3));
  j_in01 ta_lsb_in2 (.i(ta_en[2]), .zn(ta_en_lsb2));
  j_in01 ta_lsb_in1 (.i(ta_en[1]), .zn(ta_en_lsb1));
  j_in01 ta_lsb_in0 (.i(ta_en[0]), .zn(ta_en_lsb0));

  // define the tile_attr memory

  // msb
  always @(negedge clk) begin
   if (start_gclk) begin
    if (ta_en_msb0)
      memory_attr_msb0 <= tile_data_ireg_msb_at;

    if (ta_en_msb1)
      memory_attr_msb1 <= tile_data_ireg_msb_at;

    if (ta_en_msb2)
      memory_attr_msb2 <= tile_data_ireg_msb_at;

    if (ta_en_msb3)
      memory_attr_msb3 <= tile_data_ireg_msb_at;

    if (ta_en_msb4)
      memory_attr_msb4 <= tile_data_ireg_msb_at;

    if (ta_en_msb5)
      memory_attr_msb5 <= tile_data_ireg_msb_at;

    if (ta_en_msb6)
      memory_attr_msb6 <= tile_data_ireg_msb_at;

    if (ta_en_msb7)
      memory_attr_msb7 <= tile_data_ireg_msb_at;
   end
  end // always


  // lsb
  always @(negedge clk) begin
   if (start_gclk) begin
    if (ta_en_lsb0)
      memory_attr_lsb0 <= tile_data_ireg_lsb;

    if (ta_en_lsb1)
      memory_attr_lsb1 <= tile_data_ireg_lsb;

    if (ta_en_lsb2)
      memory_attr_lsb2 <= tile_data_ireg_lsb;

    if (ta_en_lsb3)
      memory_attr_lsb3 <= tile_data_ireg_lsb;

    if (ta_en_lsb4)
      memory_attr_lsb4 <= tile_data_ireg_lsb;

    if (ta_en_lsb5)
      memory_attr_lsb5 <= tile_data_ireg_lsb;

    if (ta_en_lsb6)
      memory_attr_lsb6 <= tile_data_ireg_lsb;

    if (ta_en_lsb7)
      memory_attr_lsb7 <= tile_data_ireg_lsb;
   end
  end // always



  assign ts_wrd[7:0] = {8{we_tile_size_l1}} & decode[7:0];

  j_nd02 ts_nd7 (.a1(1'b1), .a2(ts_wrd[7]), .zn(ts_en[7]));
  j_nd02 ts_nd6 (.a1(1'b1), .a2(ts_wrd[6]), .zn(ts_en[6]));
  j_nd02 ts_nd5 (.a1(1'b1), .a2(ts_wrd[5]), .zn(ts_en[5]));
  j_nd02 ts_nd4 (.a1(1'b1), .a2(ts_wrd[4]), .zn(ts_en[4]));
  j_nd02 ts_nd3 (.a1(1'b1), .a2(ts_wrd[3]), .zn(ts_en[3]));
  j_nd02 ts_nd2 (.a1(1'b1), .a2(ts_wrd[2]), .zn(ts_en[2]));
  j_nd02 ts_nd1 (.a1(1'b1), .a2(ts_wrd[1]), .zn(ts_en[1]));
  j_nd02 ts_nd0 (.a1(1'b1), .a2(ts_wrd[0]), .zn(ts_en[0]));

  j_in01 ts_msb_in7 (.i(ts_en[7]), .zn(ts_en_msb7));
  j_in01 ts_msb_in6 (.i(ts_en[6]), .zn(ts_en_msb6));
  j_in01 ts_msb_in5 (.i(ts_en[5]), .zn(ts_en_msb5));
  j_in01 ts_msb_in4 (.i(ts_en[4]), .zn(ts_en_msb4));
  j_in01 ts_msb_in3 (.i(ts_en[3]), .zn(ts_en_msb3));
  j_in01 ts_msb_in2 (.i(ts_en[2]), .zn(ts_en_msb2));
  j_in01 ts_msb_in1 (.i(ts_en[1]), .zn(ts_en_msb1));
  j_in01 ts_msb_in0 (.i(ts_en[0]), .zn(ts_en_msb0));

  j_in01 ts_lsb_in7 (.i(ts_en[7]), .zn(ts_en_lsb7));
  j_in01 ts_lsb_in6 (.i(ts_en[6]), .zn(ts_en_lsb6));
  j_in01 ts_lsb_in5 (.i(ts_en[5]), .zn(ts_en_lsb5));
  j_in01 ts_lsb_in4 (.i(ts_en[4]), .zn(ts_en_lsb4));
  j_in01 ts_lsb_in3 (.i(ts_en[3]), .zn(ts_en_lsb3));
  j_in01 ts_lsb_in2 (.i(ts_en[2]), .zn(ts_en_lsb2));
  j_in01 ts_lsb_in1 (.i(ts_en[1]), .zn(ts_en_lsb1));
  j_in01 ts_lsb_in0 (.i(ts_en[0]), .zn(ts_en_lsb0));

  // define the tile_size memory

  // msb
  always @(negedge clk)
   if (start_gclk) begin
    if (ts_en_msb0)
      memory_size_msb0 <= tile_data_ireg_msb_sz;

    if (ts_en_msb1)
      memory_size_msb1 <= tile_data_ireg_msb_sz;

    if (ts_en_msb2)
      memory_size_msb2 <= tile_data_ireg_msb_sz;

    if (ts_en_msb3)
      memory_size_msb3 <= tile_data_ireg_msb_sz;

    if (ts_en_msb4)
      memory_size_msb4 <= tile_data_ireg_msb_sz;

    if (ts_en_msb5)
      memory_size_msb5 <= tile_data_ireg_msb_sz;

    if (ts_en_msb6)
      memory_size_msb6 <= tile_data_ireg_msb_sz;

    if (ts_en_msb7)
      memory_size_msb7 <= tile_data_ireg_msb_sz;
  end // always


  // lsb
  always @(negedge clk)
   if (start_gclk) begin
    if (ts_en_lsb0)
      memory_size_lsb0 <= tile_data_ireg_lsb;

    if (ts_en_lsb1)
      memory_size_lsb1 <= tile_data_ireg_lsb;

    if (ts_en_lsb2)
      memory_size_lsb2 <= tile_data_ireg_lsb;

    if (ts_en_lsb3)
      memory_size_lsb3 <= tile_data_ireg_lsb;

    if (ts_en_lsb4)
      memory_size_lsb4 <= tile_data_ireg_lsb;

    if (ts_en_lsb5)
      memory_size_lsb5 <= tile_data_ireg_lsb;

    if (ts_en_lsb6)
      memory_size_lsb6 <= tile_data_ireg_lsb;

    if (ts_en_lsb7)
      memory_size_lsb7 <= tile_data_ireg_lsb;
  end // always


  // decode the read address

  always @(l_tile or memory_attr_msb0 or memory_attr_msb1 or 
	   memory_attr_msb2 or memory_attr_msb3 or memory_attr_msb4 or 
	   memory_attr_msb5 or memory_attr_msb6 or memory_attr_msb7)
  begin
    case (l_tile[2:0])
      3'h0: rd_data_attr_msb[22:0] = memory_attr_msb0;
      3'h1: rd_data_attr_msb[22:0] = memory_attr_msb1;
      3'h2: rd_data_attr_msb[22:0] = memory_attr_msb2;
      3'h3: rd_data_attr_msb[22:0] = memory_attr_msb3;
      3'h4: rd_data_attr_msb[22:0] = memory_attr_msb4;
      3'h5: rd_data_attr_msb[22:0] = memory_attr_msb5;
      3'h6: rd_data_attr_msb[22:0] = memory_attr_msb6;
      3'h7: rd_data_attr_msb[22:0] = memory_attr_msb7;
      default: rd_data_attr_msb[22:0] = 8'hx;
    endcase
  end

  always @(l_tile or memory_attr_lsb0 or memory_attr_lsb1 or 
           memory_attr_lsb2 or memory_attr_lsb3 or memory_attr_lsb4 or 
           memory_attr_lsb5 or memory_attr_lsb6 or memory_attr_lsb7)
  begin
    case (l_tile[2:0])
      3'h0: rd_data_attr_lsb[23:0] = memory_attr_lsb0;
      3'h1: rd_data_attr_lsb[23:0] = memory_attr_lsb1;
      3'h2: rd_data_attr_lsb[23:0] = memory_attr_lsb2;
      3'h3: rd_data_attr_lsb[23:0] = memory_attr_lsb3;
      3'h4: rd_data_attr_lsb[23:0] = memory_attr_lsb4;
      3'h5: rd_data_attr_lsb[23:0] = memory_attr_lsb5;
      3'h6: rd_data_attr_lsb[23:0] = memory_attr_lsb6;
      3'h7: rd_data_attr_lsb[23:0] = memory_attr_lsb7;
      default: rd_data_attr_lsb[23:0] = 8'hx;
    endcase
  end

  always @(l_tile or memory_size_msb0 or memory_size_msb1 or
           memory_size_msb2 or memory_size_msb3 or memory_size_msb4 or
           memory_size_msb5 or memory_size_msb6 or memory_size_msb7)
  begin
    case (l_tile[2:0])
      3'h0: rd_data_size_msb[23:0] = memory_size_msb0;
      3'h1: rd_data_size_msb[23:0] = memory_size_msb1;
      3'h2: rd_data_size_msb[23:0] = memory_size_msb2;
      3'h3: rd_data_size_msb[23:0] = memory_size_msb3;
      3'h4: rd_data_size_msb[23:0] = memory_size_msb4;
      3'h5: rd_data_size_msb[23:0] = memory_size_msb5;
      3'h6: rd_data_size_msb[23:0] = memory_size_msb6;
      3'h7: rd_data_size_msb[23:0] = memory_size_msb7;
      default: rd_data_size_msb[23:0] = 8'hx;
    endcase
  end

  always @(l_tile or memory_size_lsb0 or memory_size_lsb1 or
           memory_size_lsb2 or memory_size_lsb3 or memory_size_lsb4 or
           memory_size_lsb5 or memory_size_lsb6 or memory_size_lsb7)
  begin
    case (l_tile[2:0])
      3'h0: rd_data_size_lsb[23:0] = memory_size_lsb0;
      3'h1: rd_data_size_lsb[23:0] = memory_size_lsb1;
      3'h2: rd_data_size_lsb[23:0] = memory_size_lsb2;
      3'h3: rd_data_size_lsb[23:0] = memory_size_lsb3;
      3'h4: rd_data_size_lsb[23:0] = memory_size_lsb4;
      3'h5: rd_data_size_lsb[23:0] = memory_size_lsb5;
      3'h6: rd_data_size_lsb[23:0] = memory_size_lsb6;
      3'h7: rd_data_size_lsb[23:0] = memory_size_lsb7;
      default: rd_data_size_lsb[23:0] = 8'hx;
    endcase
  end

  // memory output registers
  always @(posedge clk)
    if (start_gclk) begin

    {tex_type, tex_size, line, tmem_adrs, palette, clamp_t, mir_t, mask_t, 
     shift_t, clamp_s, mir_s, mask_s, shift_s} <= 
			{rd_data_attr_msb, rd_data_attr_lsb};

    {sl, sh, tl, th} <= {rd_data_size_msb, rd_data_size_lsb};

  end // always


  always @(posedge clk)
   if (start_gclk) begin

    // delay outputs of tile memory

    tex_type_1d <= tex_type;
    tex_type_2d <= tex_type_1d;

    tex_size_1d <= tex_size;
    tex_size_2d <= tex_size_1d;
    
    line_1d <= line;
    line_2d <= line_1d;

    tmem_adrs_1d <= tmem_adrs;
    tmem_adrs_2d <= tmem_adrs_1d;

    palette_1d <= palette;
    palette_2d <= palette_1d;
    palette_3d <= palette_2d;
    palette_4d <= palette_3d;

    clamp_t_1d <= clamp_t;

    mir_t_1d <= mir_t;

    mask_t_1d <= mask_t;

    clamp_s_1d <= clamp_s;

    mir_s_1d <= mir_s;

    mask_s_1d <= mask_s;

  end // always

endmodule // tc_tilemem