// ui.v v1 Doug Solomon
// USB Interface

module ui (
	sysclk,
	Reset,
	cbus_write_enable,
	cbus_select,
	cbus_command,
	cbus_din,
	cbus_dout,
	cbus_read_request,
	cbus_read_grant,
	cbus_dma_request,
	cbus_dma_grant,
	dbus_din,
	dbus_dout,
	dma_start,
	dbus_read_enable,
	dbus_write_enable,
	secure,
	irq,
	usb_clk,	// 48MHz USB clock
	usb_sel_sys,	// usb select sysclk/2
	usb_dp,		// USB propagated up signals
	usb_dpo, 
	usb_dm, 
	usbxr_ose,
	usbxr_y1, 
	usbxr_oen, 
	usbxr_ien, 
	usbxr_fl,
	usb_dp_high, 
	usb_d_low_n,
	usb_vbus_vld,
	usb_id, 
	usb_vbus_on_n
	);

	input		sysclk;
	input		Reset;
	input		cbus_write_enable;
	input	[1:0]	cbus_select;
	input	[2:0]	cbus_command;
	input	[31:0]	cbus_din;
	output	[31:0]	cbus_dout;
	output		cbus_read_request;
	input		cbus_read_grant;
	output		cbus_dma_request;
	input		cbus_dma_grant;
	input	[63:0]	dbus_din;
	output	[63:0]	dbus_dout;
	input		dma_start;
	input		dbus_read_enable;
	input		dbus_write_enable;
	input		secure;
	output	[1:0]	irq;
	input		usb_clk;	//48 MHz USB clock
	output		usb_sel_sys;
	input	[1:0]	usb_dp;		// USB propagated up signal 
	input	[1:0]	usb_dm;		//  (move test out of chip).
	output	[1:0]	usb_dpo;
	output	[1:0]	usbxr_ose;
	input	[1:0]	usbxr_y1;
	output	[1:0]	usbxr_oen;
	output	[1:0]	usbxr_ien;
	output	[1:0]	usbxr_fl;
	output	[1:0]	usb_dp_high;    // resistor signals
	output	[1:0]	usb_d_low_n;
	input 	[1:0]	usb_vbus_vld;
	input	[1:0]	usb_id;         //  OTG signals
	output	[1:0]	usb_vbus_on_n;
	

	wire		cbus_read_request0;
	wire		cbus_dma_request0;
	wire		irq0;
	wire		Stwg0;
	wire	[31:0]	CADOut0;
	wire	[31:0]	i_wdata0;

	wire		cbus_read_request1;
	wire		cbus_dma_request1;
	wire		irq1;
	wire		Stwg1;
	wire	[31:0]	CADOut1;
	wire	[31:0]	i_wdata1;

	//	cbus commands

	`define		CMD_IDLE	3'h0
	`define		CMD_DMA		3'h1
	`define		CMD_WRITE	3'h2
	`define		CMD_READ	3'h3
	`define		CMD_RESPONSE	3'h4
	`define		CMD_REFRESH	3'h5

	//	cbus selects

	`define		SEL_DATA	2'b10
	`define		SEL_LEN		2'b01
	`define		SEL_ADDR	2'b00

	//	cbus device identifiers

	`define		ID_UI	4'hA

	//      ui register space

	`define		BUS_ADDRESS_UI0	12'h049
	`define		BUS_ADDRESS_UI1	12'h04A

	wire	[1:0]	irq = {irq1,irq0};

	wire	CAEn = (cbus_command==`CMD_READ)
		     | (cbus_command==`CMD_WRITE);

	reg	[31:0]	CAddrIn;

	wire	[31:0]	nxt_CAddrIn = CAEn ? cbus_din : CAddrIn;

	always @(posedge sysclk) 
		CAddrIn  <= nxt_CAddrIn;

	`define		CLK_SEL		16'h4_000	// Address[19:4]
	`define		ACC_CTL		16'h4_001

	wire	UISpace0 = (CAddrIn[31:20]==`BUS_ADDRESS_UI0);
	wire	UISpace1 = (CAddrIn[31:20]==`BUS_ADDRESS_UI1);

	wire	RegSpace0 = UISpace0 & ~CAddrIn[19];
	wire	RegSpace1 = UISpace1 & ~CAddrIn[19];

	wire	CtlSpace0 = RegSpace0 & ~CAddrIn[18];
	wire	CtlSpace1 = RegSpace1 & ~CAddrIn[18];

	wire	BDTSpace0 = UISpace0 &  CAddrIn[19];
	wire	BDTSpace1 = UISpace1 &  CAddrIn[19];

	reg	cbus_read;
	reg	cbus_write;
	wire	nxt_cbus_read  = (cbus_command==`CMD_READ);
	wire	nxt_cbus_write = (cbus_command==`CMD_WRITE);
	always @(posedge sysclk) begin
			cbus_read  <= nxt_cbus_read  & ~Reset;
			cbus_write <= nxt_cbus_write & ~Reset;
	end

	wire	CDEn = cbus_write & (BDTSpace0  | BDTSpace1 | 
				     RegSpace0  | RegSpace1);

	reg	[31:0]	CDataIn;
	wire	[31:0]	nxt_CDataIn = CDEn ? cbus_din[31:0] 
					   : CDataIn;
	always @(posedge sysclk) 
		CDataIn  <= nxt_CDataIn;

	reg	Write_CS0;
	reg	CS0;
	reg	AC0;
	wire	nxt_Write_CS0 = CDEn & RegSpace0 & (CAddrIn[19:4]==`CLK_SEL);
	wire	nxt_CS0 = (AC0 & Write_CS0) ? CDataIn[0] : CS0;
	always @(posedge sysclk) begin
		      CS0 <= ~Reset & nxt_CS0;
		Write_CS0 <= ~Reset & nxt_Write_CS0;
	end

	reg	Write_CS1;
	reg	CS1;
	reg	AC1;
	wire	nxt_Write_CS1 = CDEn & RegSpace1 & (CAddrIn[19:4]==`CLK_SEL);
	wire	nxt_CS1 = (AC1 & Write_CS1) ? CDataIn[0] : CS1;
	always @(posedge sysclk) begin
		      CS1 <= ~Reset & nxt_CS1;
		Write_CS1 <= ~Reset & nxt_Write_CS1;
	end

	wire	usb_sel_sys = (CS0 | CS1);

	reg	Write_AC0;
	wire	nxt_Write_AC0 = CDEn & RegSpace0 & (CAddrIn[19:4]==`ACC_CTL);
	wire	nxt_AC0 = Write_AC0 ? (secure ? CDataIn[0] 
					      : (AC0 &  CDataIn[0]))
				    : AC0;
	always @(posedge sysclk) begin
		      AC0 <= ~Reset & nxt_AC0;	
		Write_AC0 <= ~Reset & nxt_Write_AC0;
	end

	reg	Write_AC1;
	wire	nxt_Write_AC1 = CDEn & RegSpace1 & (CAddrIn[19:4]==`ACC_CTL);
	wire	nxt_AC1 = Write_AC1 ? (secure ? CDataIn[0] 
					      : (AC1 &  CDataIn[0]))
				    : AC1;
	always @(posedge sysclk) begin
		      AC1 <= ~Reset & nxt_AC1;
		Write_AC1 <= ~Reset & nxt_Write_AC1;
	end

	wire	sec_cbus_write0 = cbus_write & AC0;
	wire	sec_cbus_write1 = cbus_write & AC1;

	wire	cbus_dma_addr0 =  cbus_dma_request0 & cbus_dma_grant;
	wire	cbus_dma_addr1 = ~cbus_dma_request0 & cbus_dma_grant;
	reg	cbus_dma_length0;
	reg	cbus_dma_length1;
	always @(posedge sysclk) begin
			cbus_dma_length0 <= cbus_dma_addr0;
			cbus_dma_length1 <= cbus_dma_addr1;
	end
	wire	cbus_read_data0 =  cbus_read_request0 & cbus_read_grant;
	wire	cbus_read_data1 =  cbus_read_request1 & cbus_read_grant;

	wire	[31:0]	CADOut = {32{      cbus_dma_addr0  }} & CADOut0
			       | {32{      cbus_dma_length0}} & CADOut0
			       | {32{AC0 & cbus_read_data0 }} & CADOut0
			       | {32{      cbus_dma_addr1  }} & CADOut1
			       | {32{      cbus_dma_length1}} & CADOut1
			       | {32{AC1 & cbus_read_data1 }} & CADOut1;

	wire	[31:0]	cbus_dout = cbus_write_enable ? CADOut : 32'b0;

	reg	[63:0]	DBusOut;
	wire	[63:0]	nxt_DBusOut = Stwg0 ? {i_wdata0,i_wdata0}
					    : (Stwg1 ? {i_wdata1,i_wdata1}
						     : 64'b0);
	always @(posedge sysclk)
			DBusOut <= nxt_DBusOut;

	wire	[63:0]	dbus_dout = dbus_write_enable ? DBusOut : 64'b0;

	reg	[63:0]	DBusIn;
	wire	[63:0]	nxt_DBusIn = dbus_read_enable ? dbus_din : DBusIn;
	always @(posedge sysclk)
			DBusIn <= nxt_DBusIn;

	wire	cbus_dma_grant0 = cbus_dma_grant &  cbus_dma_request0;
	wire	cbus_dma_grant1 = cbus_dma_grant & ~cbus_dma_request0;

	wire	cbus_dma_request  = cbus_dma_request0  | cbus_dma_request1;
	wire	cbus_read_request = cbus_read_request0 | cbus_read_request1;

	wire [1:0] usb_rcv;
	wire [1:0] usb_oe_n;
	wire [1:0] usb_speed;
	wire [1:0] usb_dmo;

	usb_ioblk usb_ioblk0(
		.usb_suspnd(1'b0),
		.usbxr_y1(usbxr_y1[0]),
		.usb_oe_n(usb_oe_n[0]),
		.usb_speed(usb_speed[0]),
		.usb_dpo(usb_dpo[0]),
		.usb_dmo(usb_dmo[0]),
		.usbxr_oen(usbxr_oen[0]),
		.usbxr_ien(usbxr_ien[0]),
		.usbxr_fl(usbxr_fl[0]),
		.usb_rcv(usb_rcv[0]),
		.usbxr_ose(usbxr_ose[0]));
	
	usb_ioblk usb_ioblk1(
		.usb_suspnd(1'b0),
		.usbxr_y1(usbxr_y1[1]),
		.usb_oe_n(usb_oe_n[1]),
		.usb_speed(usb_speed[1]),
		.usb_dpo(usb_dpo[1]),
		.usb_dmo(usb_dmo[1]),
		.usbxr_oen(usbxr_oen[1]),
		.usbxr_ien(usbxr_ien[1]),
		.usbxr_fl(usbxr_fl[1]),
		.usb_rcv(usb_rcv[1]),
		.usbxr_ose(usbxr_ose[1]));
	
	ui_ctrl ui_ctrl0 (
		.sysclk			(sysclk),
		.Reset			(Reset),
		.CtlSpace		(CtlSpace0),
		.BDTSpace		(BDTSpace0),
		.cbus_read		(cbus_read),
		.cbus_write		(sec_cbus_write0),
		.cbus_read_grant	(cbus_read_grant),
		.cbus_dma_grant		(cbus_dma_grant0),
		.t_address		(CAddrIn),
		.CDataIn		(CDataIn),
		.DBusIn			(DBusIn),
		.cbus_select		(cbus_select),
		.dma_start		(dma_start),

		.cbus_read_request	(cbus_read_request0),
		.cbus_dma_request	(cbus_dma_request0),
		.irq			(irq0),
		.Stwg			(Stwg0),
		.CADOut			(CADOut0),
		.i_wdata		(i_wdata0),
		// USB propagated up signals 
		.usb_clk48 		(usb_clk),
		.usb_rcv		(usb_rcv[0]),
		.usb_dp			(usb_dp[0]),
		.usb_dpo		(usb_dpo[0]),
		.usb_dm			(usb_dm[0]),
		.usb_dmo		(usb_dmo[0]),
		.usb_oe_n		(usb_oe_n[0]),
		.usb_speed		(usb_speed[0]),
		.usb_dp_high		(usb_dp_high[0]),
		.usb_d_low_n		(usb_d_low_n[0]),
		.usb_vbus_vld		(usb_vbus_vld[0]),
		.usb_id			(usb_id[0]),
		.usb_vbus_on_n 		(usb_vbus_on_n[0])
		);

	ui_ctrl ui_ctrl1 (
		.sysclk			(sysclk),
		.Reset			(Reset),
		.CtlSpace		(CtlSpace1),
		.BDTSpace		(BDTSpace1),
		.cbus_read		(cbus_read),
		.cbus_write		(sec_cbus_write1),
		.cbus_read_grant	(cbus_read_grant),
		.cbus_dma_grant		(cbus_dma_grant1),
		.t_address		(CAddrIn),
		.CDataIn		(CDataIn),
		.DBusIn			(DBusIn),
		.cbus_select		(cbus_select),
		.dma_start		(dma_start),

		.cbus_read_request	(cbus_read_request1),
		.cbus_dma_request	(cbus_dma_request1),
		.irq			(irq1),
		.Stwg			(Stwg1),
		.CADOut			(CADOut1),
		.i_wdata		(i_wdata1),
		// USB propagated up signals 
		.usb_clk48 		(usb_clk),
		.usb_rcv		(usb_rcv[1]),
		.usb_dp			(usb_dp[1]),
		.usb_dpo		(usb_dpo[1]),
		.usb_dm			(usb_dm[1]),
		.usb_dmo		(usb_dmo[1]),
		.usb_oe_n		(usb_oe_n[1]),
		.usb_speed		(usb_speed[1]),
		.usb_dp_high		(usb_dp_high[1]),
		.usb_d_low_n		(usb_d_low_n[1]),
		.usb_vbus_vld		(usb_vbus_vld[1]),
		.usb_id			(usb_id[1]),
		.usb_vbus_on_n 		(usb_vbus_on_n[1])
		);

endmodule