ui_buf.v
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// ui_buf.v v1 Frank Berndt
// ui buffer wrapper;
// :set tabstop=4
module ui_buf (
clk, en, addr, di, we, do
);
input clk; // sync clock;
input en; // chip enable;
input [6:0] addr; // address;
input [31:0] di; // write data;
input [3:0] we; // write enables;
output [31:0] do; // read data;
wire csb = ~en; // active low read enable
wire [3:0] web = ~we; // active low write enable
// four 128x8 sync SRAMs;
WBSRAMSHS128W8C3 uibuf3 (
.DO7 (do[31]),
.DO6 (do[30]),
.DO5 (do[29]),
.DO4 (do[28]),
.DO3 (do[27]),
.DO2 (do[26]),
.DO1 (do[25]),
.DO0 (do[24]),
.DI7 (di[31]),
.DI6 (di[30]),
.DI5 (di[29]),
.DI4 (di[28]),
.DI3 (di[27]),
.DI2 (di[26]),
.DI1 (di[25]),
.DI0 (di[24]),
.A6 (addr[6]),
.A5 (addr[5]),
.A4 (addr[4]),
.A3 (addr[3]),
.A2 (addr[2]),
.A1 (addr[1]),
.A0 (addr[0]),
.WEB (web[1]),
.CSB (csb),
.BE (clk),
.TBE (1'b0),
.TEST (1'b0),
.BUB (1'b1)
);
WBSRAMSHS128W8C3 uibuf2 (
.DO7 (do[23]),
.DO6 (do[22]),
.DO5 (do[21]),
.DO4 (do[20]),
.DO3 (do[19]),
.DO2 (do[18]),
.DO1 (do[17]),
.DO0 (do[16]),
.DI7 (di[23]),
.DI6 (di[22]),
.DI5 (di[21]),
.DI4 (di[20]),
.DI3 (di[19]),
.DI2 (di[18]),
.DI1 (di[17]),
.DI0 (di[16]),
.A6 (addr[6]),
.A5 (addr[5]),
.A4 (addr[4]),
.A3 (addr[3]),
.A2 (addr[2]),
.A1 (addr[1]),
.A0 (addr[0]),
.WEB (web[2]),
.CSB (csb),
.BE (clk),
.TBE (1'b0),
.TEST (1'b0),
.BUB (1'b1)
);
WBSRAMSHS128W8C3 uibuf1 (
.DO7 (do[15]),
.DO6 (do[14]),
.DO5 (do[13]),
.DO4 (do[12]),
.DO3 (do[11]),
.DO2 (do[10]),
.DO1 (do[9]),
.DO0 (do[8]),
.DI7 (di[15]),
.DI6 (di[14]),
.DI5 (di[13]),
.DI4 (di[12]),
.DI3 (di[11]),
.DI2 (di[10]),
.DI1 (di[9]),
.DI0 (di[8]),
.A6 (addr[6]),
.A5 (addr[5]),
.A4 (addr[4]),
.A3 (addr[3]),
.A2 (addr[2]),
.A1 (addr[1]),
.A0 (addr[0]),
.WEB (web[1]),
.CSB (csb),
.BE (clk),
.TBE (1'b0),
.TEST (1'b0),
.BUB (1'b1)
);
WBSRAMSHS128W8C3 uibuf0 (
.DO7 (do[7]),
.DO6 (do[6]),
.DO5 (do[5]),
.DO4 (do[4]),
.DO3 (do[3]),
.DO2 (do[2]),
.DO1 (do[1]),
.DO0 (do[0]),
.DI7 (di[7]),
.DI6 (di[6]),
.DI5 (di[5]),
.DI4 (di[4]),
.DI3 (di[3]),
.DI2 (di[2]),
.DI1 (di[1]),
.DI0 (di[0]),
.A6 (addr[6]),
.A5 (addr[5]),
.A4 (addr[4]),
.A3 (addr[3]),
.A2 (addr[2]),
.A1 (addr[1]),
.A0 (addr[0]),
.WEB (web[0]),
.CSB (csb),
.BE (clk),
.TBE (1'b0),
.TEST (1'b0),
.BUB (1'b1)
);
endmodule