// ui_ctrl.v v1 Doug Solomon
// USB Interface

module ui_ctrl (
	sysclk,
	Reset,
	CtlSpace,
	BDTSpace,
	cbus_read,
	cbus_write,
	cbus_read_grant,
	cbus_dma_grant,
	t_address,
	CDataIn,
	DBusIn,
	cbus_select,
	dma_start,

	cbus_read_request,
	cbus_dma_request,
	irq,
	Stwg,
	CADOut,
	i_wdata,

	usb_clk48,
	usb_rcv, // propagated up signals
	usb_dp,
	usb_dm,
	usb_dpo,
	usb_dmo,
	usb_oe_n,
	usb_speed,
	usb_dp_high,	// resistor signal
	usb_d_low_n,
	usb_vbus_vld,
	usb_id,		// OTG signals
	usb_vbus_on_n
	);

	input		sysclk;
	input		Reset;
	input		CtlSpace;
	input		BDTSpace;
	input		cbus_read;
	input		cbus_write;
	input		cbus_read_grant;
	input		cbus_dma_grant;
	input	[31:0]	t_address;
	input	[31:0]	CDataIn;
	input	[63:0]	DBusIn;
	input	[1:0]	cbus_select;
	input		dma_start;

	output		cbus_dma_request;
	output		cbus_read_request;
	output		irq;
	output		Stwg;
	output	[31:0]	CADOut;
	output	[31:0]	i_wdata;

	// USB propagated up signal (move test out of chip).
    input       usb_clk48;     //48 MHz USB clock

    input       usb_rcv;       // xcvr signals
    input       usb_dp;
    input       usb_dm;
    output      usb_dpo;
    output      usb_dmo;
    output      usb_oe_n;
    output      usb_speed;

    output      usb_dp_high;   // resistor signals
    output      usb_d_low_n;

    input	usb_vbus_vld;
    input       usb_id;         //  OTG signals
    output      usb_vbus_on_n;

	wire    	usb_clk; 
	wire    	usb_clk48; 
	reg	    	usb_rst48; 
//  BVCI Initiator Interface
	wire    	i_cmdack;
	wire	[31:0]	i_rdata;
	wire		i_reop;
	reg		i_rspval;
	wire	[31:0]	i_address;
	wire	[3:0]	i_be;
	wire	[1:0]	i_cmd;
	wire		i_cmdval;
	wire		i_eop;		// NC from vusb_bvci
	wire		i_rspack;	// NC from vusb_bvci
	wire	[31:0]	i_wdata;
//  BVCI Target Interface
	wire	[31:0]	t_address;
	wire	[3:0]	t_be;
	reg	[1:0]	t_cmd;
	reg	    	t_cmdval;
	wire		t_eop;
	wire		t_rspack;
	wire    [31:0]	t_wdata;
	wire		t_cmdack;	// NC from vusb_bvci
	wire    [31:0]	t_rdata;
	wire		t_reop;		// NC from vusb_bvci
	wire		t_rspval;	// NC from vusb_bvci
	wire		irq; 
//  usb signals
	wire    	usb_rcv; 
	wire    	usb_dp; 
	wire    	usb_dm; 
	wire    	usb_dpo; 
	wire    	usb_dmo; 
	wire    	usb_oe_n; 
	wire    	usb_speed; 
	wire    	usb_suspnd; 
//  pull-up resistor controls
	wire    	usb_dp_high; 
	wire    	usb_dp_low_n; 
	wire    	usb_dm_high; 
	wire    	usb_dm_low_n; 
//  OTG signals
	wire    	usb_id; 
	wire    	usb_a_vbus_vld; 
	wire    	usb_sess_vld; 
	wire    	usb_b_sess_end; 
	wire    	usb_vbus_on; 
	wire    	usb_vbus_chg; 
	wire    	usb_vbus_dschg; 
	wire		usb_vbus_vld_n;
	wire    	usb_a_vbus_vld_n; 
	wire    	usb_sess_vld_n; 
	wire    	usb_b_sess_end_n; 
	wire    	usb_vbus_on_n; 
	wire    	usb_vbus_chg_n; 
	wire    	usb_vbus_dschg_n; 

	//	cbus commands

	`define		CMD_IDLE	3'h0
	`define		CMD_DMA		3'h1
	`define		CMD_WRITE	3'h2
	`define		CMD_READ	3'h3
	`define		CMD_RESPONSE	3'h4
	`define		CMD_REFRESH	3'h5

	//	cbus selects

	`define		SEL_DATA	2'b10
	`define		SEL_LEN		2'b01
	`define		SEL_ADDR	2'b00

	//	cbus device identifiers

	`define		ID_UI	4'hA

	//      ui register space

	`define		BUS_ADDRESS_UI0	12'h049
	`define		BUS_ADDRESS_UI1	12'h04A

	wire		ui_read	 = cbus_read  & CtlSpace;
	wire		ui_write = cbus_write & CtlSpace;

	wire		bdt_read  = cbus_read  & BDTSpace;
	wire		bdt_write = cbus_write & BDTSpace;

	reg		cbus_bdt_read;
	reg		cbus_bdt_write;
	wire		cbus_bdt = cbus_bdt_read | cbus_bdt_write;

	wire		nxt_ui_bdt;

	reg		cbus_bdt_read_wait;
	reg		cbus_bdt_write_wait;

	wire		nxt_cbus_bdt_read_wait  = 
			~cbus_bdt_read_wait & bdt_read & nxt_ui_bdt
		      |  cbus_bdt_read_wait & nxt_ui_bdt;

	wire		nxt_cbus_bdt_write_wait  = 
			~cbus_bdt_write_wait & bdt_write & nxt_ui_bdt
		      |  cbus_bdt_write_wait & nxt_ui_bdt;

	always @(posedge sysclk) begin
		cbus_bdt_read_wait  <= nxt_cbus_bdt_read_wait & ~Reset;
		cbus_bdt_write_wait <= nxt_cbus_bdt_write_wait & ~Reset;
	end

	wire	nxt_cbus_bdt_read = bdt_read & ~nxt_ui_bdt
				  | cbus_bdt_read_wait & ~nxt_ui_bdt;

	wire	nxt_cbus_bdt_write = bdt_write & ~nxt_ui_bdt
				   | cbus_bdt_write_wait & ~nxt_ui_bdt;

	always @(posedge sysclk) begin
		cbus_bdt_read  <= nxt_cbus_bdt_read;
		cbus_bdt_write <= nxt_cbus_bdt_write;
	end

	wire		nxt_t_cmdval = ui_read | ui_write;

	wire	[1:0]	nxt_t_cmd = ui_read ? 2'h1 : (ui_write ? 2'h2 : 2'h0);

	always @(posedge sysclk) begin
		t_cmdval  <= nxt_t_cmdval;
		t_cmd     <= nxt_t_cmd;
	end

	reg	cbus_read_request;

	wire	nxt_cbus_read_request = ~cbus_read_request &  ui_read
				      | ~cbus_read_request &  cbus_bdt_read
				      |  cbus_read_request & ~cbus_read_grant;

	always @(posedge sysclk) 
		cbus_read_request  <= nxt_cbus_read_request & ~Reset;

	wire	i_addren;

	reg	[31:0]	i_addr_reg;
	wire	[31:0]	nxt_i_addr_reg = i_addren ?  i_address
						  :  i_addr_reg;

	reg	[3:0]	i_be_reg;
	wire	[3:0]	nxt_i_be_reg   = i_addren ? {i_be[0],
						     i_be[1],
						     i_be[2],
						     i_be[3]}
						  : i_be_reg;

	always @(posedge sysclk) begin
			i_addr_reg <= nxt_i_addr_reg;
			i_be_reg   <= nxt_i_be_reg;
	end

	wire	ui_bdt_sel = (nxt_i_addr_reg[31:20]==`BUS_ADDRESS_UI0)
			   | (nxt_i_addr_reg[31:20]==`BUS_ADDRESS_UI1);

	wire	nxt_ui_bdt_read  = (i_cmdval & (i_cmd==2'h1) & ui_bdt_sel);
	wire	nxt_ui_bdt_write = (i_cmdval & (i_cmd==2'h2) & ui_bdt_sel);

	reg	ui_bdt_read;
	reg	ui_bdt_write;

	always @(posedge sysclk) begin
			ui_bdt_read  <= nxt_ui_bdt_read;
			ui_bdt_write <= nxt_ui_bdt_write;
	end

	assign	nxt_ui_bdt = nxt_ui_bdt_read | nxt_ui_bdt_write;

	wire	ui_bdt = ui_bdt_read | ui_bdt_write;

	reg	i_rdata_sel;

	reg	DBLRead;

	always @(posedge sysclk)
			i_rdata_sel  <= ui_bdt_read;

	wire	[6:0]	bdt_addr = ui_bdt ? {i_addr_reg[8:3],
					    (i_addr_reg[2] ^ DBLRead)}
					  :  t_address[8:2];

	wire	[3:0]	bdt_we =  ui_bdt_write   ? i_be_reg
			       :  cbus_bdt_write ? 4'b1111 
			       : 		   4'b0000;

	wire	[31:0]	bdt_datai = ui_bdt_write ? i_wdata 
						 : CDataIn;

	wire		bdt_enable = ui_bdt_read  | cbus_bdt_read
				   | ui_bdt_write | cbus_bdt_write;

	reg		bdt2cbus_enable;

	always @(posedge sysclk) 
			bdt2cbus_enable <= cbus_bdt_read;

	wire	[31:0]	bdt_datao;

	reg	[31:0]	bdt2cbus_datao;

	always @(posedge sysclk) 	
			bdt2cbus_datao <= bdt2cbus_enable ? bdt_datao
							  : bdt2cbus_datao;

	ui_buf	ui_buf0 (
		.clk		(sysclk),
		.en		(bdt_enable),
		.addr		(bdt_addr),
		.di		(bdt_datai),
		.we		(bdt_we),
		.do		(bdt_datao)
		);

	reg	dma_read;

	wire	[2:0]	end_addr;
	wire	[2:0]	start_addr;

	assign	end_addr[2] = nxt_i_addr_reg[2];

	assign	start_addr[2] = nxt_i_addr_reg[2];

	assign	start_addr[1:0] = {2{(nxt_i_be_reg==4'b0001)}} & 2'b11
				| {2{(nxt_i_be_reg==4'b0010)}} & 2'b10
				| {2{(nxt_i_be_reg==4'b0100)}} & 2'b01
				| {2{(nxt_i_be_reg==4'b1000)}} & 2'b00
				| {2{(nxt_i_be_reg==4'b0011)}} & 2'b10
				| {2{(nxt_i_be_reg==4'b0110)}} & 2'b01
				| {2{(nxt_i_be_reg==4'b1100)}} & 2'b00
				| {2{(nxt_i_be_reg==4'b0111)}} & 2'b01
				| {2{(nxt_i_be_reg==4'b1110)}} & 2'b00
				| {2{(nxt_i_be_reg==4'b1111)}} & 2'b00;

	assign	end_addr[1:0]   = {2{(nxt_i_be_reg==4'b0001)}} & 2'b11
				| {2{(nxt_i_be_reg==4'b0010)}} & 2'b10
				| {2{(nxt_i_be_reg==4'b0100)}} & 2'b01
				| {2{(nxt_i_be_reg==4'b1000)}} & 2'b00
				| {2{(nxt_i_be_reg==4'b0011)}} & 2'b11
				| {2{(nxt_i_be_reg==4'b0110)}} & 2'b10
				| {2{(nxt_i_be_reg==4'b1100)}} & 2'b01
				| {2{(nxt_i_be_reg==4'b0111)}} & 2'b11
				| {2{(nxt_i_be_reg==4'b1110)}} & 2'b10
				| {2{(nxt_i_be_reg==4'b1111)}} & 2'b11;


	wire	[31:0]	length = {8'b0,			// 31:24
				  1'b0,			//    23 I
				  1'b0,			//    22 M
				  1'b0,			//    21 D
				  1'b0,			//    20 ?
				  `ID_UI,		// 19:16 ID
				  8'b0,			// 15:8  ?
				  dma_read,		//    7	 Read
				  {4'b0, 		//  6:3  DW Length - 1
				  end_addr}		//  2:0  end byte add
				  };

	reg	[31:0]	CADOut;

	wire	[31:0]	dma_addr = {nxt_i_addr_reg[31:3],start_addr};

	wire	[31:0]	nxt_CADOut   = (cbus_select==`SEL_ADDR) ? dma_addr
				     : (cbus_select==`SEL_LEN ) ? length
				     : BDTSpace 		? bdt2cbus_datao
				     :                            t_rdata;

	always @(posedge sysclk)
		CADOut <= nxt_CADOut;

	// Initiator State Machine

	reg	Sti;
	reg	Strr;		// cbus read request
	reg	Strg;		// cbus read grant
	reg	Strv1;		// cbus read data valid 1
	reg	Strv2;		// cbus read data valid 2
	reg	Stwr;		// cbus write request
	reg	Stwg;		// cbus write grant
	reg	Stwv;		// cbus write data valid
	reg	Stbr;		// bdt read
	reg	Stbw;		// bdt write
	reg	cbus_dma_request;

	wire	i_read_mem  = Sti   &  i_cmdval & (i_cmd==2'h1) & ~ui_bdt_sel;
	wire	i_read_bdt  = Sti   &  i_cmdval & (i_cmd==2'h1) &  ui_bdt_sel;
	wire	i_write_mem = Sti   &  i_cmdval & (i_cmd==2'h2) & ~ui_bdt_sel;
	wire	i_write_bdt = Sti   &  i_cmdval & (i_cmd==2'h2) &  ui_bdt_sel;

	wire	nxt_Sti   = Sti   & ~i_cmdval
			  | Sti   &  i_cmdval & (i_cmd==2'h0)
			  | Sti   &  i_cmdval & (i_cmd==2'h3)
			  | Strv1 & ~i_cmdval & ~DBLRead
			  | Strv2
			  | Stwv;

	wire	nxt_Strr  = Sti   &  i_read_mem 
			  | Strr  & ~cbus_dma_grant;

	wire	nxt_Stbr  = Sti   &  i_read_bdt;

	wire	nxt_Stwr  = Sti   &  i_write_mem 
			  | Stwr  & ~cbus_dma_grant;
			
	wire	nxt_Stbw  = Sti   &  i_write_bdt;

	wire	nxt_Strg  = Strr  &  cbus_dma_grant
			  | Strg  & ~dma_start;

	wire	nxt_Strv1 = Strg  &  dma_start
			  | Stbr;

	wire	nxt_Strv2 = Strv1 &  DBLRead
			  | Strv1 &  i_cmdval;

	wire	nxt_Stwg  = Stwr  &  cbus_dma_grant
			  | Stwg  & ~dma_start;

	wire	nxt_Stwv  = Stwg  &  dma_start
			  | Stbw;

	wire	nxt_DBLRead = ~DBLRead &  Strr  & i_cmdval
			    | ~DBLRead &  Stbr  & i_cmdval
			    |  DBLRead & ~Strv1;

	always @(posedge sysclk) begin
		Sti              <= nxt_Sti     |  Reset;
		Strr             <= nxt_Strr    & ~Reset;
		Stbr             <= nxt_Stbr    & ~Reset;
		Strg             <= nxt_Strg    & ~Reset;
		Strv1            <= nxt_Strv1   & ~Reset;
		Strv2            <= nxt_Strv2   & ~Reset;
		Stwr             <= nxt_Stwr    & ~Reset;
		Stbw             <= nxt_Stbw    & ~Reset;
		Stwg             <= nxt_Stwg    & ~Reset;
		Stwv             <= nxt_Stwv    & ~Reset;
		cbus_dma_request <= nxt_Strr    & ~Reset
				  | nxt_Stwr    & ~Reset;
		i_rspval         <= nxt_Strv1   & ~Reset 
				  | nxt_Strv2   & ~Reset 
				  | nxt_Stwv    & ~Reset;
		dma_read	 <= nxt_Strr    & ~Reset  
				  | nxt_Strg    & ~Reset  
				  | nxt_Strv1   & ~Reset 
				  | nxt_Strv2   & ~Reset;
		DBLRead          <= nxt_DBLRead & ~Reset;
	end

	assign	i_addren = i_cmdval & Sti;

	assign	i_rdata = i_rdata_sel ?  bdt_datao
				      : (i_addr_reg[2] ^ Strv2) ? DBusIn[31:0]
							        : DBusIn[63:32];

	assign		i_cmdack = 1'b1;
	assign		i_reop   = 1'b1;
	assign		t_eop    = 1'b1;
	assign		t_rspack = 1'b1;
	assign		t_be = 4'b1111;
	assign		t_wdata   = {24'b0,CDataIn[7:0]};


//	assign usb_vbus_vld_n   = ~usb_vbus_vld;
	assign usb_vbus_on_n	= ~usb_vbus_on; 

	always @(posedge usb_clk48) 	// sync to usb clock, just in case
	usb_rst48 <= Reset;

vusb_bvci vusb_bvci0 (
	.clk			(sysclk),
	.rst			(Reset),
	.rst_a			(Reset),
	.usb_clk48		(usb_clk48), 
	.usb_rst48		(usb_rst48),
	.usb_rst48_a		(Reset),
//  BVCI Initiator Interface
	.vusb_i_cmdack		(i_cmdack),
	.vusb_i_rdata		({i_rdata[7:0],
				  i_rdata[15:8],
				  i_rdata[23:16],
				  i_rdata[31:24]}),
	.vusb_i_reop		(i_reop),
	.vusb_i_rspval		(i_rspval),
	.vusb_i_address		(i_address),
	.vusb_i_be		(i_be),
	.vusb_i_cmd		(i_cmd),
	.vusb_i_cmdval		(i_cmdval),
	.vusb_i_eop		(i_eop),
	.vusb_i_rspack		(i_rspack),
	.vusb_i_wdata		({i_wdata[7:0],
				  i_wdata[15:8],
				  i_wdata[23:16],
				  i_wdata[31:24]}),
//  BVCI Target Interface
	.vusb_t_address		(t_address),
	.vusb_t_be		(t_be),
	.vusb_t_cmd		(t_cmd),
	.vusb_t_cmdval		(t_cmdval),
	.vusb_t_eop		(t_eop),
	.vusb_t_rspack		(t_rspack),
	.vusb_t_wdata		(t_wdata),
	.vusb_t_cmdack		(t_cmdack),
	.vusb_t_rdata		(t_rdata),
	.vusb_t_reop		(t_reop),
	.vusb_t_rspval		(t_rspval),
//  Interrupt Out
	.vusb_irq		(irq),
//  USB transceiver interfaces
	.usb_rcv		(usb_rcv),
	.usb_dp			(usb_dp),
	.usb_dm			(usb_dm),
	.usb_vbus_in	(1'b1),
	.usb_dpo		(usb_dpo),
	.usb_dmo		(usb_dmo),
	.usb_oe_n		(usb_oe_n),
	.usb_speed		(usb_speed),
	.usb_suspnd		(usb_suspnd),
//  Pull-Up Resistor Controls
	.usb_dp_high		(usb_dp_high),
	.usb_dp_low_n		(usb_d_low_n),
	.usb_dm_high		(),
	.usb_dm_low_n		(usb_d_low_n),
//  OTG Signals
	.usb_id			    (usb_id),
	.usb_a_vbus_vld		(usb_vbus_vld),
	.usb_sess_vld		(usb_vbus_vld),
	.usb_b_sess_end		(1'b0),
	.usb_vbus_on		(usb_vbus_on),
	.usb_vbus_chg		(),
	.usb_vbus_dschg		()
	);

endmodule