// vi_dummy.v v1 Frank Berndt
// vi dummy for speeding up the simulator;
// using vi_dummy will hang the simulator;
// :set tabstop=4

`timescale 1ns/1ns

module vi_dummy (
	clk, vclk, reset_l,
	cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
	dma_start, dma_last, dma_grant, read_grant, dbus_data, ebus_data,
	dma_request, read_request, vbus_data, vbus_sync, vbus_clock_enable_l,
	vi_int, cbus_din, cbus_dout
);
	input clk;
	input vclk;
	input reset_l;
	input cbus_read_enable;
	input cbus_write_enable;
	input [1:0] cbus_select;
	input [2:0] cbus_command;
	input dma_start;
	input dma_last;
	input dma_grant;
	input read_grant;
	input [63:0] dbus_data;
	input [7:0] ebus_data;
	output dma_request;
	output read_request;
	output [6:0] vbus_data;
	output vbus_sync;
	output vbus_clock_enable_l;
	output vi_int;
	input [31:0] cbus_din;
	output [31:0] cbus_dout;

	initial
		$display("%M: vi not compiled in");

	assign dma_request = 0;
	assign read_request = 0;
	assign vbus_data = 7'd0;
	assign vbus_sync = 0;
	assign vbus_clock_enable_l = 1;
	assign vi_int = 0;
	assign cbus_dout = 32'b0;

endmodule