Makefile
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TARGET_ARCH = linux
include ../../../Makefile.defs
CC = g++
CFLAGS = -fexceptions -freg-struct-return -Wall
INCDIR = -I./ -I$(SYSTEMC_LINUX)/include -I$(PLI_HOME_LINUX)/include -I$(TEST_ROOT)/include -I$(TEST_ROOT)/common_include
COMPILE = $(CC) -g $(CFLAGS) $(INCDIR) -c -fPIC
COMPILE_NC = $(CC) -g $(CFLAGS) $(INCDIR) -c -DNC_USE_VPI_ONLY
LIBDIR = -L$(SYSTEMC_LINUX)/lib-$(TARGET_ARCH) -L/usr/lib
LIBS = -Wl,-Bstatic -lsystemc -lnumeric_bit -lqt -lm
SYS_C_LIB1 = $(SYSTEMC_LINUX)/lib-$(TARGET_ARCH)/libsystemc.a
SYS_C_LIB2 = $(SYSTEMC_LINUX)/lib-$(TARGET_ARCH)/libnumeric_bit.a
SYS_C_LIB3 = $(SYSTEMC_LINUX)/lib-$(TARGET_ARCH)/libqt.a
SYS_C_LIB4 = $(SYSTEMC_LINUX)/lib-$(TARGET_ARCH)/libfx.a
SYS_C_TMP = ./systemc_tmp
COSIM = ../../../bfm/co_simulation
INCDIR_TMP = -I$(SYSTEMC_LINUX)/include -I$(PLI_HOME_LINUX)/include
INCDIR_TMP += -I$(COSIM)/include -I$(COSIM)/common_include
COMPILE_TMP = $(CC) -g $(CFLAGS) $(INCDIR_TMP) -c -fPIC
COMPILE_VCS_TMP = $(CC) -g $(CFLAGS) $(INCDIR_TMP) -c -DUSE_PLI_ONLY
SOURCE_DIR = ../../bfm/co_simulation/tests/vusb/APILevelTestCode
SimSocket:
# Compile for ModemSim
rm -f *.dll
rm -f *.o
$(COMPILE) $(SOURCE_DIR)/*.cpp
$(COMPILE) $(TEST_ROOT)$(PLI_SRC)/*.cpp
$(CC) -shared -fPIC -o SimSocket.dll *.o $(TEST_ROOT)/lib-$(TARGET_ARCH)/*.a $(LIBDIR) $(LIBS)
# Compile for NC
rm -f *.so
rm -f *.o
$(COMPILE_NC) $(SOURCE_DIR)/*.cpp
$(COMPILE_NC) $(TEST_ROOT)$(PLI_SRC)/*.cpp
$(CC) -shared -fPIC -o SimSocketNCVerilog.so *.o $(TEST_ROOT)/lib-$(TARGET_ARCH)/*.a $(LIBDIR) $(LIBS)
vcs:
mkdir -p $(SYS_C_TMP); \
cd $(SYS_C_TMP); \
cp $(TEST_ROOT)/lib-$(TARGET_ARCH)/co_simulation.a . ; \
ar -x co_simulation.a; \
rm -f co_simulation.a; \
$(COMPILE_VCS_TMP) ../../../bfm/co_simulation/src_mti/*.cpp; \
$(COMPILE_TMP) ../$(SOURCE_DIR)/*.cpp; \
ar -x $(SYS_C_LIB1) ; \
ar -x $(SYS_C_LIB2) ; \
ar -x $(SYS_C_LIB3) ; \
ar -x $(SYS_C_LIB4) ; \
ar rc co_simulation_vcs_verilog.a *.o ; \
ranlib co_simulation_vcs_verilog.a; \
mv co_simulation_vcs_verilog.a ../; \
cd ..; \
rm -rf $(SYS_C_TMP)