// Copyright 1994, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

// NOTICE:  THIS IS A "NEAR" MODEL OF AN RDDRAM.  IT SHOULD NOT BE USED
//          FOR TAPEOUT.  USERS OF THIS MODEL SHOULD TAKE SPECIAL CARE
//          TO UNDERSTAND WHAT IT DOES, AND WHAT VALUE IT MAY HAVE FOR
//          ANY DESIGN ACTIVITY.  IT IS DEFINITELY NOT AN ACCURATE MODEL.

// known deficiencies and/or plans for improvement
// . add checking for the sundry timing violations surrounding powerdown
// . RasInterval mechanism is wholly substituted with alternative registers
// . the option to Okay/Nack in tPOSTWRITEDELAY is always a Nack
// . there is no accounting for bit rot in the core from lack of refresh
// . the quickstart mechanism is a total fiction
// . quickstart and reset value selection does not neccessarily represent
//   any actual part, the user of this model should build to suit
// . does not account for the queued RAS behaviour of the 4.5M parts

// module definition for rdram_near_model
// 
module rdram_near_model (
      	RxClk,
	TxClk,
      	BusEnable,
	BusCtrl,
	BusData,
	SIn,
	SOut);

// port declarations
input		RxClk;
input		TxClk;
input		BusEnable;
inout		BusCtrl;
inout	[8:0]	BusData;
input		SIn;
output		SOut;


event load_DeviceID;


reg		BusCtrl_drive;
initial		BusCtrl_drive  = 1'bz;
assign          BusCtrl        = (BusCtrl_drive === 1'b1) 
                                 ? 1'bz : BusCtrl_drive;

reg	[8:0]	BusData_drive;
initial		BusData_drive  = 9'bz;
assign          BusData[8]     = (BusData_drive[8] === 1'b1) 
                                 ? 1'bz : BusData_drive[8];
assign          BusData[7]     = (BusData_drive[7] === 1'b1) 
                                 ? 1'bz : BusData_drive[7];
assign          BusData[6]     = (BusData_drive[6] === 1'b1) 
                                 ? 1'bz : BusData_drive[6];
assign          BusData[5]     = (BusData_drive[5] === 1'b1) 
                                 ? 1'bz : BusData_drive[5];
assign          BusData[4]     = (BusData_drive[4] === 1'b1) 
                                 ? 1'bz : BusData_drive[4];
assign          BusData[3]     = (BusData_drive[3] === 1'b1) 
                                 ? 1'bz : BusData_drive[3];
assign          BusData[2]     = (BusData_drive[2] === 1'b1) 
                                 ? 1'bz : BusData_drive[2];
assign          BusData[1]     = (BusData_drive[1] === 1'b1) 
                                 ? 1'bz : BusData_drive[1];
assign          BusData[0]     = (BusData_drive[0] === 1'b1) 
                                 ? 1'bz : BusData_drive[0];

// octbyte input and output circular buffers, multiple octbytes long
parameter       		inout_bits = 5;
parameter       		circular_buffer_size = 1 << inout_bits;
reg				inEnable[0:circular_buffer_size-1];
reg				inCtrl[0:circular_buffer_size-1];
reg	[8:0]			inData[0:circular_buffer_size-1];
reg				outCtrl[0:circular_buffer_size-1];
reg	[8:0]			outData[0:circular_buffer_size-1];
initial         		init_output_buffers;
reg	[inout_bits-1:0]	inout_counter;
initial         		inout_counter = 0;

// main process for sampling and driving the channel
always @(RxClk)
  // tolerate x on clock and align with counter
  if (RxClk === inout_counter[0])
    begin
      // sample inputs
      inEnable[inout_counter] = ~BusEnable;
      inCtrl[inout_counter]   = ~BusCtrl;
      inData[inout_counter]   = ~BusData;
      // clear drive values for this interval
      outCtrl[inout_counter]  = 0;
      outData[inout_counter]  = 0;
      // increment counter
      inout_counter           = inout_counter + 1;
      // drive outputs for next interval
      BusCtrl_drive           <= ~outCtrl[inout_counter];
      BusData_drive           <= ~outData[inout_counter];
    end
  
// QuarterClock generation - to facilitate integration with an aggregate model
//                           which will activate on the rising edge
wire QuarterClock;
assign QuarterClock = inout_counter[2];

//////////////////////////////////////////////////////////////////////////////
// common section - code below is same for normal and quarter clocks
//                  references should be to the inout buffers and Quarterclock
//////////////////////////////////////////////////////////////////////////////

// true/false in various flavors
parameter true         = 1;
parameter false        = 0;
parameter dirty_if_hit = true;
parameter do_not_dirty = false;

// unit definitions
parameter BusClk_cycle  = 1;		      // define basic unit
parameter BusClk_cycles = BusClk_cycle;
parameter oct           = 8;
parameter SynClk_cycle  = 4 * BusClk_cycle;   // derived
parameter SynClk_cycles = SynClk_cycle;
parameter bc            = 2 * BusClk_cycle;      // bus ticks in a buscycle


// register and/or parameter declarations for device states
                                              // register DeviceType
parameter Version    =      0;
parameter Type       =      0;
parameter corebits   =     18;
parameter BankBits   =      1;
parameter ColumnBits =     11;
parameter RowBits    =      9;
parameter byte       =      9;
parameter octbytes   = 262144;
parameter num_banks  = 1 << BankBits;
parameter columnbits = ColumnBits - 3; // oct
                                              // register DeviceID
parameter IDField_quickstart = 0;
parameter IDField_reset      = 0;
reg       [35:(BankBits+RowBits+columnbits+3)] IDField;
initial   IDField = IDField_quickstart;

                                              // register Delay
parameter WriteBits    = 3;
parameter WriteDelay_quickstart   = (1 * BusClk_cycle) % (1 << WriteBits);
parameter WriteDelay_reset        = (4 * BusClk_cycle) % (1 << WriteBits);
parameter AckBits      = 2;
parameter AckDelay_quickstart     = (3 * BusClk_cycle) % (1 << AckBits);
parameter AckDelay_reset          = (4 * BusClk_cycle) % (1 << AckBits);
parameter ReadBits     = 3;
parameter ReadDelay_quickstart    = (7 * BusClk_cycle) % (1 << ReadBits);
parameter ReadDelay_reset         = (9 * BusClk_cycle) % (1 << ReadBits);
parameter AckWinBits   = 3;
parameter AckWinDelay_quickstart  = (5 * BusClk_cycle) % (1 << AckWinBits);
parameter AckWinDelay_reset       = (12 * BusClk_cycle) % (1 << AckWinBits);
reg       [WriteBits-1:0] WriteDelay;
initial   WriteDelay  = WriteDelay_quickstart;
reg       [AckBits-1:0] AckDelay;
initial   AckDelay    = AckDelay_quickstart;
reg       [ReadBits-1:0] ReadDelay;
initial   ReadDelay   = ReadDelay_quickstart;
reg       [AckWinBits-1:0] AckWinDelay;
initial   AckWinDelay = AckWinDelay_quickstart;

                                              // register Mode
parameter CCValue_quickstart  = 63;
parameter CCValue_reset       = 63;
parameter CCEnable_quickstart = 0;
parameter CCEnable_reset      = 0;
parameter CCMult_quickstart   = 0;
parameter CCMult_reset        = 0;
parameter PwrLng_quickstart   = 0;
parameter PwrLng_reset        = 0;
parameter DevEn_quickstart    = 1;
parameter DevEn_reset         = 0;
reg       [5:0] CCValue;
initial   CCValue = CCValue_quickstart;
reg       CCEnable;
initial   CCEnable = CCEnable_quickstart;
reg       CCMult;
initial   CCMult = CCMult_quickstart;
reg       PwrLng;
initial   PwrLng = PwrLng_quickstart;
reg       DevEn;
initial   DevEn = DevEn_quickstart;

                                              // register RefRow
parameter refresh_row_quickstart  = 0;
parameter refresh_bank_quickstart = 0;
parameter refresh_row_reset       = 0;
parameter refresh_bank_reset      = 0;
reg       [RowBits-1:0]  refresh_row;
initial   refresh_row  = refresh_row_quickstart;
reg       [BankBits-1:0] refresh_bank;
initial   refresh_bank = refresh_bank_quickstart;

                                              // register RasInterval
parameter clean_rowmiss_quickstart =	      // start bit to start bit
            5 * SynClk_cycles + 2 * BusClk_cycles;
parameter dirty_rowmiss_quickstart =	      // start bit to start bit
            7 * SynClk_cycles + 2 * BusClk_cycles;
parameter clean_ras_again_quickstart =	      // start bit to start bit
            9 * SynClk_cycles + 3 * BusClk_cycles;
parameter clean_full_refresh_quickstart =     // data start to start bit
            50 * SynClk_cycles + 2 * BusClk_cycles;
parameter less_row_refresh_quickstart =	      // row reduction for short burst
            4 * SynClk_cycles + 3 * BusClk_cycles;
parameter clean_rowmiss_reset =  
            6 * SynClk_cycles + 2 * BusClk_cycles;
parameter dirty_rowmiss_reset =
            8 * SynClk_cycles + 3 * BusClk_cycles;
parameter clean_ras_again_reset =
            11 * SynClk_cycles;
parameter clean_full_refresh_reset = 
            60 * SynClk_cycles;
parameter less_row_refresh_reset = 
            44 * BusClk_cycles;
integer   clean_rowmiss;
initial   clean_rowmiss      = clean_rowmiss_quickstart;
integer   dirty_rowmiss;
initial   dirty_rowmiss      = dirty_rowmiss_quickstart;
integer   clean_ras_again;
initial   clean_ras_again    = clean_ras_again_quickstart;
integer   clean_full_refresh;
initial   clean_full_refresh = clean_full_refresh_quickstart;
integer   less_row_refresh;
initial   less_row_refresh   = less_row_refresh_quickstart;

                                              // register MinInterval
parameter MinAckDly           = 3 * BusClk_cycles;
parameter MinReadDly          = 7 * BusClk_cycles;
parameter MinWriteDly         = 1 * BusClk_cycle;
parameter MinAckWinDly_offset = (octbytes > 65536) 
                                ? 2 * BusClk_cycles
				: 1 * BusClk_cycles;

                                              // register AddressSelect
parameter SwapField_quickstart = 0;
parameter SwapField_reset      = 0;
reg       [RowBits-1:0] SwapField;
initial   SwapField = SwapField_quickstart;

                                              // register DeviceManufacture
parameter Manufacturer    = 5;
parameter ManufactureCode = 1;

                                              // register Row
parameter valid_row_quickstart = false;
parameter valid_row_reset      = false;
reg	  valid_row[0:num_banks-1];

parameter dirty_row_quickstart = false;
parameter dirty_row_reset      = false;
reg	  dirty_row[0:num_banks-1];

parameter SensedRow_quickstart = 0;
parameter SensedRow_reset      = 0;
reg	  [RowBits-1:0] SensedRow[0:num_banks-1];
initial
  begin :Row_init
    integer bank;
    for (bank = 0; bank < num_banks; bank = bank+1)
      begin
        valid_row[bank] = valid_row_quickstart;
        dirty_row[bank] = dirty_row_quickstart;
        SensedRow[bank] = SensedRow_quickstart;
      end
  end

					      // internal mask_data_register
parameter mask_data_register_quickstart = {oct*byte{1'bx}};
parameter mask_data_register_reset      = {oct*byte{1'bx}};
reg	[oct*byte-1:0]	mask_data_register;
initial mask_data_register = mask_data_register_quickstart;

					      // internal nonseq_byte_mask
parameter nonseq_byte_mask_quickstart = {oct*byte{1'bx}};
parameter nonseq_byte_mask_reset      = {oct*byte{1'bx}};
reg	[oct*byte-1:0]	nonseq_byte_mask[0:oct-1];
initial
  begin :nonseq_byte_mask_init
    integer octbyte_index;
    for (octbyte_index = 0; 
         octbyte_index < oct; 
         octbyte_index = octbyte_index + 1)
      nonseq_byte_mask[octbyte_index] = nonseq_byte_mask_quickstart;
  end
					      
// defined register addresses
parameter DeviceType        =   0;
parameter DeviceID          =   1;
parameter Delay             =   2;
parameter Mode              =   3;
parameter RefRow            =   5;
parameter RasInterval       =   6;
parameter MinInterval       =   7;
parameter AddressSelect     =   8;
parameter DeviceManufacture =   9;
parameter Row               = 128;

// timing specification in bus clock cycles
parameter tMODEARmin             = 254 * BusClk_cycles;
parameter tMODEARmax             = 288 * BusClk_cycles;
parameter tMODEOFFSETmin         =   4 * BusClk_cycles;
parameter tMODEOFFSETmax         =   4 * BusClk_cycles;
  //parameter tSETPDTOPOWERUP    =     * BusClk_cycles;
parameter tPOSTWRITEDELAY        =   2 * BusClk_cycles;
parameter tREGISTERWRITEOVERHEAD =  16 * BusClk_cycles;
  //parameter tSETPDTORESUME     =     * BusClk_cycles;
parameter tSERIALREADOFFSET      =  13 * BusClk_cycles;
parameter tSERIALWRITEOFFSET     =   5 * BusClk_cycles;
initial if (tMODEOFFSETmin !== tMODEOFFSETmax)
  issue_warning("Parameter check failed. tMODEOFFSETmin !== tMODEOFFSETmax.");
initial if (tMODEOFFSETmin !== (4 * BusClk_cycles))
  issue_warning("Model as written implements as thought tMODEOFFSET=4");


// request packet opcodes
parameter Rseq       = 'b000000;
parameter Rnsq       = 'b000001;
parameter RseqAlt    = 'b000100;
parameter RnsqAlt    = 'b000101;
parameter WseqNpb    = 'b010000;
parameter WseqDpb    = 'b010001;
parameter WseqBpb    = 'b010010;
parameter WseqMpb    = 'b010011;
parameter WseqNpbAlt = 'b010100;
parameter WseqDpbAlt = 'b010101;
parameter WseqBpbAlt = 'b010110;
parameter WseqMpbAlt = 'b010111;
parameter Rreg       = 'b011000;
parameter Wreg       = 'b011100;
parameter WnsqNpb    = 'b100000;
parameter WnsqDpb    = 'b100001;
parameter WnsqBpb    = 'b100010;
parameter WnsqMpb    = 'b100011;
parameter WnsqNpbAlt = 'b100100;
parameter WnsqDpbAlt = 'b100101;
parameter WnsqBpbAlt = 'b100110;
parameter WnsqMpbAlt = 'b100111;
parameter WbnsNpb    = 'b110000;
parameter WbnsDpb    = 'b110001;
parameter WbnsMpb    = 'b110011;
parameter WbnsNpbAlt = 'b110100;
parameter WbnsDpbAlt = 'b110101;
parameter WbnsMpbAlt = 'b110111;
parameter WregB      = 'b111100;


// transaction action encodings
parameter inspect_request       = 0;
parameter read_register         = 1;
parameter write_register        = 2;
parameter read_memory           = 3;
parameter write_memory          = 4;
parameter write_bit_mask        = 5;
parameter load_nonseq_byte_mask = 6;
parameter end_read_transaction  = 7;


////////////////////////////////////////////////////////////////////////////////

// counter for number of warning messages
integer			warning;
initial			warning = 0;

// transaction specific registers
reg			transaction_in_progress;
initial                 transaction_in_progress = false;
integer			transaction_action;
reg	[corebits-1:0]	transaction_address;
reg	[6:0]		transaction_octcount;
reg			transaction_sequential;
reg     [6:0]           transaction_first_count;
reg	[oct*byte-1:0]	transaction_first_mask;
reg	[oct*byte-1:0]	transaction_last_mask;
reg			transaction_bit_masking;
reg			transaction_mask_per_bit;
reg			transaction_c_bit_masks;
reg			transaction_c_byte_masks;
reg	[2:0]		transaction_byte_load_modulus;
integer			transaction_dwell;

// non-transaction specific registers
reg     reset;
initial reset = 0;
reg     powerdown;
initial powerdown = false;
integer ack_window;
initial ack_window = 0;
integer smode_maybe_count;
initial smode_maybe_count = 0;
integer smode_asserted_count;
initial smode_asserted_count = 0;
integer quiet_required;
initial quiet_required = 0;
integer cant_accept_request_off3;
initial cant_accept_request_off3 = 0;
integer cant_rowmiss_off3;
initial cant_rowmiss_off3 = 0;
integer cant_start_after_some_wregs_off3;
initial cant_start_after_some_wregs_off3 = 0;
integer pd_to_powerup;
initial pd_to_powerup = 0;


//////////////////////////////////////////////////////////////////////////////

// SOut handling, mirrors SIn when device enabled
assign SOut = SIn & DevEn;

// instantiate the core, maintained as separate module for synthesis ease
reg	[corebits-1:0]	core_write_address;
reg	[oct*byte-1:0]	core_write_data;
reg	[corebits-1:0]	core_read_address;
wire	[oct*byte-1:0]	core_read_data;
rdram0_core #(oct, byte, corebits, octbytes, BankBits, RowBits, columnbits) 
            core (
             .write_address(core_write_address),
	     .write_data(core_write_data),
	     .read_address(core_read_address),
	     .read_data(core_read_data),
	     .reset(reset),
	     .IDField(IDField),
	     .SwapField(SwapField));

// transaction handling and sequential state
integer              bustick;
reg [inout_bits-1:0] tick_current;
// the comment below turns synthesis off for the synopsis tool
// synopsys translate_off
`ifdef debug
always @(negedge inout_counter[0])			 // debug
for (bustick = 0; bustick <= 0; bustick = bustick + 2) // debug
`else
// the comment below turns synthesis on for the synopsis tool
// synopsys translate_on
always @(QuarterClock)
  // expect inout_counter to point after the last cycle received
  for (bustick = -2; bustick <= 0; bustick = bustick + 2)
// the comment below turns synthesis off for the synopsis tool
// synopsys translate_off
`endif
// the comment below turns synthesis on for the synopsis tool
// synopsys translate_on
    begin :channel_action
      // declare temporary local storage for the block
      reg [8:0] Data_temp;
      integer   byte_num;
      reg [oct*byte-1:0] new_data, byte_enable, bit_enable;
      // resolve pointer for circular buffer
      tick_current = io_mod(inout_counter + bustick);
      // adjust non-transaction counters
      ack_window =			 // AckWin period remaining
        (ack_window === -(tSERIALREADOFFSET + tSERIALWRITEOFFSET)) 
	? ack_window : ack_window - 1;
      smode_maybe_count =		 // low bandwidth SMode count
        ((smode(-1*bc) === 0) && (smode(-2*bc) === 0) && (smode(-3*bc) === 0))
	? 0
	: (smode_maybe_count < tMODEARmax)
	  ? smode_maybe_count + 1
	  : smode_maybe_count;
      smode_asserted_count =		 // definite SMode count
        (smode(-1*bc) === 3)
	? (smode_asserted_count < tMODEARmax)
	  ? smode_asserted_count + 1
	  : smode_asserted_count
	: 0;
      quiet_required =			 // period requiring quiet channel
        (quiet_required === 0) ? 0 : quiet_required - 1;
      cant_accept_request_off3 =	 // period of request lockout
        (cant_accept_request_off3 === 0) ? 0 : cant_accept_request_off3 - 1;
      cant_rowmiss_off3 =		 // period unable to do a RAS
        (cant_rowmiss_off3 === 0) ? 0 : cant_rowmiss_off3 - 1;
      cant_start_after_some_wregs_off3 = // period for holdoff after reg write
        (cant_start_after_some_wregs_off3 === 0) 
	? 0 : cant_start_after_some_wregs_off3 - 1;
//      pd_to_powerup =			 // period from setting powerdown
//        (pd_to_powerup < (PwrLng ? tSETPDTOPOWERUPLONG : tSETPDTOPOWERUPSHORT)
//	? pd_to_powerup = pd_to_powerup + 1;
//	: pd_to_powerup;
      // issue warning if not quiet when required
      if ((quiet_required !== 0) &&
          ((inCtrl[io_mod(tick_current-2)] !== 0) || 
	   (inCtrl[io_mod(tick_current-1)] !== 0) ||
           (inData[io_mod(tick_current-2)] !== 0) || 
	   (inData[io_mod(tick_current-1)] !== 0)))
	issue_warning("BusCtrl/BusData not quiet when required.");
      // issue warning if might have reset
      if ((smode_maybe_count) >= tMODEARmin &&
          (reset !== 1'b1) &&
          (smode_asserted_count == 0))
        issue_warning("Possible reset, without definite reset.  Hosed.");
      // reset if clearly across the threshold
      if (smode_asserted_count >= tMODEARmax && (reset !== 1'b1))
        begin :reset_action
          // multiple use index counter
          integer index;
          // show the flag
	  reset = 1;
	  // stop all transactions
	  transaction_in_progress = false;
	  // clear anything posted to the output buffers
	  init_output_buffers;
	  // set registers to the reset value
	  IDField            = IDField_reset;
	  WriteDelay         = WriteDelay_reset;
	  AckDelay           = AckDelay_reset;
	  ReadDelay          = ReadDelay_reset;
	  AckWinDelay        = AckWinDelay_reset;
	  CCValue            = CCValue_reset;
	  CCEnable           = CCEnable_reset;
	  CCMult             = CCMult_reset;
	  PwrLng             = PwrLng_reset;
	  DevEn              = DevEn_reset;
	  refresh_row        = refresh_row_reset;
	  refresh_bank       = refresh_bank_reset;
	  clean_rowmiss      = clean_rowmiss_reset;
	  dirty_rowmiss      = dirty_rowmiss_reset;
	  clean_ras_again    = clean_ras_again_reset;
	  clean_full_refresh = clean_full_refresh_reset;
	  less_row_refresh   = less_row_refresh_reset;
	  SwapField = SwapField_reset;
	  for (index = 0; index < num_banks; index = index+1)
	    begin
	      valid_row[index] = valid_row_reset;
	      dirty_row[index] = dirty_row_reset;
	      SensedRow[index] = SensedRow_reset;
	    end
	  mask_data_register = mask_data_register_reset;
	  for (index = 0; index < oct; index = index + 1)
	    nonseq_byte_mask[index] = nonseq_byte_mask_reset;
	end // reset_action

      // clear reset if definitely deasserted
      if (smode_maybe_count === 0)
	  reset = 0;

      // transaction processing
      transaction_dwell =		 // decrement any remaining dwell time
        (transaction_dwell === 0) ? 0 : transaction_dwell -1;

      if (!transaction_in_progress &&	 // not a transaction in progress
          (reset === 0))		 // and not in reset
        begin
          if (inCtrl[io_mod(tick_current - bc)]) // see start bit
	    begin
	      if (!((ack_window > 0) ||	 // not in AckWindow or powerdown
	            powerdown))
	        begin
                  if ((  (smode((-1 - tMODEOFFSETmin)*bc) === 3)
		      || (smode((-2 - tMODEOFFSETmin)*bc) === 3)
		      || (smode((-3 - tMODEOFFSETmin)*bc) === 3)) && // SMode okay
		      (cant_start_after_some_wregs_off3 === 0)) //!wreg holdoff
		    begin
		      transaction_in_progress = true;
		      transaction_action      = inspect_request;
		      transaction_dwell       = 2; // after last request cycle
		    end
		  else			 // lacking SMode activation
		    begin
		      if (  (smode((-1 - tMODEOFFSETmin)*bc) === 3)
		         || (smode((-2 - tMODEOFFSETmin)*bc) === 3)
		         || (smode((-3 - tMODEOFFSETmin)*bc) === 3))
		        issue_warning("Start bit without SMode activation.");
		      if (cant_start_after_some_wregs_off3 !== 0)
		        issue_warning("Request in a post reg write holdoff.");
		    end
	        end
	    end

	end
      else if (transaction_dwell === 0)	 // transaction in progress, done dwell
	case (transaction_action)	 // next action with transaction
	  inspect_request:
	    begin :inspect_request_action
	      // expect tick_current to be after last cycle of request
	      // temp storage for opcode
	      reg [5:0] opcode;
	      opcode = req_opcode(-3*bc);
	      // set the AckWin counter
	      ack_window = delay(AckWinDelay,
				 AckWinBits,
				 MinAckDly + MinAckWinDly_offset);
	      // act if idmatch and device_enable requirements met
	      if ((req_idmatch(-3*bc) && ((DevEn === 1) || 
					  ((SIn === 1) && 
					   (opcode === Wreg)))) ||
		  (opcode === WregB))
		begin
		  if (cant_accept_request_off3 > 0) // can't handle req
		    begin
		      acknowledge_Nack;
		      transaction_in_progress = false;
		    end
		  else
		    case (opcode)	 // decode opcode
		      Rseq, RseqAlt:
			begin
			  transaction_action       = read_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  core_read_address        = transaction_address;
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = true;
			  transaction_dwell        = delay(ReadDelay,
							   ReadBits,
							   MinReadDly) - 4;
			  continuation_and_ack_based_on_rowhit(do_not_dirty);
			end
		      Rnsq, RnsqAlt:
			begin
			  transaction_action       = read_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  core_read_address        = transaction_address;
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_dwell        = delay(ReadDelay,
							   ReadBits,
							   MinReadDly) - 4;
			  continuation_and_ack_based_on_rowhit(do_not_dirty);
			end
		      WseqNpb, WseqNpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = true;
			  transaction_first_count  = transaction_octcount;
			  transaction_first_mask   = req_first_mask(-3*bc);
			  transaction_last_mask    = req_last_mask(-3*bc);
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WseqDpb, WseqDpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = true;
			  transaction_first_count  = transaction_octcount;
			  transaction_first_mask   = req_first_mask(-3*bc);
			  transaction_last_mask    = req_last_mask(-3*bc);
			  transaction_bit_masking  = true;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WseqBpb, WseqBpbAlt:
			begin
			  transaction_action       = write_bit_mask;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = true;
			  transaction_first_count  = transaction_octcount;
			  transaction_first_mask   = req_first_mask(-3*bc);
			  transaction_last_mask    = req_last_mask(-3*bc);
			  transaction_bit_masking  = true;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = true;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WseqMpb, WseqMpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = true;
			  transaction_first_count  = transaction_octcount;
			  transaction_first_mask   = req_first_mask(-3*bc);
			  transaction_last_mask    = req_last_mask(-3*bc);
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = true;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      Rreg:
			begin
			  transaction_action       = read_register;
			  transaction_address      = req_regaddress(-3*bc);
			  transaction_dwell        = delay(ReadDelay,
							   ReadBits,
							   MinReadDly) - 4;
			  acknowledge_Okay;
			end
		      Wreg:
			begin
			  transaction_action       = write_register;
			  transaction_address      = req_regaddress(-3*bc);
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  acknowledge_Okay;
			end
		      WregB:
			begin
			  transaction_action       = write_register;
			  transaction_address      = req_regaddress(-3*bc);
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  acknowledge_Nonexistent;
			end
		      WnsqNpb, WnsqNpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = false;
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WnsqDpb, WnsqDpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = false;
			  transaction_bit_masking  = true;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WnsqBpb, WnsqBpbAlt:
			begin
			  transaction_action       = write_bit_mask;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = false;
			  transaction_bit_masking  = true;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = true;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WnsqMpb, WnsqMpbAlt:
			begin
			  transaction_action       = write_memory;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = false;
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = true;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WbnsNpb, WbnsNpbAlt:
			begin
			  transaction_action       = load_nonseq_byte_mask;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = true;
			  transaction_byte_load_modulus =
			    transaction_octcount%oct;
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WbnsDpb, WbnsDpbAlt:
			begin
			  transaction_action       = load_nonseq_byte_mask;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = true;
			  transaction_byte_load_modulus =
			    transaction_octcount%oct;
			  transaction_bit_masking  = true;
			  transaction_mask_per_bit = false;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      WbnsMpb, WbnsMpbAlt:
			begin
			  transaction_action       = load_nonseq_byte_mask;
			  transaction_address      = req_octaddress(-3*bc);
			  transaction_octcount     = req_octcount(-3*bc);
			  transaction_sequential   = false;
			  transaction_c_byte_masks = true;
			  transaction_byte_load_modulus =
			    transaction_octcount%oct;
			  transaction_bit_masking  = false;
			  transaction_mask_per_bit = true;
			  transaction_c_bit_masks  = false;
			  transaction_dwell        = delay(WriteDelay,
							   WriteBits,
							   MinWriteDly) + 4;
			  continuation_and_ack_based_on_rowhit(dirty_if_hit);
			end
		      default:
			begin
			  transaction_in_progress  = false;
			  if (req_idmatch(-3*bc))
			    issue_warning("UndefOrRsrv opcode unexpected.");
			end
		    endcase // opcode
		end
	      else // don't act on request, no operation required
		begin
		  transaction_in_progress = false;
		end
	    end // inspect_request
	  read_register:
	    begin
	      // expect tick_current to be at octbyte previous to send data
	      case (transaction_address)
		DeviceType:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      {ColumnBits, 1'b1, byte[0], 2'b0};
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {BankBits[3:0], RowBits[3:0]};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      0;
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      {Version[3:0], Type[3:0]};
		  end
		DeviceID:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      {IDField[25:21], 3'b0};
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {IDField[26], 7'b0};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      {IDField[34:27]};
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      {IDField[35], 7'b0};
		  end
		Delay:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      {AckWinDelay, AckWinBits[2:0]};
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {ReadDelay,   ReadBits[2:0]};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      {AckDelay,    AckBits[2:0]};
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      {WriteDelay,  WriteBits[2:0]};
		  end
		Mode:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      {~CCEnable, ~CCMult, PwrLng, 3'b0,
		       DevEn, 1'b0};
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {CCValue[5], CCValue[2], 6'b0};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      {CCValue[4], CCValue[1], 6'b0};
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      {CCValue[3], CCValue[0], 6'b0};

		  end
		RefRow:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      refresh_row[15-RowBits:0] << (RowBits - 8);
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {refresh_bank, 3'b0};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      refresh_row >> (16 - RowBits);
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      0;
		  end
		RasInterval:
		  begin
		    issue_warning("RasInterval alternatives in use");
		  end
		MinInterval:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      {MinAckDly[3], 
		       MinReadDly[3], 
		       MinWriteDly[3], 5'b0};
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      {MinAckDly[2], 
		       MinReadDly[2], 
		       MinWriteDly[2], 5'b0};
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      {MinAckDly[1], 
		       MinReadDly[1], 
		       MinWriteDly[1], 5'b0};
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      {MinAckDly[0], 
		       MinReadDly[0], 
		       MinWriteDly[0], 5'b0};
		  end
		AddressSelect:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] =
		      SwapField[(7-(columnbits-7)):0] << (columnbits-7);
		    if ((RowBits + columnbits) > 15)
		      outData[io_mod(tick_current+ 4*bc + 1)] =
		        SwapField[RowBits-1:(8-(columnbits-7))];
		  end
		DeviceManufacture:
		  begin
		    outData[io_mod(tick_current+ 4*bc)] = 
		      ManufactureCode[7:0];
		    outData[io_mod(tick_current+ 4*bc + 1)] = 
		      ManufactureCode[15:8];
		    outData[io_mod(tick_current+ 4*bc + 2)] = 
		      Manufacturer[7:0];
		    outData[io_mod(tick_current+ 4*bc + 3)] = 
		      Manufacturer[15:8];
		  end
		Row:
		  begin :read_Row
		    reg [RowBits-1:0] sensed_row;
		    sensed_row = SensedRow[0];
		    outData[io_mod(tick_current+ 4*bc)] =
		      sensed_row[(7-(columnbits-7)):0] << (columnbits-7);
		    if ((RowBits + columnbits) > 15)
		      outData[io_mod(tick_current+ 4*bc + 1)] =
		        sensed_row[RowBits-1:(8-(columnbits-7))];
		    sensed_row = SensedRow[1];
		    outData[io_mod(tick_current+ 4*bc + 2)] =
		      sensed_row[(7-(columnbits-7)):0] << (columnbits-7);
		    if ((RowBits + columnbits) > 15)
		      outData[io_mod(tick_current+ 4*bc + 3)] =
		        sensed_row[RowBits-1:(8-(columnbits-7))];
		  end
		default:
		  issue_warning("Undefined register referenced for read.");
	      endcase
	      // end of transaction
	      transaction_action = end_read_transaction;
	      transaction_dwell = 5;
	    end // read_register
	  write_register:
	    begin
	      // expect tick_current to be aftter last cycle of octbyte
	      // set extensive holdoff for wreg, cleared by some cases
	      cant_start_after_some_wregs_off3 =
		tREGISTERWRITEOVERHEAD + 3;
	      // perform for addressed register
	      case (transaction_address)
		DeviceType:
		  issue_warning("No writable fields in DeviceType");
		DeviceID:
		  begin
		    Data_temp      = inData[io_mod(tick_current-4*bc)];
		    IDField[25:21] = Data_temp[7:3];
		    Data_temp      = inData[io_mod(tick_current-4*bc + 1)];
		    IDField[26]    = Data_temp[7];
		    Data_temp      = inData[io_mod(tick_current-4*bc + 2)];
		    IDField[34:27] = Data_temp[7:0];
		    Data_temp      = inData[io_mod(tick_current-4*bc + 3)];
		    IDField[35]    = Data_temp[7];
		    -> load_DeviceID;
		  end
		Delay:
		  begin
		    Data_temp   = inData[io_mod(tick_current-4*bc)];
		    AckWinDelay = Data_temp[8:3];
		    Data_temp   = inData[io_mod(tick_current-4*bc + 1)];
		    ReadDelay   = Data_temp[8:3];
		    Data_temp   = inData[io_mod(tick_current-4*bc + 2)];
		    AckDelay    = Data_temp[8:3];
		    Data_temp   = inData[io_mod(tick_current-4*bc + 3)];
		    WriteDelay  = Data_temp[8:3];
		  end
		Mode:
		  begin
		    Data_temp   = inData[io_mod(tick_current-4*bc)];
		    CCEnable    = Data_temp[7];
		    CCMult      = Data_temp[6];
		    PwrLng      = Data_temp[5];
		    DevEn       = Data_temp[1];
		    if ({Data_temp[4:3], Data_temp[0]} !== 4'b0)
		      issue_warning("Mode[0] bits 4,3,0 must be 0");
		    Data_temp   = inData[io_mod(tick_current-4*bc + 1)];
		    CCValue[5]  = ~Data_temp[7];
		    CCValue[2]  = ~Data_temp[6];
		    Data_temp   = inData[io_mod(tick_current-4*bc + 2)];
		    CCValue[4]  = ~Data_temp[7];
		    CCValue[1]  = ~Data_temp[6];
		    Data_temp   = inData[io_mod(tick_current-4*bc + 3)];
		    CCValue[3]  = ~Data_temp[7];
		    CCValue[0]  = ~Data_temp[6];
		  end
		RefRow:
		  begin
		    Data_temp    = inData[io_mod(tick_current-4*bc)];
		    refresh_row[15-RowBits:0] = 
				   Data_temp >> (RowBits - 8);
		    Data_temp    = inData[io_mod(tick_current-4*bc + 1)];
		    refresh_bank = Data_temp >> 3;
		    Data_temp    = inData[io_mod(tick_current-4*bc + 2)];
                    refresh_row[RowBits-1:16-RowBits] =
		                   Data_temp;
		  end
		RasInterval:
		  begin
		    // issue_warning("RasInterval alternatives loaded with quickstart values.");
		    clean_rowmiss      = clean_rowmiss_quickstart;
		    dirty_rowmiss      = dirty_rowmiss_quickstart;
		    clean_ras_again    = clean_ras_again_quickstart;
		    clean_full_refresh = clean_full_refresh_quickstart;
		    less_row_refresh   = less_row_refresh_quickstart;
		  end
		MinInterval:
		  begin
		    Data_temp = inData[io_mod(tick_current-4*bc + 3)];
		    case (Data_temp[4:0])
		      5'b00000:
			issue_warning("Write MinInterval did nothing.");
		      5'b00001:
			begin
			  // set timers to measure length of refresh
			  cant_rowmiss_off3 = 
			    (dirty_row[refresh_bank] 
			     ? clean_full_refresh + 
			       (dirty_rowmiss - clean_rowmiss)
			     : clean_full_refresh)
			    - (refresh_row[2:0] * less_row_refresh)
			    - 4 +3;
			  cant_accept_request_off3 = cant_rowmiss_off3;
			  // mark sensed row for bank as valid and clean
			  valid_row[refresh_bank] = true;
			  dirty_row[refresh_bank] = false;
			  // update refresh pointers
			  refresh_bank = refresh_bank + 1;
			  refresh_row[1:0] = 2'b0;
			  refresh_row[(RowBits-1):2]  = 
			    (refresh_bank === 0)
			    ? refresh_row[(RowBits-1):2] + 1
			    : refresh_row[(RowBits-1):2];
			  // special case allows attempting transactions
			  cant_start_after_some_wregs_off3 = 0;
			end
		      5'b00100:
			begin
			  powerdown = true;
			  // quiet_required = tSETPDTORESUME;
			end	
		      default:
			issue_warning("Undefined MinInterval.SpecFunc.");
		    endcase
		  end
		AddressSelect:
		  begin
		    Data_temp = inData[io_mod(tick_current-4*bc)];
                    SwapField[(7-(columnbits-7)):0] = 
		      Data_temp >> (columnbits-7);
		    if ((RowBits + columnbits) > 15)
		      SwapField[RowBits-1:(8-(columnbits-7))] =
		        Data_temp;
		  end
		DeviceManufacture:
		  issue_warning("Nothing writable in DeviceManufacture.");
		Row:
		  issue_warning("Nothing writable in Row register.");
		default:
                  begin
		    // relax holdoff for nonexistent registers
		    cant_start_after_some_wregs_off3 = 0;
		    cant_accept_request_off3 = tPOSTWRITEDELAY + 3;
		    issue_warning("Undefined reg referenced for write.");
		  end
	      endcase
	      // end of transaction
	      transaction_in_progress = false;
	    end // write_register
	  read_memory:
	    begin
	      // expect tick_current to be at octbyte previous to send data
	      outData[io_mod(tick_current+ 4*bc)] = 
		core_read_data[((byte*1)-1):(byte*0)];
	      outData[io_mod(tick_current+ 4*bc + 1)] = 
		core_read_data[((byte*2)-1):(byte*1)];
	      outData[io_mod(tick_current+ 4*bc + 2)] = 
		core_read_data[((byte*3)-1):(byte*2)];
	      outData[io_mod(tick_current+ 4*bc + 3)] = 
		core_read_data[((byte*4)-1):(byte*3)];
	      outData[io_mod(tick_current+ 4*bc + 4)] = 
		core_read_data[((byte*5)-1):(byte*4)];
	      outData[io_mod(tick_current+ 4*bc + 5)] = 
		core_read_data[((byte*6)-1):(byte*5)];
	      outData[io_mod(tick_current+ 4*bc + 6)] = 
		core_read_data[((byte*7)-1):(byte*6)];
	      outData[io_mod(tick_current+ 4*bc + 7)] = 
		core_read_data[((byte*8)-1):(byte*7)];
	      // adjust count, and post next read if not done
	      transaction_octcount = transaction_octcount - 1;
	      if ((transaction_octcount > 0) &&
		  !terminate((+4+4 - tSERIALREADOFFSET)*bc))
		begin
		  if (transaction_sequential)
		    begin
		      transaction_address = 
			transaction_address + 1;
		      core_read_address = transaction_address;
		      if (transaction_address[columnbits-1:0] === 0)
			issue_warning("Transaction passes end of row.");
		    end
		  else
		    transaction_address =
		      {transaction_address[corebits-1:8],
			 serial_address((+4+4 - tSERIALREADOFFSET)*bc)};
		  core_read_address = transaction_address;
		  transaction_dwell = 4;
		end
	      else
		begin
		  transaction_action = end_read_transaction;
		  transaction_dwell  = 5;
		end
	    end // read_memory
	  write_memory:
	    begin
	      // expect tick_current to be after last cycle of data
	      // form octbyte wide byte enable
	      byte_enable =
		transaction_sequential
		? ((transaction_octcount === transaction_first_count)
		   ? transaction_first_mask
		   : {oct*byte{1'b1}})  &
		  ((transaction_octcount === 1)
		      ? transaction_last_mask
		      : {oct*byte{1'b1}})
		: (transaction_c_byte_masks)
		  ? nonseq_byte_mask
		      [(oct - 1) -
		       ((transaction_octcount +
		         (oct - 1) - transaction_byte_load_modulus) % oct)]
		  : {oct*byte{1'b1}};
	      // form octbyte wide bit enables
	      bit_enable = transaction_bit_masking
			   ? mask_data_register
			   : transaction_mask_per_bit
			     ? channel_data(-4*bc)
			     : {oct*byte{1'b1}};
	      // select source for new data, before masking
	      new_data   = transaction_mask_per_bit
			   ? mask_data_register
			   : channel_data(-4*bc);
	      // form and post the write
	      core_write_address = transaction_address;
	      core_write_data = 
		(new_data       &  (byte_enable & bit_enable)) |
		(core_read_data & ~(byte_enable & bit_enable)) |
		// next term reduces mux pessimism with X's
		((new_data ~^ core_read_data) & 
		 new_data & core_read_data);
	      // adjust count, post read,  and decide next action to post
	      transaction_octcount = transaction_octcount - 1;
	      if ((transaction_octcount > 0) &&
		  !terminate(-tSERIALWRITEOFFSET*bc))
		begin
		  if (transaction_sequential)
		    begin
		      transaction_address = 
			transaction_address + 1;
		      core_read_address = transaction_address;
		      if (transaction_address[columnbits-1:0] === 0)
			issue_warning("Transaction passes end of row.");
		    end
		  else
		    transaction_address =
		      {transaction_address[corebits-1:8],
			 serial_address(-tSERIALWRITEOFFSET*bc)};
		  core_read_address = transaction_address;
		  if (transaction_c_bit_masks)
		    transaction_action = write_bit_mask;
		  else if (!transaction_sequential &&
			   transaction_c_byte_masks &&
			   (transaction_octcount%oct ===
			      transaction_byte_load_modulus))
		    transaction_action = load_nonseq_byte_mask;
		  transaction_dwell = 4;
		end
	      else
		begin
		  cant_accept_request_off3 = tPOSTWRITEDELAY + 3;
		  transaction_in_progress = false;
		end
	    end // write_memory
	  write_bit_mask:
	    begin
	      // expect tick_current to be after last cycle of data
	      // load the mask register
	      mask_data_register = channel_data(-4*bc);
	      // adjust count, post read,  and decide next action to post
	      transaction_octcount = transaction_octcount - 1;
	      if ((transaction_octcount > 0) &&
		  !terminate(-tSERIALWRITEOFFSET*bc))
		begin
		  if (!transaction_sequential)
		    begin
		      transaction_address =
		        {transaction_address[corebits-1:8],
			   serial_address(-tSERIALWRITEOFFSET*bc)};
		      core_read_address = transaction_address;
		    end
                  transaction_action = write_memory;
		  transaction_dwell = 4;
		end
	      else
		begin
		  cant_accept_request_off3 = tPOSTWRITEDELAY + 3;
		  transaction_in_progress = false;
		end
	    end // write_bit_mask
	  load_nonseq_byte_mask:
	    begin
	      // expect tick_current to be after last cycle of data
	      // load the byte mask array
	      for (byte_num = 0; byte_num < 8; byte_num = byte_num +1)
		begin
		  Data_temp = inData[io_mod(tick_current-4*bc + byte_num)];
		  nonseq_byte_mask[byte_num] =
		    {{byte{Data_temp[7]}}, {byte{Data_temp[6]}},
		     {byte{Data_temp[5]}}, {byte{Data_temp[4]}},
		     {byte{Data_temp[3]}}, {byte{Data_temp[2]}},
		     {byte{Data_temp[1]}}, {byte{Data_temp[0]}}};
		end
	      // post read, and decide on next action to post
	      if (!terminate(-tSERIALWRITEOFFSET*bc))
		begin
		  transaction_address =
		    {transaction_address[corebits-1:8],
		       serial_address(-tSERIALWRITEOFFSET*bc)};
		  core_read_address = transaction_address;
		  transaction_action = write_memory;
		  transaction_dwell  = 4;
		end
	      else
		begin
		  cant_accept_request_off3 = tPOSTWRITEDELAY + 3;
		  transaction_in_progress = false;
		end
	    end // load_nonseq_byte_mask
	  end_read_transaction:
	    begin
	      // expect tick_current to be after last transaction cycle
	      transaction_in_progress = false;
	    end // end_transaction
	endcase // transaction_action
        // end of else if transaction in progress and no dwell
    end // at posedge QuarterClock step through busticks by 2

// tasks and functions

task continuation_and_ack_based_on_rowhit;
input mark_dirty_if_hit;
reg   mark_dirty_if_hit;
  begin
    // expect tick_current to be after the request packet
    if ((transaction_address[RowBits+columnbits-1:columnbits] ===
           SensedRow[bank(transaction_address)]) && 
	valid_row[bank(transaction_address)])
      begin
        if (mark_dirty_if_hit)
          dirty_row[bank(transaction_address)] = true;
        core_read_address = transaction_address;
        acknowledge_Okay;
      end
    else
      begin
        acknowledge_Nack;
	if (!(cant_rowmiss_off3 > 0))	 // if a rowmiss is possible
          begin
	    if (dirty_row[bank(transaction_address)])
	      begin
		dirty_row[bank(transaction_address)] = false;
		cant_accept_request_off3 = dirty_rowmiss;
		cant_rowmiss_off3 = 
		  clean_ras_again + (dirty_rowmiss - clean_rowmiss);
	      end
	    else
	      begin
		cant_accept_request_off3 = clean_rowmiss;
		cant_rowmiss_off3 = clean_ras_again;
	      end
	    SensedRow[bank(transaction_address)] = 
	      transaction_address[RowBits+columnbits-1:columnbits];
	    valid_row[bank(transaction_address)] = true;
          end
        transaction_in_progress = false;
      end
  end
endtask

function [1:0] smode;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  begin
    tick_origin = io_mod(tick_current + tick_offset);
    smode[0]    = inEnable[tick_origin];
    smode[1]    = inEnable[io_mod(tick_origin+ 1)];
  end
endfunction

function [5:0] req_opcode;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [8:0] Data_temp;
  begin
    tick_origin   = io_mod(tick_current + tick_offset);
    Data_temp     = inData[io_mod(tick_origin + 1)];
    req_opcode[5] = Data_temp[8];
    req_opcode[4] = inCtrl[io_mod(tick_origin + 3)];
    req_opcode[3] = inCtrl[io_mod(tick_origin + 1)];
    Data_temp     = inData[tick_origin];
    req_opcode[2] = Data_temp[8];
    req_opcode[1] = inCtrl[io_mod(tick_origin + 2)];
    req_opcode[0] = inCtrl[io_mod(tick_origin + 4)];
  end
endfunction

function req_idmatch;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [35:10] unswapped_addr;
  reg [35:(BankBits+RowBits+columnbits+3)] requested_device;
  begin
    tick_origin           = io_mod(tick_current + tick_offset);
    unswapped_addr[17:10] = inData[io_mod(tick_origin + 1)];
    unswapped_addr[26:18] = inData[io_mod(tick_origin + 2)];
    unswapped_addr[35:27] = inData[io_mod(tick_origin + 3)];
    requested_device[35:((2*RowBits) + columnbits + 3)] =
      unswapped_addr[35:((2*RowBits) + columnbits + 3)];
    requested_device[((2*RowBits) + columnbits + 3)-1:
                     (BankBits+RowBits+columnbits+3)] =
      (~SwapField & unswapped_addr[((2*RowBits)+columnbits+3)-1:
                                   (BankBits+RowBits+columnbits+3)]) |
      (SwapField  & unswapped_addr[(RowBits+columnbits+3)-1:
                                   (BankBits+columnbits+3)]);
    req_idmatch = (requested_device === IDField) ? true : false;
  end
endfunction

function [(BankBits+RowBits+columnbits+3)-1:3] req_octaddress;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [35:2] unswapped_addr;
  begin
    tick_origin           = io_mod(tick_current + tick_offset);
    unswapped_addr[9:2]   = inData[tick_origin];
    unswapped_addr[17:10] = inData[io_mod(tick_origin + 1)];
    unswapped_addr[26:18] = inData[io_mod(tick_origin + 2)];
    unswapped_addr[35:27] = inData[io_mod(tick_origin + 3)];
    req_octaddress[(columnbits+3)-1:3] =
      unswapped_addr[(columnbits+3)-1:3];
    req_octaddress[(RowBits+columnbits+3)-1:(columnbits+3)] =
      (~SwapField & unswapped_addr[(RowBits+columnbits+3)-1:
                                   (columnbits+3)]) |
      (SwapField  & unswapped_addr[((2*RowBits)+columnbits+3)-1:
                                   (RowBits+columnbits+3)]);
    req_octaddress[(BankBits+RowBits+columnbits+3)-1:
                   (RowBits+columnbits+3)] =
      (SwapField  & unswapped_addr[(BankBits+columnbits+3)-1:
                                   (columnbits+3)]) |
      (~SwapField & unswapped_addr[(BankBits+RowBits+columnbits+3)-1:
                                   (RowBits+columnbits+3)]);
  end
endfunction

function [9:2] req_regaddress;
  input [inout_bits-1:0] tick_offset;
  begin
    req_regaddress = inData[io_mod(tick_current + tick_offset)];
  end
endfunction

function [8:3] req_octcount;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [8:0] Data_temp;
  begin
    tick_origin     = io_mod(tick_current + tick_offset);
    Data_temp       = inData[io_mod(tick_origin + 4)];
    req_octcount[6] = Data_temp[6];
    req_octcount[4] = Data_temp[5];
    Data_temp       = inData[io_mod(tick_origin + 5)];
    req_octcount[7] = Data_temp[6];
    req_octcount[5] = Data_temp[5];
    req_octcount[3] = Data_temp[4];
    req_octcount[8] = 0;
    req_octcount    = req_octcount + 1;
  end
endfunction

function [oct*byte-1:0] req_first_mask;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [2:0] address;
  begin
    tick_origin  = io_mod(tick_current + tick_offset);
    address[2]   = inData[tick_origin];
    address[1:0] = inData[io_mod(tick_origin + 5)];
    req_first_mask = {oct*byte{1'b1}} << address*byte;
  end
endfunction

function [oct*byte-1:0] req_last_mask;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  reg [2:0] count;
  reg [8:0] Data_temp;
  begin
    tick_origin   = io_mod(tick_current + tick_offset);
    Data_temp     = inData[io_mod(tick_origin + 4)];
    count[2]      = Data_temp[4];
    Data_temp     = inData[io_mod(tick_origin + 5)];
    count[1:0]    = Data_temp[3:2];
    req_last_mask = {oct*byte{1'b1}} >> ((7 - count)*byte);
  end
endfunction

function terminate;
  input [inout_bits-1:0] tick_offset;
  begin
    if ((tick_offset + 5 - (ack_window*bc)) >= 0)
      terminate = (inCtrl[io_mod(tick_current + tick_offset + 5)] === 1'b1) 
                  ? true : false;
    else
      terminate = false;
  end
endfunction

function [10:3] serial_address;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  begin
    tick_origin        = io_mod(tick_current + tick_offset);
    serial_address[3]  = inEnable[tick_origin];
    serial_address[4]  = inEnable[io_mod(tick_origin + 1)];
    serial_address[5]  = inEnable[io_mod(tick_origin + 2)];
    serial_address[6]  = inEnable[io_mod(tick_origin + 3)];
    serial_address[7]  = inEnable[io_mod(tick_origin + 4)];
    serial_address[8]  = inEnable[io_mod(tick_origin + 5)];
    serial_address[9]  = inEnable[io_mod(tick_origin + 6)];
    serial_address[10] = inEnable[io_mod(tick_origin + 7)];
  end
endfunction

function [oct*byte-1:0] channel_data;
  input [inout_bits-1:0] tick_offset;
  reg [inout_bits-1:0] tick_origin;
  begin
    tick_origin   = io_mod(tick_current + tick_offset);
    channel_data[(  byte)-1:(0     )] = inData[tick_origin];
    channel_data[(2*byte)-1:(1*byte)] = inData[io_mod(tick_origin + 1)];
    channel_data[(3*byte)-1:(2*byte)] = inData[io_mod(tick_origin + 2)];
    channel_data[(4*byte)-1:(3*byte)] = inData[io_mod(tick_origin + 3)];
    channel_data[(5*byte)-1:(4*byte)] = inData[io_mod(tick_origin + 4)];
    channel_data[(6*byte)-1:(5*byte)] = inData[io_mod(tick_origin + 5)];
    channel_data[(7*byte)-1:(6*byte)] = inData[io_mod(tick_origin + 6)];
    channel_data[(8*byte)-1:(7*byte)] = inData[io_mod(tick_origin + 7)];
  end
endfunction

function [BankBits-1:0] bank;
  input [(BankBits+RowBits+columnbits)-1:0] octbyte_address;
  begin
    bank = octbyte_address[(BankBits+RowBits+columnbits)-1:
                           (RowBits+columnbits)];
  end
endfunction

function [7:0] delay;
  input [5:0] encoded_delay;
  input [2:0] bit_width;
  input [3:0] min_delay;
  begin
    delay = (encoded_delay << (6 - bit_width)) >> (6 - bit_width);
    if (delay < min_delay)
      delay = delay | (1 << bit_width);
  end
endfunction

function [inout_bits-1:0] io_mod;
  input [inout_bits-1:0] pointer;
  begin
    io_mod = pointer;
  end
endfunction  

task acknowledge_Okay;
  reg [7:0] ackdelay;
  begin
    // expect tick_current to be after last cycle of request
    ackdelay = delay(AckDelay, AckBits, MinAckDly);
    outCtrl[io_mod(tick_current + (ackdelay*bc))] = 1;
  end
endtask

task acknowledge_Nack;
  reg [7:0] ackdelay;
  begin
    // expect tick_current to be after last cycle of request
    ackdelay = delay(AckDelay, AckBits, MinAckDly);
    outCtrl[io_mod(tick_current + (ackdelay*bc) + 1)] = 1;
  end
endtask

task acknowledge_Nonexistent;
  begin
    // since values are nonasserted, do not need to do anything
  end
endtask

task init_output_buffers;
  integer tick;
  begin
    for (tick = 0; tick < circular_buffer_size; tick = tick + 1)
      begin
        outCtrl[tick] = 0;
	outData[tick] = 0;
      end
  end
endtask

task issue_warning;
  input string;
  reg [(70*8)-1:0] string;
  begin
    warning = warning + 1;
    // the comment below turns synthesis off for the synopsis tool
    // synopsys translate_off
    $display("%0d %m ** WARNING **: %0s ", $stime, string);
    `ifdef no_stop_on_warning
    `else
      $stop;
    `endif
    // the comment below turns synthesis on for the synopsis tool
    // synopsys translate_on
  end
endtask

endmodule

//////////////////////////////////////////////////////////////////////////////

// the comment below turns synthesis off for the synopsis tool
// synopsys translate_off

module rdram0_core (
	write_address,
	write_data,
	read_address,
	read_data,
	reset,
	IDField,
        SwapField
	);

// parameters, must be the same as enclosing module
parameter oct        =      8;
parameter byte       =      9;
parameter corebits   =     18;
parameter octbytes   = 262144;

parameter BankBits   = 1;
parameter RowBits    = 9;
parameter columnbits = 8;
parameter num_banks  = 1 << BankBits;

// port declarations
input	[corebits-1:0]	write_address;
input	[oct*byte-1:0]	write_data;
input	[corebits-1:0]	read_address;
output	[oct*byte-1:0]	read_data;
input                   reset;
input   [35:(BankBits+RowBits+columnbits+3)] IDField;
input   [RowBits-1:0]   SwapField;

// array  declaration
reg	[oct*byte-1:0]	core [0:octbytes-1];

integer memory_id;
initial memory_id = -1;

// reset operation
reg [corebits:0] address;
always @(posedge reset)
  for (address = 0; address < oct*byte; address = address + 1)
    core[address] = {oct*byte{1'bx}};

// read operation
assign read_data = core[read_address];

// write operation
always @(write_address or write_data) begin
  core[write_address] = write_data;
  
`ifdef MMAP_RDRAM
    if (memory_id >= 0)
    begin
	if ($rdram_mmap_write(memory_id, write_address, write_data) == -1)
	begin
	    $display("Could not write mmap files");
	    $finish;
	end
    end
`endif // MMAP_RDRAM

end


// optional reading of files into memory
always @(rdram_near_model.load_DeviceID) begin : load_rdram
   parameter FILE_NAME = "rdram_reordered_";
   parameter FILE_EXT = ".data";
   reg [7:0] file_number;
   reg [8*20-1:0] file_name;
   integer i;
   reg [3:0] nibble;
   if ($test$plusargs("load_rdram")) begin
      nibble = IDField & 4'hf;
      file_number = nibble + ((nibble > 9) ? "a" - 10 : "0");
      $readmemh({FILE_NAME, file_number, FILE_EXT}, core);
      end
   end
   

`ifdef MMAP_RDRAM
// optional mmap of files  ??? can IDField be used for > 1 rdram?
// initial @(rdram_near_model.load_DeviceID)
always @(rdram_near_model.load_DeviceID)
begin : mmap_rdram
   reg [1:256*8] filename;
   reg [oct*byte-1:0] mmapdata;
   integer offset;

   if ($getstr$plusarg("mmap_rdram=", filename) == 1)
   begin
      memory_id = IDField & 4'hf;
   
      if ($rdram_mmap_init_check(memory_id) == -1)
      begin
         $display("RDRAM mmap files never initialized");
         $finish;
      end
   
      for (offset = 0; offset < octbytes; offset = offset+1)
      begin
         if ($rdram_mmap_read_q(memory_id, offset, mmapdata) == -1)
         begin
            $display("Could not read mmap files %d", offset);
            $finish;
         end
         core[offset] = mmapdata;
      end
   end
end
`endif // MMAP_RDRAM


endmodule // rdram0_core

// synopsys translate_on