synopsys.scr
2.26 KB
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/*----------------------------------------------------------------------
--
-- Copyright (c) 2002 CAST, inc.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this source
-- code file and notify CAST immediately that you inadvertently received
-- an unauthorized copy.
------------------------------------------------------------------------
--
-- Project : AES_CBC_D
--
-- Description : AES Decryption core in CBC Mode
--
-- File : synopsys.scr
--
-- Purpose : Sample Synopsys synthesis script
--
-- Designer : NS
--
-- QA Engineer : JH
--
-- Creation Date : 24-July-2002
--
-- Last Update : 24-July-2002
--
-- Version : 1.0
--
------------------------------------------------------------------------*/
read -format verilog ../src/addmod.v
read -format verilog ../src/ctrl.v
read -format verilog ../src/mem4.v
read -format verilog ../src/mixcol.v
read -format verilog ../src/sbox.v
read -format verilog ../src/main.v
read -format verilog ../src/aes_d.v
read -format verilog ../src/aes_cbc_d.v
create_clock -name "clk" -period 20 -waveform {"0" "10"} {"clk"}
set_dont_touch_network find(clock, "clk")
set_dont_touch_network find(port, "rstn")
set_input_delay -clock clk -max -rise 1.5 all_inputs() - find(port, "clk") - find(port, "rstn")
set_input_delay -clock clk -max -fall 1.5 all_inputs() - find(port, "clk") - find(port, "rstn")
set_input_delay -clock clk -min -rise 1.5 all_inputs() - find(port, "clk") - find(port, "rstn")
set_input_delay -clock clk -min -fall 1.5 all_inputs() - find(port, "clk") - find(port, "rstn")
set_output_delay -clock clk -max -rise 2 all_outputs()
set_output_delay -clock clk -max -fall 2 all_outputs()
set_output_delay -clock clk -min -rise 2 all_outputs()
set_output_delay -clock clk -min -fall 2 all_outputs()
set_max_area 0
uniquify
compile -map_effort medium
report_area
report_timing -path full -delay max -max_paths 1 -nworst 1
write -format db -hierarchy -output aes_cbc_d.db
compile -map_effort medium
report_timing -path full -delay max -max_paths 1 -nworst 1 > report.rep
report_area >> report.rep
report_cell >> report.rep
write -format db -hierarchy -output aes_cbc_d.db
write -format edif -output aes_cbc_d.edf
exit