/*******************************************************************************

-- File Type:    Verilog HDL 
-- Tool Version: VHDL2verilog  v4.4 Tue Sep 19 10:06:32 EDT 2000 SunOS 5.5.1 
-- Input file was: vusb_up_int_bvci
-- Date Created: Tue Jul 16 13:59:59 2002

*******************************************************************************/


`timescale 1 ns / 1 ns // timescale for following modules

// ----------------------------------------------------------------------------
//  Copyright 2000 VAutomation Inc. Nashua NH USA. All rights reserved.
//  This software is provided under license and contains proprietary
//  and confidential material which is the property of VAutomation Inc.
//  HTTP://www.vautomation.com
// ----------------------------------------------------------------------------
//  File Name: $Workfile: vusb_up_int_bvci.vhdl$
//  Revision: $Revision: 1.3 $
//  Description:
// 
//  Description:
//   Synthesizable VHDL description implementing the USB Serial Interface
//   Engine (SIE) Micro Processor Interface with a Basic Virtual
//   Component Interface (BVCI).
// 
//   This logic includes:
// 
//        1) the write register block that is accessed through target
//           cycles over the BVCI,
// 
//        2) Interrupt & error control logic for VUSB 1.1 interface,
// 
//        3) VUSB 1.1 Host Control registers
// 
//        4) Status FIFO implementation
// 
//        5) DMA Logic used to transfer data from/to memory accessed through the
//           BVCI Initiator interface and into/from the RX and TX FIFOs
// 
//        6) Read register block, slave accesses through the BVCI Target
//           Interface,
// 
//        7) Control Data Bus assignment. The control data bus interface defines
//        a common interface to the SIE. This allows designers to modify the
//        micro processor interface and still maintain a common known interface
//        interface to the SIE. See the bottom of this file for Control Data Bus
//        Definitions.
// 
// -----------------------------------------------------------------------------
//  This product is licensed to:
//  John Princen of RouteFree
// for use at site(s):
// broadon
// -----------Revision History--------------------------------------------------
//  $Log: 
//   37   VUSB      1.36        7/12/02 12:12:30 PM    Chris Kolb      Updated 
//         1msec count value for 12MHz clock enable.
//   36   VUSB      1.35        7/5/02 2:54:22 PM      Chris Kolb      syntax
//   35   VUSB      1.34        7/5/02 2:21:33 PM      Chris Kolb      Added 
//         LOW_SPEED_DEVICE constant to dp and dm pull-up equations.
//   34   VUSB      1.33        7/5/02 9:18:36 AM      Chris Kolb      Moved 
//         VUSB build configruation Revision constant to vusb_cfg, and updated 
//         the rev number to 3.0
//   33   VUSB      1.32        7/3/02 4:30:07 PM      Will Sanborn    Linestate
//          interrupt needed to be on bit 5, not bit 6. Also fixed 1ms interrupt
//          to be 1 ms (from shorter durration originally used for testing)
//   32   VUSB      1.31        6/27/02 6:04:03 PM     Will Sanborn    Doc 
//         Change Only: replacing "synopsysTM" in comments with "_synopsysTMTM" to 
//         prevent error with compiler interpreting those comments as pragmas.
//   31   VUSB      1.30        6/25/02 2:33:16 PM     Chris Kolb      Added 
//         Linestate stable status bit and linestate interrupt indication to the
//          OTG registers.
//   30   VUSB      1.29        6/7/02 3:12:29 PM      Tom Frechette   Added 
//         fifo flush signal to dma_wrt/rd_en signals so they reset when the 
//         rest of the system does.
//   29   VUSB      1.28        5/13/02 3:16:12 PM     Will Sanborn    Changing 
//         Reset structure of OTG processes so they will be translated correctly
//          by ChangeReset script.
//   28   VUSB      1.27        4/12/02 2:38:38 PM     Tom Frechette   First 
//         round of OTG Debug -- working.
//   27   VUSB      1.26        4/12/02 10:43:48 AM    Tom Frechette   Debugging
//          otg
//   26   VUSB      1.25        4/11/02 2:49:12 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   25   VUSB      1.24        3/19/02 11:10:34 AM    Tom Frechette   Syntax 
//         error on byte count equal.
//   24   VUSB      1.23        3/18/02 10:52:25 AM    Tom Frechette   Updated 
//         revision field.
//   23   VUSB      1.22        3/15/02 2:39:07 PM     Tom Frechette   Added 
//         Interupt info into add_info register.
//   22   VUSB      1.21        2/11/02 1:37:11 PM     Tom Frechette   Fixed 
//         sync resets for changereset script.
//   21   VUSB      1.20        2/7/02 4:40:34 PM      Tom Frechette   Changed 
//         rst_sync to rst.
//   20   VUSB      1.19        2/7/02 4:02:35 PM      Tom Frechette   Fixed 
//         dma_rd_en stuck when bdt is stalled.
//   19   VUSB      1.18        10/31/01 4:38:40 PM    Tom Frechette   Fixed 
//         typo on endpoint10 stall clear.
//   18   VUSB      1.17        10/30/01 11:05:42 AM   Tom Frechette   Removed 
//         un-necessary logic to get rid synthesis warnings.
//   17   VUSB      1.16        10/9/01 4:02:17 PM     Tom Frechette   
//         Registering stat_we to break async loop.
//   16   VUSB      1.15        10/5/01 7:11:59 AM     Tom Frechette   
//         Simplified CMD_NOP state.
//   15   VUSB      1.14        10/4/01 4:55:25 PM     Tom Frechette   Added 
//         BVCI NOP Support
//   14   VUSB      1.13        10/4/01 10:53:39 AM    Tom Frechette   Fixed 
//         data01_pid to update when writing the bdt. Added fifo flush signal to
//          clear out fifo state machines.
//   13   VUSB      1.12        9/6/01 10:25:37 AM     Tom Frechette   Removed 
//         registered version of current_endpoint on odd_bdt selects
//   12   VUSB      1.11        9/5/01 10:34:05 AM     Tom Frechette   
//         Implemented t_reop functionality; fixed current endpoint
//   11   VUSB      1.10        8/24/01 11:54:02 AM    Tom Frechette   Added 
//         byte enables to target writes.
//   10   VUSB      1.9         8/22/01 2:34:27 PM     Tom Frechette   
//         Registering endpoint and out_data01_pid at the beggining of a packet 
//         only if last is finished.
//   9    VUSB      1.8         8/15/01 2:57:31 PM     Tom Frechette   
//   8    VUSB      1.7         8/13/01 11:05:07 AM    Tom Frechette   Fixed rx 
//         flushing on <8 byte packets.
//   7    VUSB      1.6         7/30/01 11:10:20 AM    Tom Frechette   Changed 
//         cmdack to go low when writes start until rspack comes back.
//   6    VUSB      1.5         7/23/01 2:22:01 PM     Tom Frechette   Fixed ID 
//         regsiter in read mode.
//   5    VUSB      1.4         7/18/01 12:00:33 PM    Tom Frechette   Looking 
//         at empty and full fifo flags instead of the half full.
//   4    VUSB      1.3         7/13/01 11:37:09 AM    Tom Frechette   Added 
//         Peripheral ID Register.
//   3    VUSB      1.2         6/22/01 9:10:00 AM     Tom Frechette   Changed 
//         name of config package
//   2    VUSB      1.1         6/21/01 10:42:33 AM    Tom Frechette   Changed 
//         name.
//   1    VUSB      1.0         6/21/01 9:25:02 AM     Tom Frechette   
//  $
//  $NoKeywords$
// -----------------------------------------------------------------------------
//  Block Diagram:
// 
//  Processor
//  Interface
//   Signals +--------------------+
//           |vusb_up_int_bvci.vhd|
//   ------->+                    |
//           |                    |
//   <-------+                    | cdb_in
//           |                    +--------->
//   ------->+                    |
//           |                    | cdb_out
//   <-------+                    +<---------
//           |                    |
//   <-------+                    |
//           |                    |
//   ------->+                    |
//           |                    |
//           +--------------------+
// 
//  For timing of the busses, see the BVCI specification.
//  
// ------------------------------------------------------------------------------
// ------------------------------------------------------------------------------
//  Copyright 1995 VAutomation Inc. Nashua NH (603)882-2282 ALL RIGHTS RESERVED.
//  This software is provided under license and contains proprietary and 
//  confidential material which is the property of VAutomation Inc.
// 
//  File: vusb_cfg.vhd	USB Configuration file.
// 
//  Revision: $Revision: 1.3 $
// 
//  Description: A Package file for the usb core that defines global usb constants
//      that contol how the VUSB core is synthesised.
// 
// ---------------------------------------------------------------------------
//  This product is licensed to:
//  $name$ of $company$
//  for use at site(s): 
//  $site$
// ------------------------------------------------------------------------------
//  Revision History
//  $Log: 
//   32   VUSB      1.31        7/5/02 9:15:50 AM      Chris Kolb      Moved 
//         VUSB build configruation Revision constant to vusb_cfg, and updated 
//         the rev number to 3.0.
//   31   VUSB      1.30        4/11/02 2:49:09 PM     Patrick Koran   all 
//         checked in from pats pc, week of Starteam upgrade 4.6 to 5.1
//   30   VUSB      1.29        3/18/02 10:52:11 AM    Tom Frechette   Changed 
//         IRQ_NUM default to 0x0.
//   29   VUSB      1.28        3/15/02 2:39:08 PM     Tom Frechette   Added 
//         Interupt info into add_info register.
//   28   VUSB      1.27        2/7/02 4:49:00 PM      Tom Frechette   Removed 
//         sync config variable.
//   27   VUSB      1.26        8/23/01 9:48:58 AM     Tom Frechette   
//   26   VUSB      1.25        7/25/01 3:41:35 PM     Tom Frechette   Changed 
//         FIFO Parameter Names.
//   25   VUSB      1.24        7/10/01 3:03:41 PM     Tom Frechette   Moved 
//         HOST comment for verilog.
//   24   VUSB      1.23        7/6/01 7:44:00 AM      Tom Frechette   Added 
//         host comments around host constant to make it look like vusb_sie.
//   23   VUSB      1.22        7/6/01 7:34:33 AM      Tom Frechette   Added 
//         device constant comment for ARC.
//   22   VUSB      1.21        7/3/01 4:42:08 PM      Tom Frechette   Changed 
//         mode to a constant in vusb_cfg.
//   21   VUSB      1.20        6/22/01 3:09:48 PM     Tom Frechette   Changed 
//         endpoint number.
//   20   VUSB      1.19        6/21/01 9:59:56 AM     Tom Frechette   Changed 
//         the name and added fifo constants
//   19   VUSB      1.18        6/21/01 9:51:24 AM     Tom Frechette   
//   18   VUSB      1.17        5/25/01 10:25:08 AM    Monika Leary    Set 
//         synchronous reset constant to '1'
//   17   VUSB      1.16        5/17/01 2:52:48 PM     Monika Leary    Added 
//         USE_SYNC_RESET constant
//   16   VUSB      1.15        12/14/00 8:42:11 AM    Christopher Meyers RCS 
//         Keyword To StarTeam Keyword Translation
//   15   VUSB      1.14        12/13/00 7:58:39 PM    Chris Kolb      Removed 
//         the HOST_WITHOUT_HUB constant. This control is now a Endpt0 control 
//         register bit in up_int.vhd.
//   14   VUSB      1.13        12/13/00 7:58:31 PM    Gregory Recupero Removed 
//         ^M's
//   13   VUSB      1.12        12/13/00 7:58:26 PM    Mark Pettigrew  
//         ulogicified source - no functional changes
//   12   VUSB      1.11        12/13/00 7:58:19 PM    Chris Kolb      Change 
//         type of HOST_WITHOUT_HUB from std_logic to integer so that it could 
//         be used to initialize a _synopsysTM(TM) compatible generic.
//   11   VUSB      1.10        12/13/00 7:58:14 PM    Chris Kolb      Set 
//         constant to support Host to Low Speed device thru a hub.
//   10   VUSB      1.9         12/13/00 7:58:07 PM    Chris Kolb      Changed 
//         LOW_SPEED_DEV constant to type integer to support generics.
//   9    VUSB      1.8         12/13/00 7:57:58 PM    Christopher Meyers 
//         removed ASIC_IMPLEMENTATION constant
//   8    VUSB      1.7         12/13/00 7:57:46 PM    Chris Kolb      Remove 
//         ^M's. No functional changes.
//   7    VUSB      1.6         12/13/00 7:57:39 PM    Chris Kolb      Added 
//         HOST_WITHOUT_HUB constant to support new code in the DPLLNRZI.
//   6    VUSB      1.5         12/13/00 7:57:19 PM    Chris Kolb      Turned 
//         host mode back on.
//   5    VUSB      1.4         12/13/00 7:57:12 PM    Chris Kolb      Reverted 
//         to device only implementation.
//   4    VUSB      1.3         12/13/00 7:57:08 PM    Chris Kolb      Added 
//         revision string.
//   3    VUSB      1.2         12/13/00 7:57:03 PM    Chris Kolb      Enabled 
//         implementation of embedded host functions.
//   2    VUSB      1.1         12/13/00 7:56:58 PM    Chris Kolb      Added 
//         IMPLEMENT_EMBEDED_HOST constant.
//   1    VUSB      1.0         12/13/00 7:56:51 PM    Chris Kolb      initial 
//         revision
//  $
// 
// 
// ------------------------------------------------------------------------------
module vusb_up_int_bvci (clk,
   rst,
   rst_a,
   sys_clken12,
   i_cmdack,
   i_rdata,
   i_reop,
   i_rspval,
   i_address,
   i_be,
   i_cmd,
   i_cmdval,
   i_eop,
   i_rspack,
   i_wdata,
   t_address,
   t_be,
   t_cmd,
   t_cmdval,
   t_eop,
   t_rspack,
   t_wdata,
   t_cmdack,
   t_rdata,
   t_reop,
   t_rspval,
   vusb_irq,
   cdb_in,
   cdb_out,
   flush,
   rcv,
   se0,
   host_mode_en,
   low_speed_req,
   host_wo_hub,
   usb_en,
   stat_empty,
   stat_full,
   stat_rdata,
   stat_re,
   stat_we,
   stat_wdata,
   rx_empty,
   rx_rdata,
   rx_re,
   tx_full,
   tx_wdata,
   tx_we,
   usb_id,
   usb_sess_vld,
   usb_a_vbus_vld,
   usb_b_sess_end,
   usb_dp_high,
   usb_dm_high,
   usb_dp_low_n,
   usb_dm_low_n,
   usb_vbus_on,
   usb_vbus_chg,
   usb_vbus_dschg);

 		// file containing translation of VHDL package 'vusb_cfg' 

`include "vusb_cfg.v"
input   clk; //  VUSB synthesis and simulation configuration constants.
//  system clock
input   rst; //  sync reset
input   rst_a; //  async reset
input   sys_clken12; //  12 mhz clock enable on sys slock domain
input   i_cmdack; //  init. command acknowledge
input   [31:0] i_rdata; //  init. read data
input   i_reop; //  init. response end of packet
input   i_rspval; //  init. response valid
output   [31:0] i_address; //  init. address
output   [3:0] i_be; //  init. byte enables
output   [1:0] i_cmd; //  init. command
output   i_cmdval; //  init. command valid
output   i_eop; //  init. end of packet
output   i_rspack; //  init. response acknowledge
output   [31:0] i_wdata; //  init. write data
input   [31:0] t_address; //  target address
input   [3:0] t_be; //  target byte enables
input   [1:0] t_cmd; //  target command
input   t_cmdval; //  target command valid
input   t_eop; //  target end of packet
input   t_rspack; //  target response acknowledge
input   [31:0] t_wdata; //  target write data
output   t_cmdack; //  target command acknowledge
output   [31:0] t_rdata; //  target read data
output   t_reop; //  target response end of packet
output   t_rspval; //  target response valid
output   vusb_irq; 
input   [45:0] cdb_in; //  Control/Data bus in
output   [43:0] cdb_out; //  Control/Data bus out
input   flush; //  fifo flush
input   rcv; //  USB data input
input   se0; //  USB single ended zero
output   host_mode_en; //  embedded host controller enable
output   low_speed_req; //  set USB communication to low speed
output   host_wo_hub; //  set USB communication to low speed
output   usb_en; //  USB pull up enable
input   stat_empty; //  status FIFO empty
input   stat_full; //  status FIFO full
input   [7:0] stat_rdata; 
output   stat_re; //  status FIFO read enable
output   stat_we; //  status FIFO write enable
output   [7:0] stat_wdata; 
input   rx_empty; //  Rx FIFO empty
input   [7:0] rx_rdata; //  Rx FIFO read data
output   rx_re; //  Rx FIFO read enable
input   tx_full; //  Tx FIFO full
output   [7:0] tx_wdata; //  Tx FIFO write data
output   tx_we; //  Tx FIFO write enable
input   usb_id; //  id pin from mini connectors
input   usb_sess_vld; //  session valid
input   usb_a_vbus_vld; //  "A" VBUS valid
input   usb_b_sess_end; //  "B" session end
output   usb_dp_high; //  pull up dplus
output   usb_dm_high; //  pull up dminus
output   usb_dp_low_n; //  pull down dplus
output   usb_dm_low_n; //  pull down dminus
output   usb_vbus_on; //  turn on vbus
output   usb_vbus_chg; //  charge vbus
output   usb_vbus_dschg; 
//  system signals
wire    [31:0] i_address; 
wire    [3:0] i_be; 
wire    [1:0] i_cmd; 
wire    i_cmdval; 
wire    i_eop; 
wire    i_rspack; 
//  BVCI Target Interface
wire    [31:0] i_wdata; 
wire    t_cmdack; 
wire    [31:0] t_rdata; 
wire    t_reop; 
//  usb 1.1 interrupt
wire    t_rspval; 
//  Control/Data bus Interface
wire    vusb_irq; 
wire    [43:0] cdb_out; 
wire    host_mode_en; 
wire    low_speed_req; 
wire    host_wo_hub; 
//  Status FIFO Interface
wire    usb_en; 
wire    stat_re; 
reg     stat_we; 
//  RX FIFO Interface
wire    [7:0] stat_wdata; 
wire    rx_re; 
wire    [7:0] tx_wdata; 
//  OTG signals
wire    tx_we; 
wire    usb_dp_high; 
wire    usb_dm_high; 
wire    usb_dp_low_n; 
wire    usb_dm_low_n; 
wire    usb_vbus_on; 
wire    usb_vbus_chg; 
//  discharge vbus    
wire    usb_vbus_dschg; 
parameter ID_FIELD_ADD = 6'b 000000; //  00
parameter ID_COMP_ADD = 6'b 000001; //  04
parameter REV_ADD = 6'b 000010; //  08
parameter ADD_INFO_ADD = 6'b 000011; //  0C
//  otg
parameter OTG_ISTAT_ADD = 6'b 000100; //  10
parameter OTG_ICTRL_ADD = 6'b 000101; //  14
parameter OTG_STAT_ADD = 6'b 000110; //  18
parameter OTG_CTRL_ADD = 6'b 000111; //  1C
parameter INT_STAT_ADD = 6'b 100000; //  80
parameter INT_ENBL_ADD = 6'b 100001; //  84
parameter ERR_STAT_ADD = 6'b 100010; //  88
parameter ERR_ENBL_ADD = 6'b 100011; //  8C
parameter USB_STAT_ADD = 6'b 100100; //  90
parameter USB_CTRL_ADD = 6'b 100101; //  94
parameter USB_ADDR_ADD = 6'b 100110; //  98
parameter BDT_PAG1_ADD = 6'b 100111; //  9C
parameter FRM_NUML_ADD = 6'b 101000; //  A0
parameter FRM_NUMH_ADD = 6'b 101001; //  A4
parameter HST_TOKN_ADD = 6'b 101010; //  A8
parameter SOF_THLD_ADD = 6'b 101011; //  AC
parameter BDT_PAG2_ADD = 6'b 101100; //  B0
parameter BDT_PAG3_ADD = 6'b 101101; //  B4
parameter NOT_USD0_ADD = 6'b 101110; //  B8
parameter NOT_USD1_ADD = 6'b 101111; //  BC
parameter END_CTL0_ADD = 6'b 110000; //  C0
parameter END_CTL1_ADD = 6'b 110001; //  C4
parameter END_CTL2_ADD = 6'b 110010; //  C8
parameter END_CTL3_ADD = 6'b 110011; //  CC
parameter END_CTL4_ADD = 6'b 110100; //  D0
parameter END_CTL5_ADD = 6'b 110101; //  D4
parameter END_CTL6_ADD = 6'b 110110; //  D8
parameter END_CTL7_ADD = 6'b 110111; //  DC
parameter END_CTL8_ADD = 6'b 111000; //  E0
parameter END_CTL9_ADD = 6'b 111001; //  E4
parameter END_CTLA_ADD = 6'b 111010; //  E8
parameter END_CTLB_ADD = 6'b 111011; //  EC
parameter END_CTLC_ADD = 6'b 111100; //  F0
parameter END_CTLD_ADD = 6'b 111101; //  F4
parameter END_CTLE_ADD = 6'b 111110; //  F8
parameter END_CTLF_ADD = 6'b 111111; //  FC
//  ID Field Defines
parameter ID_FIELD = 8'b 00000100; //  04
parameter COMP_ID = 8'b 11111011; //  fb
//  Additional info field
parameter ADD_INFO_HST = 3'b 001; //  01
parameter ADD_INFO_DEV = 3'b 000; //  00
//  bvci commands
parameter CMD_NOP = 2'b 00; 
parameter CMD_RD = 2'b 01; 
parameter CMD_WR = 2'b 10; 
parameter CMD_LCK = 2'b 11; //  not used
// ---------------------------------------------------------------------------
//  bvci target signals
// ---------------------------------------------------------------------------

// TYPE bvci_target_states:
parameter bvci_target_states_BVCI_T_IDLE = 0;
parameter bvci_target_states_BVCI_T_RD_DATA = 1;
parameter bvci_target_states_BVCI_T_WR_DATA = 2;

reg     [1:0] bvci_target_state_r; 
reg     [1:0] bvci_target_state_nxt; 
reg     t_rspval_nxt; 
reg     t_cmdack_nxt; 
reg     t_reop_nxt; 
reg     [7:0] rd_datao_nxt; 
reg     t_rspval_r; 
reg     t_cmdack_r; 
reg     t_reop_r; 
reg     [7:0] rd_datao_r; 
wire    [5:0] addr_i; //  for address decoding
wire    [7:0] rd_datao; //  placeholder for data
wire    [7:0] rd_data_id; //  placeholder for ids
// ---------------------------------------------------------------------------
//  VUSB Microprocessor Registers
// ---------------------------------------------------------------------------
wire    [7:0] int_stat_rg; //  Interrupt status 
reg     [7:0] int_enb_r; //  Interrupt enable 
wire    [7:0] err_stat_rg; //  Error status 
reg     [7:0] err_enb_r; //  Error enable 
reg     [4:0] ctl_r; //  Control 
wire    [7:0] ctl_rg_out; //  Control 
wire    usb_en_int; //  Control reg bit 0
wire    odd_rst; //  Control reg bit 1
reg     [7:0] usb_addr_r; //  Address 
reg     [7:0] bdt_page1_r; //  BDT page 
reg     [7:0] bdt_page2_r; //  BDT page 
reg     [7:0] bdt_page3_r; //  BDT page
wire    [31:0] bdt_addr; //  bdt address
wire    [31:0] bdt_wrt_data; //  bdt write data
// ---------------------------------------------------------------------------
//  Endpoint Registers
// ---------------------------------------------------------------------------
reg     [4:0] endpt0_r; //  Endpoint ctrl reg0
reg     [4:0] endpt1_r; //  Endpoint ctrl reg1
reg     [4:0] endpt2_r; //  Endpoint ctrl reg2
reg     [4:0] endpt3_r; //  Endpoint ctrl reg3
reg     [4:0] endpt4_r; //  Endpoint ctrl reg4
reg     [4:0] endpt5_r; //  Endpoint ctrl reg5
reg     [4:0] endpt6_r; //  Endpoint ctrl reg6
reg     [4:0] endpt7_r; //  Endpoint ctrl reg7
reg     [4:0] endpt8_r; //  Endpoint ctrl reg8
reg     [4:0] endpt9_r; //  Endpoint ctrl reg9
reg     [4:0] endpt10_r; //  Endpoint ctrl reg10
reg     [4:0] endpt11_r; //  Endpoint ctrl reg11
reg     [4:0] endpt12_r; //  Endpoint ctrl reg12
reg     [4:0] endpt13_r; //  Endpoint ctrl reg13
reg     [4:0] endpt14_r; //  Endpoint ctrl reg14
reg     [4:0] endpt15_r; //  Endpoint ctrl reg15
//  these should disappear if these endpoints aren't used
wire    [4:0] endpt4_reg; 
wire    [4:0] endpt5_reg; 
wire    [4:0] endpt6_reg; 
wire    [4:0] endpt7_reg; 
wire    [4:0] endpt8_reg; 
wire    [4:0] endpt9_reg; 
wire    [4:0] endpt10_reg; 
wire    [4:0] endpt11_reg; 
wire    [4:0] endpt12_reg; 
wire    [4:0] endpt13_reg; 
wire    [4:0] endpt14_reg; 
wire    [4:0] endpt15_reg; 
// ---------------------------------------------------------------------------
//  interrupts and error signals & their clears
// ---------------------------------------------------------------------------
reg     stall_int_r; //  stall register
reg     sleep_r; //  Sleep interrupt
reg     resume_r; //  Resume interrupt
reg     sof_tok_r; //  SOF token interrupt
reg     error_r; //  Error interrupt
reg     usb_rst_r; //  USB reset interrupt
reg     bts_err_r; //  Bit stuff error interrupt
reg     own_err_r; //  Own error interrupt
reg     dma_err_r; //  DMA error interrupt
reg     bto_err_r; //  Bus timeout error interrupt
reg     dfn8_err_r; //  Data field not 8-bits error interrupt
reg     crc5_err_r; //  CRC5 error interrupt
reg     crc16_err_r; //  CRC16 error interrupt
reg     pid_err_r; //  PID error interrupt
reg     stall_int_clr_r; 
reg     sleep_clr_r; 
reg     resume_clr_r; 
reg     tok_dne_clr_r; 
reg     sof_tok_clr_r; 
reg     error_clr_r; 
reg     usb_rst_clr_r; 
reg     bts_err_clr_r; 
reg     own_err_clr_r; 
reg     dma_err_clr_r; 
reg     bto_err_clr_r; 
reg     dfn8_err_clr_r; 
reg     crc16_err_clr_r; 
reg     crc5_err_clr_r; 
reg     pid_err_clr_r; 
// ---------------------------------------------------------------------------
//  other register bits
// ---------------------------------------------------------------------------
//  target mode transmit suspend / host mode token busy dual use signal
reg     txdsuspend_tokbusy_r; //  register
wire    endpt_stall; 
// ---------------------------------------------------------------------------
//  control data bus input signals
// ---------------------------------------------------------------------------
wire    txd_token; 
reg     txd_token_r; 
wire    endpt_stall_clr; 
wire    endpt_stall_set; 
wire    txdsuspend_tokbusy_clr; 
wire    txdsuspend_tokbusy_set; 
wire    out_data01_pid; 
reg     out_data01_pid_r; 
wire    [3:0] bdt_wrt_pid; 
wire    [7:0] frm_numh_rg; 
wire    [7:0] frm_numl_rg; 
wire    [3:0] current_endpt; 
reg     [3:0] current_endpt_r; 
wire    tx_datpkt_proc; 
wire    out_token_proc; 
wire    [3:2] sie_dma_req; 
wire    bts_err_set; 
wire    own_err_set; 
wire    dma_err_set; 
wire    bto_err_set; 
wire    dfn8_err_set; 
wire    crc16_err_set; 
wire    crc5_err_set; 
wire    pid_err_set; 
wire    stall_int_set; 
wire    resume_set; 
wire    sleep_set; 
wire    tok_dne_set; 
wire    sof_tok_set; 
wire    error_set; 
wire    usb_rst_set; 
// ---------------------------------------------------------------------------
//  control data bus outputs
// ---------------------------------------------------------------------------
wire    resume_req; 
wire    byte_count_eq; 
wire    [4:0] endpt_ctl; 
// ---------------------------------------------------------------------------
//  host control signals
// ---------------------------------------------------------------------------
wire    hc_en; //  host enable
wire    [7:0] hc_en_byte; 
wire    host_mode_int; //  host enable
wire    hc_rst_req; //  host reset request
reg     hc_token_ld_r; //  load token reg
reg     [7:0] hc_token_r; 
wire    [7:0] hc_token_rg; 
reg     [7:0] hc_sof_thld_r; //  SOF Threshold 
wire    [7:0] hc_sof_thld_rg; //  gated output
wire    [3:0] hc_token_endpt; 
wire    [3:0] hc_token_pid; 
wire    hc_attach; //  attach / detach register
reg     hc_attach_r; 
wire    hc_attach_set; 
wire    host_wo_hub_int; //  host without hub control
reg     host_wo_hub_r; //  host without hub control
wire    hc_retry_disable; //  host retry disabled to SIE
reg     hc_retry_disable_r; //  host retry disabled to SIE
// ---------------------------------------------------------------------------
//  Buffer Discriptor Table (bdt) signals
// ---------------------------------------------------------------------------
reg     [31:0] dma_addr_r; //  DMA address
wire    own; //  own bit (0 = micro, 1 = SIE)
wire    keep; //  keep control bit 
wire    ninc; //  not increment
reg     bdt_valid_r; 
reg     [3:0] bdt_wrt_pid_r; 
reg     [7:0] bdt_rg0_r; //  BDT register0
reg     [7:0] bdt_rg0_nxt; //  BDT register0
reg     [9:0] byte_cnt_r; //  DMA byte count
reg     [9:0] byte_cnt_nxt; //  DMA byte count
wire    bdt_ld; 
reg     [9:0] byte_cntr_r; 
reg     [2:0] txfr_cntr_r; 
// ---------------------------------------------------------------------------
//  Endpoint odd address bits
// ---------------------------------------------------------------------------
wire    endpt_txd_odd; //  Endpoint in odd address bit
reg     endpt0_txd_odd_r; //  Endpoint0 in odd
reg     endpt1_txd_odd_r; //  Endpoint1 in odd
reg     endpt2_txd_odd_r; //  Endpoint2 in odd
reg     endpt3_txd_odd_r; //  Endpoint3 in odd
reg     endpt4_txd_odd_r; //  Endpoint4 in odd
reg     endpt5_txd_odd_r; //  Endpoint5 in odd
reg     endpt6_txd_odd_r; //  Endpoint6 in odd
reg     endpt7_txd_odd_r; //  Endpoint7 in odd
reg     endpt8_txd_odd_r; //  Endpoint8 in odd
reg     endpt9_txd_odd_r; //  Endpoint9 in odd
reg     endpt10_txd_odd_r; //  Endpoint10 in odd
reg     endpt11_txd_odd_r; //  Endpoint11 in odd
reg     endpt12_txd_odd_r; //  Endpoint12 in odd
reg     endpt13_txd_odd_r; //  Endpoint13 in odd
reg     endpt14_txd_odd_r; //  Endpoint14 in odd
reg     endpt15_txd_odd_r; //  Endpoint15 in odd
wire    endpt_rxd_odd; //  Endpoint out odd address bit
reg     endpt0_rxd_odd_r; //  Endpoint0 out odd
reg     endpt1_rxd_odd_r; //  Endpoint1 out odd
reg     endpt2_rxd_odd_r; //  Endpoint2 out odd
reg     endpt3_rxd_odd_r; //  Endpoint3 out odd
reg     endpt4_rxd_odd_r; //  Endpoint4 out odd
reg     endpt5_rxd_odd_r; //  Endpoint5 out odd
reg     endpt6_rxd_odd_r; //  Endpoint6 out odd
reg     endpt7_rxd_odd_r; //  Endpoint7 out odd
reg     endpt8_rxd_odd_r; //  Endpoint8 out odd
reg     endpt9_rxd_odd_r; //  Endpoint9 out odd
reg     endpt10_rxd_odd_r; //  Endpoint10 out odd
reg     endpt11_rxd_odd_r; //  Endpoint11 out odd
reg     endpt12_rxd_odd_r; //  Endpoint12 out odd
reg     endpt13_rxd_odd_r; //  Endpoint13 out odd
reg     endpt14_rxd_odd_r; //  Endpoint14 out odd
reg     endpt15_rxd_odd_r; //  Endpoint15 out odd
// ---------------------------------------------------------------------------
//  token done state machine signals
// ---------------------------------------------------------------------------

// TYPE tok_dne_states:
parameter tok_dne_states_TOK_DNE_IDLE = 0;
parameter tok_dne_states_TOK_DNE_PEND = 1;
parameter tok_dne_states_TOK_DNE_WAIT = 2;
parameter tok_dne_states_TOK_DNE_FIFO = 3;

reg     [1:0] tok_dne_state_r; 
reg     [1:0] tok_dne_state_nxt; 
reg     tok_dne_r; 
reg     tok_dne_nxt; 
// ---------------------------------------------------------------------------
//  rx fifo state machine signals
// ---------------------------------------------------------------------------

// TYPE rxfifo_states:
parameter rxfifo_states_RXFIFO_IDLE = 0;
parameter rxfifo_states_RXFIFO_READ = 1;
parameter rxfifo_states_RXFIFO_WAIT = 2;
parameter rxfifo_states_RXFIFO_DONE = 3;

reg     [1:0] rx_fifo_state_r; 
reg     [1:0] rx_fifo_state_nxt; 
reg     rx_re_r; 
reg     rx_re_nxt; 
reg     [31:0] rx_tdata_r; 
reg     [31:0] rx_tdata_nxt; 
reg     rx_fifo_flush_r; 
reg     dma_wrt_data_r; 
reg     dma_wrt_data_nxt; 
reg     [3:0] dma_be_r; 
reg     [3:0] dma_be_nxt; 
reg     [1:0] rx_fifo_cntr_r; 
reg     [1:0] rx_fifo_cntr_nxt; 
reg     [1:0] flush_cnt_r; 
reg     [1:0] flush_cnt_nxt; 
// ---------------------------------------------------------------------------
//  tx fifo state machine signals
// ---------------------------------------------------------------------------

// TYPE txfifo_states:
parameter txfifo_states_TXFIFO_IDLE = 0;
parameter txfifo_states_TXFIFO_WAIT = 1;
parameter txfifo_states_TXFIFO_WRT = 2;
parameter txfifo_states_TXFIFO_DONE = 3;

reg     [1:0] tx_fifo_state_r; 
reg     [1:0] tx_fifo_state_nxt; 
reg     dma_rd_data_r; 
reg     dma_rd_data_nxt; 
reg     [1:0] tx_fifo_cntr; 
reg     [1:0] tx_fifo_cntr_nxt; 
reg     [31:0] tx_tdata_r; 
reg     [31:0] tx_tdata_nxt; 
reg     [7:0] tx_wdata_r; 
reg     [7:0] tx_wdata_nxt; 
reg     tx_we_r; 
reg     tx_we_nxt; 
// ---------------------------------------------------------------------------
//  dma state machine signals
// ---------------------------------------------------------------------------

// TYPE bvci_states:
parameter bvci_states_BVCI_IDLE = 0;
parameter bvci_states_BVCI_WR_BDT_ACK = 1;
parameter bvci_states_BVCI_WR_BDT_WAIT_RSP = 2;
parameter bvci_states_RD_BDT_WAIT_CMDACK1_D1 = 3;
parameter bvci_states_RD_BDT_WAIT_CMDACK2_D2 = 4;
parameter bvci_states_RD_BDT_WAIT_CMDACK1 = 5;
parameter bvci_states_RD_BDT_WAIT_CMD = 6;
parameter bvci_states_RD_BDT_WAIT_CMDACK2 = 7;
parameter bvci_states_RD_BDT_WAIT_DATA1 = 8;
parameter bvci_states_RD_BDT_WAIT_DATA2 = 9;
parameter bvci_states_RD_BDT_WAIT_DATA1_2 = 10;
parameter bvci_states_BVCI_RD_DATA_ACK = 11;
parameter bvci_states_BVCI_RD_DATA = 12;
parameter bvci_states_BVCI_RD_CMD_ACK = 13;
parameter bvci_states_BVCI_WR_DATA_ACK = 14;
parameter bvci_states_BVCI_WR_DATA = 15;
parameter bvci_states_BVCI_WR_DATA_WAIT_RSP = 16;
parameter bvci_states_BVCI_DMA_TXFR = 17;
parameter bvci_states_BVCI_DMA_DONE = 18;

reg     [4:0] bvci_state_r; 
reg     [4:0] bvci_state_nxt; 
wire    dma_overrun; 
reg     dma_req_clr_r; 
reg     dma_req_clr_nxt; 
reg     wrt_bdt_clr_r; 
reg     wrt_bdt_clr_nxt; 
reg     rd_bdt_clr_r; 
reg     rd_bdt_clr_nxt; 
wire    odd_bdt; 
reg     odd_bdt_r; 
reg     dma_rd_en_r; 
reg     dma_wrt_en_r; 
reg     dma_rd_bdt_r; 
reg     dma_wrt_bdt_r; 
reg     dma_wrt_bdt_lat_r; 
reg     end_cycle_r; 
wire    byte_cnt_inc; 
// ---------------------------------------------------------------------------
//  bvci initiator signals
// ---------------------------------------------------------------------------
reg     [31:0] i_addr_r; 
reg     [3:0] i_be_r; 
reg     [1:0] i_cmd_r; 
reg     i_cmdval_r; 
reg     i_eop_r; 
reg     [31:0] i_wdata_r; 
reg     [31:0] i_addr_nxt; 
reg     [3:0] i_be_nxt; 
reg     [1:0] i_cmd_nxt; 
reg     i_cmdval_nxt; 
reg     i_eop_nxt; 
reg     [31:0] i_wdata_nxt; 
// ---------------------------------------------------------------------------
//  additional info reg
// ---------------------------------------------------------------------------
wire    [7:0] add_info; 
// ----------------------------------------------------------------------------------------------------------
//  otg signals
// ----------------------------------------------------------------------------------------------------------
wire    [7:0] otg_istat; 
reg     [7:0] otg_ictrl_r; 
wire    [7:0] otg_stat; 
reg     [7:0] otg_ctrl_r; 
//  interrupt enables
wire    usb_id_int_en; 
wire    usb_1msec_int_en; 
wire    usb_linestate_int_en; 
wire    usb_b_sess_end_int_en; 
wire    usb_sess_vld_int_en; 
wire    usb_a_vbus_vld_int_en; 
//  interrupt registers
reg     usb_id_int_r; 
reg     usb_1msec_int_r; 
reg     usb_linestate_int_r; 
reg     usb_b_sess_end_int_r; 
reg     usb_sess_vld_int_r; 
reg     usb_a_vbus_vld_int_r; 
//  interrupt clear signals
reg     usb_id_int_clr_r; 
reg     usb_1msec_int_clr_r; 
reg     usb_linestate_int_clr_r; 
reg     usb_b_sess_end_int_clr_r; 
reg     usb_sess_vld_int_clr_r; 
reg     usb_a_vbus_vld_int_clr_r; 
wire    hc_usb_id_int_clr; 
wire    hc_usb_1msec_int_clr; 
wire    hc_usb_linestate_int_clr; 
wire    hc_usb_b_sess_end_int_clr; 
wire    hc_usb_sess_vld_int_clr; 
wire    hc_usb_a_vbus_vld_int_clr; 
//  combined otg interrupt
wire    otg_int; 
//  sync signals
reg     usb_id_r1; 
reg     usb_id_r2; 
reg     usb_sess_vld_r1; 
reg     usb_sess_vld_r2; 
reg     usb_b_sess_end_r1; 
reg     usb_b_sess_end_r2; 
reg     usb_a_vbus_vld_r1; 
reg     usb_a_vbus_vld_r2; 
wire    hc_usb_id_r2; 
wire    hc_usb_sess_vld_r2; 
wire    hc_usb_b_sess_end_r2; 
wire    hc_usb_a_vbus_vld_r2; 
//  1 msec latch signals
reg     otg_stable_id_r; 
reg     otg_stable_se0_r; 
reg     otg_stable_jstate_r; 
wire    otg_stable_linestate; 
reg     otg_stable_linestate_r; 
reg     otg_stable_sess_vld_r; 
reg     otg_stable_b_sess_end_r; 
reg     otg_stable_a_vbus_vld_r; 
wire    hc_otg_stable_id; 
wire    hc_otg_stable_se0; 
wire    hc_otg_stable_jstate; 
wire    hc_otg_stable_linestate; 
wire    hc_otg_stable_sess_vld; 
wire    hc_otg_stable_b_sess_end; 
wire    hc_otg_stable_a_vbus_vld; 
//  debounce signals
reg     usb_id_deb_r; 
reg     usb_se0_deb_r; 
reg     usb_jstate_deb_r; 
reg     usb_sess_vld_deb_r; 
reg     usb_b_sess_end_deb_r; 
reg     usb_a_vbus_vld_deb_r; 
wire    hc_usb_id_deb; 
wire    hc_usb_se0_deb; 
wire    hc_usb_jstate_deb; 
wire    hc_usb_sess_vld_deb; 
wire    hc_usb_b_sess_end_deb; 
wire    hc_usb_a_vbus_vld_deb; 
//  last value signals
reg     usb_id_last_r; 
reg     usb_se0_last_r; 
reg     usb_jstate_last_r; 
reg     usb_sess_vld_last_r; 
reg     usb_b_sess_end_last_r; 
reg     usb_a_vbus_vld_last_r; 
wire    hc_usb_id_last; 
wire    hc_usb_se0_last; 
wire    hc_usb_jstate_last; 
wire    hc_usb_sess_vld_last; 
wire    hc_usb_b_sess_end_last; 
wire    hc_usb_a_vbus_vld_last; 
wire    lsdev; 
// ----------------------------------------------------------------------------------------------------------
//  1 msec timer signals
// ----------------------------------------------------------------------------------------------------------
parameter ONE_MS_TMR_LD = {2'b 10, 4'b 1110, 4'b 1101, 4'b 1111}; //  2edfh = 12,000
reg     [13:0] usb_1msec_tmr_r; 
reg     usb_1msec_r; 
wire    hc_usb_1msec; 
// ---------------------------------------------------------------------------
//  code begins here
// ---------------------------------------------------------------------------
// -------------------------------------------------------------------------
//  misc stuff
// -------------------------------------------------------------------------

assign usb_en = usb_en_int; 
// -------------------------------------------------------------------------
//  BVCI Target State Machine
// -------------------------------------------------------------------------
always @(t_cmdval or t_cmd or t_rspack or rd_datao or rd_datao_r
 or t_rspval_r or t_reop_r or t_cmdack_r or bvci_target_state_r or t_eop)
   begin : bvci_target_state_nxt_PROC
   rd_datao_nxt <= rd_datao_r;	
   bvci_target_state_nxt <= bvci_target_state_r;	
   t_rspval_nxt <= t_rspval_r;	
   t_cmdack_nxt <= t_cmdack_r;	
   t_reop_nxt <= t_reop_r;	
   case (bvci_target_state_r)
   bvci_target_states_BVCI_T_IDLE:
      begin
      if (t_cmdval == 1'b 1 & (t_cmd == CMD_RD | 
	t_cmd == CMD_NOP))
         begin
         t_cmdack_nxt <= 1'b 0;	
         t_rspval_nxt <= 1'b 1;	
         t_reop_nxt <= t_eop;	
         rd_datao_nxt <= rd_datao;	
         bvci_target_state_nxt <= bvci_target_states_BVCI_T_RD_DATA;	
         end
      else if (t_cmdval == 1'b 1 & t_cmd == CMD_WR )
         begin
         t_cmdack_nxt <= 1'b 0;	
         t_rspval_nxt <= 1'b 1;	
         t_reop_nxt <= t_eop;	
         bvci_target_state_nxt <= bvci_target_states_BVCI_T_WR_DATA;	
         end
      end
//  for a read or nop do a read cycle
   bvci_target_states_BVCI_T_RD_DATA:
      begin
      if (t_rspack == 1'b 1)
         begin
         t_cmdack_nxt <= 1'b 1;	
         t_rspval_nxt <= 1'b 0;	
         t_reop_nxt <= 1'b 0;	
         bvci_target_state_nxt <= bvci_target_states_BVCI_T_IDLE;	
         end
      end
   bvci_target_states_BVCI_T_WR_DATA:
      begin
      if (t_rspack == 1'b 1)
         begin
         t_cmdack_nxt <= 1'b 1;	
         t_rspval_nxt <= 1'b 0;	
         t_reop_nxt <= 1'b 0;	
         bvci_target_state_nxt <= bvci_target_states_BVCI_T_IDLE;	
         end
      end
   default:
      begin
      t_cmdack_nxt <= 1'b 1;	
      t_rspval_nxt <= 1'b 0;	
      t_reop_nxt <= 1'b 0;	
      rd_datao_nxt <= {8{1'b 0}};	
      bvci_target_state_nxt <= bvci_target_states_BVCI_T_IDLE;	
      end
   endcase
   end
// -------------------------------------------------------------------------
//  sync part of state machine
// -------------------------------------------------------------------------
//  assign default values
always @(posedge clk or posedge rst_a)
   begin : bvci_target_state_r_PROC
   if (rst_a == 1'b 1)
      begin
      t_cmdack_r <= 1'b 1;	
      t_rspval_r <= 1'b 0;	
      t_reop_r <= 1'b 0;	
      rd_datao_r <= {8{1'b 0}};	
      bvci_target_state_r <= bvci_target_states_BVCI_T_IDLE;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         t_cmdack_r <= 1'b 1;	
         t_rspval_r <= 1'b 0;	
         t_reop_r <= 1'b 0;	
         rd_datao_r <= {8{1'b 0}};	
         bvci_target_state_r <= bvci_target_states_BVCI_T_IDLE;	
         end
      else
         begin
         t_cmdack_r <= t_cmdack_nxt;	
         t_rspval_r <= t_rspval_nxt;	
         t_reop_r <= t_reop_nxt;	
         rd_datao_r <= rd_datao_nxt;	
         bvci_target_state_r <= bvci_target_state_nxt;	
         end
      end
   end
//  drive out bvci signals
assign t_reop = t_reop_r; 
assign t_rspval = t_rspval_r; 
assign t_cmdack = t_cmdack_r; 
assign t_rdata = {8'b 00000000, 8'b 00000000, 8'b 00000000, rd_datao_r}; 
//  pick off address bus for decode
assign addr_i = t_address[7:2]; 
// -------------------------------------------------------------------------
//  Implement microprocessor interface registers
// -------------------------------------------------------------------------
//  interrupt enable register
always @(posedge clk or posedge rst_a)
   begin : int_enb_r_PROC
   if (rst_a == 1'b 1)
      begin
      int_enb_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         int_enb_r <= {8{1'b 0}};	
         end
      else if (addr_i == INT_ENBL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         int_enb_r <= t_wdata[7:0];	
         end
      end
   end
//  error enable register
always @(posedge clk or posedge rst_a)
   begin : err_enb_r_PROC
   if (rst_a == 1'b 1)
      begin
      err_enb_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         err_enb_r <= {8{1'b 0}};	
         end
      else if (addr_i == ERR_ENBL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         err_enb_r <= t_wdata[7:0];	
         end
      end
   end
//  control register
always @(posedge clk or posedge rst_a)
   begin : ctl_r_PROC
   if (rst_a == 1'b 1)
      begin
      ctl_r <= {5{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         ctl_r <= {5{1'b 0}};	
         end
      else if (addr_i == USB_CTRL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         ctl_r <= t_wdata[4:0];	
         end
      end
   end
//  this bit is used in device and host mode, in device mode it is set by
//  the sie when a token has been processed, the processor should clear this
//  bit when it's done with the token.
//  in host mode the processor sets this bit by writing data pin 4 in the
//  token register, (hc_token_ld), the sie will clear this bit when he is
//  done with transmitting the token
always @(posedge clk or posedge rst_a)
   begin : txsusp_r_PROC
   if (rst_a == 1'b 1)
      begin
      txdsuspend_tokbusy_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         txdsuspend_tokbusy_r <= 1'b 0;	
         end
      else if (addr_i == USB_CTRL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         txdsuspend_tokbusy_r <= t_wdata[5];	
         end
      else if (txdsuspend_tokbusy_clr == 1'b 1 )
         begin
         txdsuspend_tokbusy_r <= 1'b 0;	
         end
      else if (txdsuspend_tokbusy_set == 1'b 1 | hc_token_ld_r == 1'b 1 )
         begin
         txdsuspend_tokbusy_r <= 1'b 1;	
         end
      end
   end
//  address register
always @(posedge clk or posedge rst_a)
   begin : usb_addr_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_addr_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_addr_r <= {8{1'b 0}};	
         end
      else if (addr_i == USB_ADDR_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         usb_addr_r <= t_wdata[7:0];	
         end
      end
   end
//  assign bit 7 to low speed signal
assign low_speed_req = usb_addr_r[7]; 
//  bdt page registers
always @(posedge clk or posedge rst_a)
   begin : bdt_page_r_PROC
   if (rst_a == 1'b 1)
      begin
      bdt_page1_r <= {8{1'b 0}};	
      bdt_page2_r <= {8{1'b 0}};	
      bdt_page3_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         bdt_page1_r <= {8{1'b 0}};	
         bdt_page2_r <= {8{1'b 0}};	
         bdt_page3_r <= {8{1'b 0}};	
         end
      else
         begin
         if (addr_i == BDT_PAG1_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            bdt_page1_r <= t_wdata[7:0];	
            end
         if (addr_i == BDT_PAG2_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            bdt_page2_r <= t_wdata[7:0];	
            end
         if (addr_i == BDT_PAG3_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            bdt_page3_r <= t_wdata[7:0];	
            end
         end
      end
   end
//  assembly the address for ease of use, take the upper 16 bits which are
//  stored in bdt page regs 3 & 2. The lower 16 bits of the address are bdt
//  page reg 1 bits 7:1 and then the endpoint, direction and odd bits. Each
//  descriptor takes up 8 bytes. Each endpoint takes 4 descriptors; 2 for
//  each direction.
assign bdt_addr = {bdt_page3_r, bdt_page2_r, bdt_page1_r[7:1], current_endpt_r, 
	txd_token_r, odd_bdt_r, 3'b 000}; //  9 bits
//  7 bits
//  assembly the write data for writing the bdt back
//  DATA01=out_data01_pid if out or setup token else it is bdt_rg(6)
assign bdt_wrt_data[31:26] = {6{1'b 0}}; 
assign bdt_wrt_data[25:16] = byte_cntr_r; 
assign bdt_wrt_data[15:8] = {8{1'b 0}}; 
assign bdt_wrt_data[7:0] = {(bdt_rg0_r[7] & bdt_rg0_r[5]), (out_data01_pid_r & ~txd_token_r | 
	bdt_rg0_r[6] & txd_token_r), bdt_wrt_pid_r, 2'b 00}; 
//  endpoint control registers
always @(posedge clk or posedge rst_a)
   begin : endpt_r_PROC
   if (rst_a == 1'b 1)
      begin
      endpt0_r <= {5{1'b 0}};	
      endpt1_r <= {5{1'b 0}};	
      endpt2_r <= {5{1'b 0}};	
      endpt3_r <= {5{1'b 0}};	
      endpt4_r <= {5{1'b 0}};	
      endpt5_r <= {5{1'b 0}};	
      endpt6_r <= {5{1'b 0}};	
      endpt7_r <= {5{1'b 0}};	
      endpt8_r <= {5{1'b 0}};	
      endpt9_r <= {5{1'b 0}};	
      endpt10_r <= {5{1'b 0}};	
      endpt11_r <= {5{1'b 0}};	
      endpt12_r <= {5{1'b 0}};	
      endpt13_r <= {5{1'b 0}};	
      endpt14_r <= {5{1'b 0}};	
      endpt15_r <= {5{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         endpt0_r <= {5{1'b 0}};	//  endpoint 0
         endpt1_r <= {5{1'b 0}};	
         endpt2_r <= {5{1'b 0}};	
         endpt3_r <= {5{1'b 0}};	
         endpt4_r <= {5{1'b 0}};	
         endpt5_r <= {5{1'b 0}};	
         endpt6_r <= {5{1'b 0}};	
         endpt7_r <= {5{1'b 0}};	
         endpt8_r <= {5{1'b 0}};	
         endpt9_r <= {5{1'b 0}};	
         endpt10_r <= {5{1'b 0}};	
         endpt11_r <= {5{1'b 0}};	
         endpt12_r <= {5{1'b 0}};	
         endpt13_r <= {5{1'b 0}};	
         endpt14_r <= {5{1'b 0}};	
         endpt15_r <= {5{1'b 0}};	
         end
      else
         begin
         if (addr_i == END_CTL0_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt0_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0000 & endpt_stall_set == 1'b 1 )
            begin
            endpt0_r <= {endpt0_r[4:2], 1'b 1, endpt0_r[0]};	
            end
         else if (current_endpt_r == 4'b 0000 & endpt_stall_clr == 1'b 1 )
            begin
            endpt0_r <= {endpt0_r[4:2], 1'b 0, endpt0_r[0]};	
//  endpoint 1
            end
         if (addr_i == END_CTL1_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt1_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0001 & endpt_stall_set == 1'b 1 )
            begin
            endpt1_r <= {endpt1_r[4:2], 1'b 1, endpt1_r[0]};	
            end
         else if (current_endpt_r == 4'b 0001 & endpt_stall_clr == 1'b 1 )
            begin
            endpt1_r <= {endpt1_r[4:2], 1'b 0, endpt1_r[0]};	
//  endpoint 2
            end
         if (addr_i == END_CTL2_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt2_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0010 & endpt_stall_set == 1'b 1 )
            begin
            endpt2_r <= {endpt2_r[4:2], 1'b 1, endpt2_r[0]};	
            end
         else if (current_endpt_r == 4'b 0010 & endpt_stall_clr == 1'b 1 )
            begin
            endpt2_r <= {endpt2_r[4:2], 1'b 0, endpt2_r[0]};	
//  endpoint 3
            end
         if (addr_i == END_CTL3_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt3_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0011 & endpt_stall_set == 1'b 1 )
            begin
            endpt3_r <= {endpt3_r[4:2], 1'b 1, endpt3_r[0]};	
            end
         else if (current_endpt_r == 4'b 0011 & endpt_stall_clr == 1'b 1 )
            begin
            endpt3_r <= {endpt3_r[4:2], 1'b 0, endpt3_r[0]};	
//  endpoint 4
            end
         if (addr_i == END_CTL4_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt4_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0100 & endpt_stall_set == 1'b 1 )
            begin
            endpt4_r <= {endpt4_r[4:2], 1'b 1, endpt4_r[0]};	
            end
         else if (current_endpt_r == 4'b 0100 & endpt_stall_clr == 1'b 1 )
            begin
            endpt4_r <= {endpt4_r[4:2], 1'b 0, endpt4_r[0]};	
//  endpoint 5
            end
         if (addr_i == END_CTL5_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt5_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0101 & endpt_stall_set == 1'b 1 )
            begin
            endpt5_r <= {endpt5_r[4:2], 1'b 1, endpt5_r[0]};	
            end
         else if (current_endpt_r == 4'b 0101 & endpt_stall_clr == 1'b 1 )
            begin
            endpt5_r <= {endpt5_r[4:2], 1'b 0, endpt5_r[0]};	
//  endpoint 6
            end
         if (addr_i == END_CTL6_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt6_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0110 & endpt_stall_set == 1'b 1 )
            begin
            endpt6_r <= {endpt6_r[4:2], 1'b 1, endpt6_r[0]};	
            end
         else if (current_endpt_r == 4'b 0110 & endpt_stall_clr == 1'b 1 )
            begin
            endpt6_r <= {endpt6_r[4:2], 1'b 0, endpt6_r[0]};	
//  endpoint 7
            end
         if (addr_i == END_CTL7_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt7_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 0111 & endpt_stall_set == 1'b 1 )
            begin
            endpt7_r <= {endpt7_r[4:2], 1'b 1, endpt7_r[0]};	
            end
         else if (current_endpt_r == 4'b 0111 & endpt_stall_clr == 1'b 1 )
            begin
            endpt7_r <= {endpt7_r[4:2], 1'b 0, endpt7_r[0]};	
//  endpoint 8
            end
         if (addr_i == END_CTL8_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt8_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1000 & endpt_stall_set == 1'b 1 )
            begin
            endpt8_r <= {endpt8_r[4:2], 1'b 1, endpt8_r[0]};	
            end
         else if (current_endpt_r == 4'b 1000 & endpt_stall_clr == 1'b 1 )
            begin
            endpt8_r <= {endpt8_r[4:2], 1'b 0, endpt8_r[0]};	
//  endpoint 9
            end
         if (addr_i == END_CTL9_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt9_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1001 & endpt_stall_set == 1'b 1 )
            begin
            endpt9_r <= {endpt9_r[4:2], 1'b 1, endpt9_r[0]};	
            end
         else if (current_endpt_r == 4'b 1001 & endpt_stall_clr == 1'b 1 )
            begin
            endpt9_r <= {endpt9_r[4:2], 1'b 0, endpt9_r[0]};	
//  endpoint 10
            end
         if (addr_i == END_CTLA_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt10_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1010 & endpt_stall_set == 1'b 1 )
            begin
            endpt10_r <= {endpt10_r[4:2], 1'b 1, endpt10_r[0]};	
            end
         else if (current_endpt_r == 4'b 1010 & endpt_stall_clr == 1'b 1 )
            begin
            endpt10_r <= {endpt10_r[4:2], 1'b 0, endpt10_r[0]};	
//  endpoint 11
            end
         if (addr_i == END_CTLB_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt11_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1011 & endpt_stall_set == 1'b 1 )
            begin
            endpt11_r <= {endpt11_r[4:2], 1'b 1, endpt11_r[0]};	
            end
         else if (current_endpt_r == 4'b 1011 & endpt_stall_clr == 1'b 1 )
            begin
            endpt11_r <= {endpt11_r[4:2], 1'b 0, endpt11_r[0]};	
//  endpoint 12
            end
         if (addr_i == END_CTLC_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt12_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1100 & endpt_stall_set == 1'b 1 )
            begin
            endpt12_r <= {endpt12_r[4:2], 1'b 1, endpt12_r[0]};	
            end
         else if (current_endpt_r == 4'b 1100 & endpt_stall_clr == 1'b 1 )
            begin
            endpt12_r <= {endpt12_r[4:2], 1'b 0, endpt12_r[0]};	
//  endpoint 13
            end
         if (addr_i == END_CTLD_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt13_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1101 & endpt_stall_set == 1'b 1 )
            begin
            endpt13_r <= {endpt13_r[4:2], 1'b 1, endpt13_r[0]};	
            end
         else if (current_endpt_r == 4'b 1101 & endpt_stall_clr == 1'b 1 )
            begin
            endpt13_r <= {endpt13_r[4:2], 1'b 0, endpt13_r[0]};	
//  endpoint 14
            end
         if (addr_i == END_CTLE_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt14_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1110 & endpt_stall_set == 1'b 1 )
            begin
            endpt14_r <= {endpt14_r[4:2], 1'b 1, endpt14_r[0]};	
            end
         else if (current_endpt_r == 4'b 1110 & endpt_stall_clr == 1'b 1 )
            begin
            endpt14_r <= {endpt14_r[4:2], 1'b 0, endpt14_r[0]};	
//  endpoint 15
            end
         if (addr_i == END_CTLF_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            endpt15_r <= t_wdata[4:0];	
            end
         else if (current_endpt_r == 4'b 1111 & endpt_stall_set == 1'b 1 )
            begin
            endpt15_r <= {endpt15_r[4:2], 1'b 1, endpt15_r[0]};	
            end
         else if (current_endpt_r == 4'b 1111 & endpt_stall_clr == 1'b 1 )
            begin
            endpt15_r <= {endpt15_r[4:2], 1'b 0, endpt15_r[0]};	
            end
         end
      end
   end
//  get rid of output signals if the endpoints are disabled in config
assign endpt4_reg = EN_EP_CTL_4_7 == 1'b 1 ? endpt4_r : 
	5'b 00000; 
assign endpt5_reg = EN_EP_CTL_4_7 == 1'b 1 ? endpt5_r : 
	5'b 00000; 
assign endpt6_reg = EN_EP_CTL_4_7 == 1'b 1 ? endpt6_r : 
	5'b 00000; 
assign endpt7_reg = EN_EP_CTL_4_7 == 1'b 1 ? endpt7_r : 
	5'b 00000; 
assign endpt8_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt8_r : 
	5'b 00000; 
assign endpt9_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt9_r : 
	5'b 00000; 
assign endpt10_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt10_r : 
	5'b 00000; 
assign endpt11_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt11_r : 
	5'b 00000; 
assign endpt12_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt12_r : 
	5'b 00000; 
assign endpt13_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt13_r : 
	5'b 00000; 
assign endpt14_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt14_r : 
	5'b 00000; 
assign endpt15_reg = EN_EP_CTL_8_15 == 1'b 1 ? endpt15_r : 
	5'b 00000; 
// -------------------------------------------------------------------------
//  The current endpoint signal is a 16:1 mux that will select the endpoint
//  control register based on the current endpoint info from the sie.
// -------------------------------------------------------------------------
assign endpt_stall = endpt_ctl[1]; 
// -------------------------------------------------------------------------
//  Interrupt Clear Logic -
//  Interrupts are cleared by writing to the interrupt status register. The
//  clear signals are one clock wide.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : int_clr_r_PROC
   if (rst_a == 1'b 1)
      begin
      stall_int_clr_r <= 1'b 0;	
      resume_clr_r <= 1'b 0;	
      sleep_clr_r <= 1'b 0;	
      tok_dne_clr_r <= 1'b 0;	
      sof_tok_clr_r <= 1'b 0;	
      error_clr_r <= 1'b 0;	
      usb_rst_clr_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         stall_int_clr_r <= 1'b 0;	
         resume_clr_r <= 1'b 0;	
         sleep_clr_r <= 1'b 0;	
         tok_dne_clr_r <= 1'b 0;	
         sof_tok_clr_r <= 1'b 0;	
         error_clr_r <= 1'b 0;	
         usb_rst_clr_r <= 1'b 0;	
         end
      else if (addr_i == INT_STAT_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         stall_int_clr_r <= t_wdata[7];	
         resume_clr_r <= t_wdata[5];	
         sleep_clr_r <= t_wdata[4];	
         tok_dne_clr_r <= t_wdata[3];	
         sof_tok_clr_r <= t_wdata[2];	
         error_clr_r <= t_wdata[1];	
         usb_rst_clr_r <= t_wdata[0];	
         end
      else
         begin
         stall_int_clr_r <= 1'b 0;	
         resume_clr_r <= 1'b 0;	
         sleep_clr_r <= 1'b 0;	
         tok_dne_clr_r <= 1'b 0;	
         sof_tok_clr_r <= 1'b 0;	
         error_clr_r <= 1'b 0;	
         usb_rst_clr_r <= 1'b 0;	
         end
      end
   end
// -------------------------------------------------------------------------
//  Error Clear Logic -
//  Errors are cleared by writing to the error status register. The clear
//  signals are one clock wide.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : err_clr_r_PROC
   if (rst_a == 1'b 1)
      begin
      bts_err_clr_r <= 1'b 0;	
      own_err_clr_r <= 1'b 0;	
      dma_err_clr_r <= 1'b 0;	
      bto_err_clr_r <= 1'b 0;	
      dfn8_err_clr_r <= 1'b 0;	
      crc16_err_clr_r <= 1'b 0;	
      crc5_err_clr_r <= 1'b 0;	
      pid_err_clr_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         bts_err_clr_r <= 1'b 0;	
         own_err_clr_r <= 1'b 0;	
         dma_err_clr_r <= 1'b 0;	
         bto_err_clr_r <= 1'b 0;	
         dfn8_err_clr_r <= 1'b 0;	
         crc16_err_clr_r <= 1'b 0;	
         crc5_err_clr_r <= 1'b 0;	
         pid_err_clr_r <= 1'b 0;	
         end
      else if (addr_i == ERR_STAT_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         bts_err_clr_r <= t_wdata[7];	
         own_err_clr_r <= t_wdata[6];	
         dma_err_clr_r <= t_wdata[5];	
         bto_err_clr_r <= t_wdata[4];	
         dfn8_err_clr_r <= t_wdata[3];	
         crc16_err_clr_r <= t_wdata[2];	
         crc5_err_clr_r <= t_wdata[1];	
         pid_err_clr_r <= t_wdata[0];	
         end
      else
         begin
         bts_err_clr_r <= 1'b 0;	
         own_err_clr_r <= 1'b 0;	
         dma_err_clr_r <= 1'b 0;	
         bto_err_clr_r <= 1'b 0;	
         dfn8_err_clr_r <= 1'b 0;	
         crc16_err_clr_r <= 1'b 0;	
         crc5_err_clr_r <= 1'b 0;	
         pid_err_clr_r <= 1'b 0;	
         end
      end
   end
// -------------------------------------------------------------------------
//  Interrupt Status Generation Logic -
//  Interrupt conditions are set from SIE inputs and cleared by
//  writing to the interrupt status register.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : intr_PROC
   if (rst_a == 1'b 1)
      begin
      stall_int_r <= 1'b 0;	//  Reset Stall
      resume_r <= 1'b 0;	//  Reset RESUME
      sleep_r <= 1'b 0;	//  Reset SLEEP
      sof_tok_r <= 1'b 0;	//  Reset SOF_TOK
      error_r <= 1'b 0;	//  Reset ERROR
      usb_rst_r <= 1'b 0;	//  Reset USB_RST
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         stall_int_r <= 1'b 0;	//  Reset Stall
         resume_r <= 1'b 0;	//  Reset RESUME
         sleep_r <= 1'b 0;	//  Reset SLEEP
         sof_tok_r <= 1'b 0;	//  Reset SOF_TOK
         error_r <= 1'b 0;	//  Reset ERROR
         usb_rst_r <= 1'b 0;	//  Reset USB_RST
         end
      else
         begin
         if (stall_int_set == 1'b 1)
            begin
            stall_int_r <= 1'b 1;	
            end
         else if (stall_int_clr_r == 1'b 1 )
            begin
            stall_int_r <= 1'b 0;	
            end
         if (resume_set == 1'b 1)
            begin
            resume_r <= 1'b 1;	
            end
//  RESUME interrupt
         else if (resume_clr_r == 1'b 1 )
            begin
            resume_r <= 1'b 0;	
            end
         if (sleep_set == 1'b 1)
            begin
            sleep_r <= 1'b 1;	
            end
//  Implements SLEEP interrupt
         else if (sleep_clr_r == 1'b 1 )
            begin
            sleep_r <= 1'b 0;	
            end
         if (sof_tok_set == 1'b 1)
            begin
            sof_tok_r <= 1'b 1;	
            end
//  SOF_TOK interrupt 
         else if (sof_tok_clr_r == 1'b 1 )
            begin
            sof_tok_r <= 1'b 0;	
            end
         if (error_set == 1'b 1)
            begin
            error_r <= 1'b 1;	
            end
//  ERROR interrupt 
         else if (error_clr_r == 1'b 1 )
            begin
            error_r <= 1'b 0;	
            end
         if (usb_rst_set == 1'b 1)
            begin
            usb_rst_r <= 1'b 1;	
            end
//  USB_RST interrupt 
         else if (usb_rst_clr_r == 1'b 1 )
            begin
            usb_rst_r <= 1'b 0;	
            end
         end
      end
   end
// ----------------------------------------------------------------------------------------------------------
//  otg register implementation
// ----------------------------------------------------------------------------------------------------------
//  interrupt enable register
always @(posedge clk or posedge rst_a)
   begin : otg_ictrl_r_PROC
   if (rst_a == 1'b 1)
      begin
      otg_ictrl_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         otg_ictrl_r <= {8{1'b 0}};	
         end
      else if (hc_en == 1'b 1 & addr_i == OTG_ICTRL_ADD & 
	t_cmd == CMD_WR & t_cmdval == 1'b 1 & 
	t_be[0] == 1'b 1 )
         begin
         otg_ictrl_r <= t_wdata[7:0];	
         end
      end
   end
//  unbundle the interrupt control
assign usb_id_int_en = hc_en & otg_ictrl_r[7]; 
assign usb_1msec_int_en = hc_en & otg_ictrl_r[6]; 
assign usb_linestate_int_en = hc_en & otg_ictrl_r[5]; 
assign usb_sess_vld_int_en = hc_en & otg_ictrl_r[3]; 
assign usb_b_sess_end_int_en = hc_en & otg_ictrl_r[2]; 
assign usb_a_vbus_vld_int_en = hc_en & otg_ictrl_r[0]; 
//  control register
always @(posedge clk or posedge rst_a)
   begin : otg_ctrl_r_PROC
   if (rst_a == 1'b 1)
      begin
      otg_ctrl_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         otg_ctrl_r[7] <= 1'b 0;	
         otg_ctrl_r[6] <= 1'b 0;	
         otg_ctrl_r[5:0] <= {6{1'b 0}};	
         end
      else
         begin
         if (addr_i == OTG_CTRL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            otg_ctrl_r[7] <= t_wdata[7];	
            end
         if (addr_i == OTG_CTRL_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1)
            begin
            otg_ctrl_r[6] <= t_wdata[6];	
            end
         if (hc_en == 1'b 1 & addr_i == OTG_CTRL_ADD & 
	t_cmd == CMD_WR & t_cmdval == 1'b 1 & 
	t_be[0] == 1'b 1)
            begin
            otg_ctrl_r[5:0] <= t_wdata[5:0];	
            end
         end
      end
   end
//  unbundle the control signals these bits are used for device mode as well as
//  host(OTG) in device mode the pull up resistor is controlled by the usb_en
//  bit in the control register.  If bit-2 of the OTG_CTL register is set then the pull
//  up and pull down resistors are controlled by the OTG_CTL register.
assign lsdev = LOW_SPEED_DEV == 1 ? 1'b 1 : 
	1'b 0; 
assign usb_dp_high = usb_en_int & ~otg_ctrl_r[2] & ~lsdev | otg_ctrl_r[7] & 
	otg_ctrl_r[2]; 
assign usb_dm_high = usb_en_int & ~otg_ctrl_r[2] & lsdev | otg_ctrl_r[6] & 
	otg_ctrl_r[2]; 
//  these are just used for host(OTG)
assign usb_dp_low_n = ~(host_mode_int & ~otg_ctrl_r[2] | otg_ctrl_r[5] & otg_ctrl_r[2]); 
assign usb_dm_low_n = ~(host_mode_int & ~otg_ctrl_r[2] | otg_ctrl_r[4] & otg_ctrl_r[2]); 
assign usb_vbus_on = otg_ctrl_r[3]; 
//  bit 2 is the 
assign usb_vbus_chg = otg_ctrl_r[1]; 
assign usb_vbus_dschg = otg_ctrl_r[0]; 
//  assembly the usb status register
assign otg_stat = {hc_usb_id_deb, hc_usb_1msec, hc_otg_stable_linestate, 1'b 0, 
	hc_usb_sess_vld_deb, hc_usb_b_sess_end_deb, 1'b 0, hc_usb_a_vbus_vld_deb} & 
	hc_en_byte; 
// -------------------------------------------------------------------------
//  OTG Interrupt Logic -
//  Interrupts are cleared by writing to the OTG interrupt status register. 
// -------------------------------------------------------------------------
//  clear signals
always @(posedge clk or posedge rst_a)
   begin : otg_int_clr_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_id_int_clr_r <= 1'b 0;	
      usb_1msec_int_clr_r <= 1'b 0;	
      usb_linestate_int_clr_r <= 1'b 0;	
      usb_b_sess_end_int_clr_r <= 1'b 0;	
      usb_sess_vld_int_clr_r <= 1'b 0;	
      usb_a_vbus_vld_int_clr_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_id_int_clr_r <= 1'b 0;	
         usb_1msec_int_clr_r <= 1'b 0;	
         usb_linestate_int_clr_r <= 1'b 0;	
         usb_b_sess_end_int_clr_r <= 1'b 0;	
         usb_sess_vld_int_clr_r <= 1'b 0;	
         usb_a_vbus_vld_int_clr_r <= 1'b 0;	
         end
      else if (hc_en == 1'b 1 & addr_i == OTG_ISTAT_ADD & 
	t_cmd == CMD_WR & t_cmdval == 1'b 1 & 
	t_be[0] == 1'b 1 )
         begin
         usb_id_int_clr_r <= t_wdata[7];	
         usb_1msec_int_clr_r <= t_wdata[6];	
         usb_linestate_int_clr_r <= t_wdata[5];	
         usb_sess_vld_int_clr_r <= t_wdata[3];	
         usb_b_sess_end_int_clr_r <= t_wdata[2];	
         usb_a_vbus_vld_int_clr_r <= t_wdata[0];	
         end
      else
         begin
         usb_id_int_clr_r <= 1'b 0;	
         usb_1msec_int_clr_r <= 1'b 0;	
         usb_linestate_int_clr_r <= 1'b 0;	
         usb_sess_vld_int_clr_r <= 1'b 0;	
         usb_b_sess_end_int_clr_r <= 1'b 0;	
         usb_a_vbus_vld_int_clr_r <= 1'b 0;	
         end
      end
   end

assign hc_usb_id_int_clr = hc_en & usb_id_int_clr_r; 
assign hc_usb_1msec_int_clr = hc_en & usb_1msec_int_clr_r; 
assign hc_usb_linestate_int_clr = hc_en & usb_linestate_int_clr_r; 
assign hc_usb_sess_vld_int_clr = hc_en & usb_sess_vld_int_clr_r; 
assign hc_usb_b_sess_end_int_clr = hc_en & usb_b_sess_end_int_clr_r; 
assign hc_usb_a_vbus_vld_int_clr = hc_en & usb_a_vbus_vld_int_clr_r; 
//  interrupt registers
always @(posedge clk or posedge rst_a)
   begin : otg_int_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_id_int_r <= 1'b 0;	
      usb_1msec_int_r <= 1'b 0;	
      usb_linestate_int_r <= 1'b 0;	
      usb_b_sess_end_int_r <= 1'b 0;	
      usb_sess_vld_int_r <= 1'b 0;	
      usb_a_vbus_vld_int_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_id_int_r <= 1'b 0;	
         usb_1msec_int_r <= 1'b 0;	
         usb_linestate_int_r <= 1'b 0;	
         usb_b_sess_end_int_r <= 1'b 0;	
         usb_sess_vld_int_r <= 1'b 0;	
         usb_a_vbus_vld_int_r <= 1'b 0;	
         end
      else
         begin
         if (hc_usb_id_int_clr == 1'b 1)
            begin
            usb_id_int_r <= 1'b 0;	
            end
         else if ((hc_en & usb_1msec_r & hc_otg_stable_id) == 1'b 1 & 
	hc_usb_id_deb != hc_usb_id_last )
            begin
            usb_id_int_r <= 1'b 1;	
            end
         if (hc_usb_1msec_int_clr == 1'b 1)
            begin
            usb_1msec_int_r <= 1'b 0;	
            end
         else if (hc_en == 1'b 1 & usb_1msec_r == 1'b 1 )
            begin
            usb_1msec_int_r <= 1'b 1;	
            end
         if (hc_usb_linestate_int_clr == 1'b 1)
            begin
            usb_linestate_int_r <= 1'b 0;	
            end
         else if ((hc_en & usb_1msec_r) == 1'b 1 & (hc_otg_stable_se0 == 
	1'b 1 & hc_usb_se0_last != hc_usb_se0_deb | hc_otg_stable_se0 == 
	1'b 1 & hc_otg_stable_jstate == 1'b 1 & (hc_usb_jstate_last != 
	hc_usb_jstate_deb & hc_usb_se0_last == 1'b 0)) )
            begin
            usb_linestate_int_r <= 1'b 1;	//  then interrupt
            end
//  when SE0 is false
         if (hc_usb_b_sess_end_int_clr == 1'b 1)
            begin
            usb_b_sess_end_int_r <= 1'b 0;	
            end
         else if ((hc_en & usb_1msec_r & hc_otg_stable_b_sess_end) == 1'b 1 & 
	hc_usb_b_sess_end_deb != hc_usb_b_sess_end_last )
            begin
            usb_b_sess_end_int_r <= 1'b 1;	
            end
         if (hc_usb_sess_vld_int_clr == 1'b 1)
            begin
            usb_sess_vld_int_r <= 1'b 0;	
            end
         else if ((hc_en & usb_1msec_r & hc_otg_stable_sess_vld) == 1'b 1 & 
	hc_usb_sess_vld_deb != hc_usb_sess_vld_last )
            begin
            usb_sess_vld_int_r <= 1'b 1;	
            end
         if (hc_usb_a_vbus_vld_int_clr == 1'b 1)
            begin
            usb_a_vbus_vld_int_r <= 1'b 0;	
            end
         else if ((hc_en & usb_1msec_r & hc_otg_stable_a_vbus_vld) == 1'b 1 & 
	hc_usb_a_vbus_vld_deb != hc_usb_a_vbus_vld_last )
            begin
            usb_a_vbus_vld_int_r <= 1'b 1;	
            end
         end
      end
   end

assign otg_istat = {usb_id_int_r, usb_1msec_int_r, usb_linestate_int_r, 1'b 0, 
	usb_sess_vld_int_r, usb_b_sess_end_int_r, 1'b 0, usb_a_vbus_vld_int_r} & 
	hc_en_byte; 
//  otg interrupt
assign otg_int = hc_en & (usb_id_int_r & usb_id_int_en | usb_1msec_int_r & 
	usb_1msec_int_en | usb_linestate_int_r & usb_linestate_int_en | usb_b_sess_end_int_r & 
	usb_b_sess_end_int_en | usb_sess_vld_int_r & usb_sess_vld_int_en | usb_a_vbus_vld_int_r & 
	usb_a_vbus_vld_int_en); 
// -------------------------------------------------------------------------
//  token done state machine -
//  keep track of tokens and keep the interrupt set, looking at the fifo
//  empty and latched token sets from sie.        
// -------------------------------------------------------------------------
always @(tok_dne_state_r or bvci_state_r or tok_dne_set or tok_dne_r or tok_dne_clr_r
 or i_cmdack or stat_empty)
   begin : tok_dne_state_nxt_PROC
   tok_dne_state_nxt <= tok_dne_state_r;	
   tok_dne_nxt <= tok_dne_r;	
   case (tok_dne_state_r)
   tok_dne_states_TOK_DNE_IDLE:
      begin
      if (tok_dne_set == 1'b 1)
         begin
         tok_dne_state_nxt <= tok_dne_states_TOK_DNE_PEND;	
         end
      end
   tok_dne_states_TOK_DNE_PEND:
      begin
      if (bvci_state_r == bvci_states_BVCI_WR_BDT_ACK & i_cmdack == 1'b 1)
         begin
         tok_dne_nxt <= 1'b 1;	
         tok_dne_state_nxt <= tok_dne_states_TOK_DNE_WAIT;	
         end
      end
//  finished writing the bdt
   tok_dne_states_TOK_DNE_WAIT:
      begin
      if (tok_dne_clr_r == 1'b 1)
         begin
         tok_dne_nxt <= 1'b 0;	
         tok_dne_state_nxt <= tok_dne_states_TOK_DNE_FIFO;	
         end
      end
//  wait for FIFO to update empty
   tok_dne_states_TOK_DNE_FIFO:
      begin
      if (stat_empty == 1'b 0)
         begin
         tok_dne_nxt <= 1'b 1;	
         tok_dne_state_nxt <= tok_dne_states_TOK_DNE_WAIT;	
         end
      else
         begin
         tok_dne_state_nxt <= tok_dne_states_TOK_DNE_IDLE;	
         end
      end
//  look at the status fifo empty flag if
//  it's not empty, we have more tokens to
//  process
   default:
      begin
      tok_dne_nxt <= 1'b 0;	
      tok_dne_state_nxt <= tok_dne_states_TOK_DNE_IDLE;	
      end
   endcase
   end
//  sync part of state machine
//  set outputs to default states
always @(posedge clk or posedge rst_a)
   begin : tok_dne_state_r_PROC
   if (rst_a == 1'b 1)
      begin
      tok_dne_r <= 1'b 0;	
      tok_dne_state_r <= tok_dne_states_TOK_DNE_IDLE;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         tok_dne_r <= 1'b 0;	
         tok_dne_state_r <= tok_dne_states_TOK_DNE_IDLE;	
         end
      else
         begin
         tok_dne_r <= tok_dne_nxt;	
         tok_dne_state_r <= tok_dne_state_nxt;	
         end
      end
   end
// -------------------------------------------------------------------------
//  Error Status Generation Logic -
//  Error conditions are set from sie inputs and cleared by
//  writing to the error status register.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : error_r_PROC
   if (rst_a == 1'b 1)
      begin
      bts_err_r <= 1'b 0;	
      own_err_r <= 1'b 0;	
      dma_err_r <= 1'b 0;	
      bto_err_r <= 1'b 0;	
      dfn8_err_r <= 1'b 0;	
      crc16_err_r <= 1'b 0;	
      crc5_err_r <= 1'b 0;	
      pid_err_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         bts_err_r <= 1'b 0;	
         own_err_r <= 1'b 0;	
         dma_err_r <= 1'b 0;	
         bto_err_r <= 1'b 0;	
         dfn8_err_r <= 1'b 0;	
         crc16_err_r <= 1'b 0;	
         crc5_err_r <= 1'b 0;	
         pid_err_r <= 1'b 0;	
         end
      else
         begin
         if (bts_err_set == 1'b 1)
            begin
            bts_err_r <= 1'b 1;	
            end
//  bts error
         else if (bts_err_clr_r == 1'b 1 )
            begin
            bts_err_r <= 1'b 0;	
            end
         if (own_err_set == 1'b 1)
            begin
            own_err_r <= 1'b 1;	
            end
//  own error
         else if (own_err_clr_r == 1'b 1 )
            begin
            own_err_r <= 1'b 0;	
            end
         if (dma_err_set == 1'b 1 | dma_overrun == 1'b 1)
            begin
            dma_err_r <= 1'b 1;	
            end
//  DMA timeout error 
         else if (dma_err_clr_r == 1'b 1 )
            begin
            dma_err_r <= 1'b 0;	
            end
         if (bto_err_set == 1'b 1)
            begin
            bto_err_r <= 1'b 1;	
            end
//  Bus timeout error
         else if (bto_err_clr_r == 1'b 1 )
            begin
            bto_err_r <= 1'b 0;	
            end
         if (dfn8_err_set == 1'b 1)
            begin
            dfn8_err_r <= 1'b 1;	
            end
//  Data Field not 8-bits error  
         else if (dfn8_err_clr_r == 1'b 1 )
            begin
            dfn8_err_r <= 1'b 0;	
            end
         if (crc16_err_set == 1'b 1)
            begin
            crc16_err_r <= 1'b 1;	
            end
//  CRC16 error 
         else if (crc16_err_clr_r == 1'b 1 )
            begin
            crc16_err_r <= 1'b 0;	
            end
         if (crc5_err_set == 1'b 1)
            begin
            crc5_err_r <= 1'b 1;	
            end
//  CRC5 error
         else if (crc5_err_clr_r == 1'b 1 )
            begin
            crc5_err_r <= 1'b 0;	
            end
         if (pid_err_set == 1'b 1)
            begin
            pid_err_r <= 1'b 1;	
            end
//  PID error
         else if (pid_err_clr_r == 1'b 1 )
            begin
            pid_err_r <= 1'b 0;	
            end
         end
      end
   end
//  assembly the interrupt and status registers
assign int_stat_rg = {stall_int_r, hc_attach, resume_r, sleep_r, 
	tok_dne_r, sof_tok_r, error_r, usb_rst_r}; 
assign err_stat_rg = {bts_err_r, own_err_r, dma_err_r, bto_err_r, 
	dfn8_err_r, crc16_err_r, crc5_err_r, pid_err_r}; 
//  generate error interrupt on any enabled errors
assign error_set = (err_stat_rg & err_enb_r) != 8'b 00000000 ? 1'b 1 : 
	1'b 0; 
// -------------------------------------------------------------------------
//  Interrupt output
//  This signal is active (high) whenever a bit in the int_stat_rg is set and
//  the corresponding enable bit in the int_enb_r is set.
// -------------------------------------------------------------------------
assign vusb_irq = int_stat_rg[7] & int_enb_r[7] | int_stat_rg[6] & int_enb_r[6] | 
	int_stat_rg[5] & int_enb_r[5] | int_stat_rg[4] & int_enb_r[4] | 
	int_stat_rg[3] & int_enb_r[3] | int_stat_rg[2] & int_enb_r[2] | 
	int_stat_rg[1] & int_enb_r[1] | int_stat_rg[0] & int_enb_r[0] | 
	otg_int; 
// -------------------------------------------------------------------------
//  assemble the control register
// -------------------------------------------------------------------------
assign ctl_rg_out = {rcv, se0, txdsuspend_tokbusy_r, ctl_r}; 
//  assign control register bits to meaningful names
assign hc_rst_req = ctl_r[4]; 
assign host_mode_int = ctl_r[3]; //  internal version of host_mode_en.
assign resume_req = ctl_r[2]; 
assign odd_rst = ctl_r[1]; 
assign usb_en_int = ctl_r[0]; 
// -------------------------------------------------------------------------
//  Host Logic  -
//  This should disappear if the host IMPLEMENT_EMBEDDED_HOST bit
//  is not set. Some of this looks bizarre but was implemented this way so
//  this logic would disappear if it's only a device.
// -------------------------------------------------------------------------
//  enables
assign hc_en = IMPLEMENT_EMBEDED_HOST; // and host_mode_int;  -- host enable
assign hc_en_byte = hc_en == 1'b 1 ? 8'b 11111111 : 
	8'b 00000000; 
assign host_mode_en = host_mode_int; 
// -------------------------------------------------------------------------
//  host register bits
// -------------------------------------------------------------------------
//  when the processor writes bit 4 of the token register, generate the
//  token load signal
always @(posedge clk or posedge rst_a)
   begin : hc_token_ld_r_PROC
   if (rst_a == 1'b 1)
      begin
      hc_token_ld_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_token_ld_r <= 1'b 0;	
         end
      else if (addr_i == HST_TOKN_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_wdata[4] == 1'b 1 )
         begin
         hc_token_ld_r <= 1'b 1;	
         end
      else
         begin
         hc_token_ld_r <= 1'b 0;	
         end
      end
   end
//  the sie will generate a attach_set signal to indicate a device is
//  attached.This signal is read in the interrupt status register. The
//  processor clears this signal by writting bit 6 of the interrupt status
//  reg.  
always @(posedge clk or posedge rst_a)
   begin : hc_attach_r_PROC
   if (rst_a == 1'b 1)
      begin
      hc_attach_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_attach_r <= 1'b 0;	
         end
      else if (hc_attach_set == 1'b 1 & hc_en == 1'b 1 )
         begin
         hc_attach_r <= 1'b 1;	
         end
      else if (addr_i == INT_STAT_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_wdata[6] == 1'b 1 )
         begin
         hc_attach_r <= 1'b 0;	
         end
      end
   end

assign hc_attach = hc_attach_r & hc_en; 
always @(posedge clk or posedge rst_a)
   begin : host_endpt0_r_PROC
   if (rst_a == 1'b 1)
      begin
      host_wo_hub_r <= 1'b 0;	
      hc_retry_disable_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         host_wo_hub_r <= 1'b 0;	
         hc_retry_disable_r <= 1'b 0;	
         end
      else if (addr_i == END_CTL0_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         host_wo_hub_r <= t_wdata[7];	
         hc_retry_disable_r <= t_wdata[6];	
         end
      end
   end

assign host_wo_hub_int = host_wo_hub_r & hc_en; 
assign host_wo_hub = host_wo_hub_int; 
assign hc_retry_disable = hc_retry_disable_r & hc_en; 
//  host token register writting to this register loads the token pid and
//  endpoint information
always @(posedge clk or posedge rst_a)
   begin : host_token_r_PROC
   if (rst_a == 1'b 1)
      begin
      hc_token_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_token_r <= {8{1'b 0}};	
         end
      else if (addr_i == HST_TOKN_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         hc_token_r <= t_wdata[7:0];	
         end
      end
   end

assign hc_token_rg = hc_token_r & hc_en_byte; 
//  pick off the register bits for pid and endpoint
assign hc_token_pid = hc_token_rg[7:4]; 
assign hc_token_endpt = hc_token_rg[3:0]; 
//  host SOF threshold register - loads counter with size of transfers so
//  that sie won't start a token if the sof needs to fire within that time.
always @(posedge clk or posedge rst_a)
   begin : host_sof_PROC
   if (rst_a == 1'b 1)
      begin
      hc_sof_thld_r <= {8{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         hc_sof_thld_r <= {8{1'b 0}};	
         end
      else if (addr_i == SOF_THLD_ADD & t_cmd == CMD_WR & 
	t_cmdval == 1'b 1 & t_be[0] == 1'b 1 )
         begin
         hc_sof_thld_r <= t_wdata[7:0];	
         end
      end
   end

assign hc_sof_thld_rg = hc_sof_thld_r & hc_en_byte; 
// -------------------------------------------------------------------------
//  status fifo and logic -
//  when a token done interrupt is set, write the status bits in the fifo
//  unless the fifo is full, the status will be available on the data output
//  pins of the fifo which the processor can read by accessing the status
//  register. When the processor clears the token done interrupt, a read
//  fifo signal is generated which causes the fifo to output the next status
//  if one is present.
// -------------------------------------------------------------------------
//  Status fifo write data
assign stat_wdata = {current_endpt_r, txd_token_r, odd_bdt_r, 2'b 00}; 
//  Status FIFO read enable
assign stat_re = tok_dne_clr_r; 
//  Status FIFO write enable register this to break timing loop
always @(posedge clk or posedge rst_a)
   begin : stat_we_PROC
   if (rst_a == 1'b 1)
      begin
      stat_we <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         stat_we <= 1'b 0;	
         end
      else
         begin
         stat_we <= tok_dne_set & ~stat_full;	
         end
      end
   end
// -------------------------------------------------------------------------
//  dma read & write enable logic -
// 
//  capture dma request signals from sie, keep track if a write request has
//  been issued but hasn't completed. If that is the case ignore the read
//  request and let the sie bus time out that packet.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : dma_en_PROC
   if (rst_a == 1'b 1)
      begin
      dma_rd_en_r <= 1'b 0;	//  read from memory write to tx_fifo
      dma_wrt_en_r <= 1'b 0;	//  write to memory read rx_fifo
      dma_rd_bdt_r <= 1'b 0;	//  read bdt from memory
      dma_wrt_bdt_lat_r <= 1'b 0;	//  write bdt latched
      dma_wrt_bdt_r <= 1'b 0;	//  now write the bdt
      end_cycle_r <= 1'b 0;	//  write bdt hasn't finished
      bdt_valid_r <= 1'b 0;	//  the bdt is valid
      rx_fifo_flush_r <= 1'b 0;	
      bdt_wrt_pid_r <= 4'b 0000;	//  update the pid
      current_endpt_r <= 4'b 0000;	//  current endpoint
      txd_token_r <= 1'b 0;	//  update the txd token
      odd_bdt_r <= 1'b 0;	//  update the odd bdt bit
      out_data01_pid_r <= 1'b 0;	//  out data
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         dma_rd_en_r <= 1'b 0;	
         dma_wrt_en_r <= 1'b 0;	
         dma_rd_bdt_r <= 1'b 0;	
         dma_wrt_bdt_lat_r <= 1'b 0;	
         dma_wrt_bdt_r <= 1'b 0;	
         end_cycle_r <= 1'b 0;	
         bdt_valid_r <= 1'b 0;	
         rx_fifo_flush_r <= 1'b 0;	
         bdt_wrt_pid_r <= 4'b 0000;	
         current_endpt_r <= 4'b 0000;	
         txd_token_r <= 1'b 0;	
         odd_bdt_r <= 1'b 0;	
         out_data01_pid_r <= 1'b 0;	
//  clear the read enable after we write the bdt or
//  we read the bdt and we don't own it or it's stalled or
//  the byte count expires.
         end
      else
         begin
         if (wrt_bdt_clr_r == 1'b 1 | flush == 1'b 1 | 
	bdt_ld == 1'b 1 & (bdt_rg0_r[7] == 1'b 0 | 
	endpt_stall == 1'b 1 | bdt_rg0_r[2] == 1'b 1) | 
	tx_fifo_state_r == txfifo_states_TXFIFO_WRT & byte_count_eq == 1'b 1)
            begin
            dma_rd_en_r <= 1'b 0;	
//  dma read enable set when we request the BDT read for a tx data packet.
            end
         else if (txd_token == 1'b 1 & dma_rd_bdt_r == 1'b 1 & 
	end_cycle_r == 1'b 0 )
            begin
            dma_rd_en_r <= 1'b 1;	
//  DMA write enable set when we request the BDT read for a rx data packet.
//  remains set until the BDT is written back to memory, or the BDT read and
//  own = 0 or stalled.
            end
         if (wrt_bdt_clr_r == 1'b 1 | flush == 1'b 1 | 
	bdt_ld == 1'b 1 & (bdt_rg0_r[7] == 1'b 0 | 
	endpt_stall == 1'b 1 | bdt_rg0_r[2] == 1'b 1))
            begin
            dma_wrt_en_r <= 1'b 0;	
            end
         else if (txd_token == 1'b 0 & dma_rd_bdt_r == 1'b 1 & 
	end_cycle_r == 1'b 0 )
            begin
            dma_wrt_en_r <= 1'b 1;	
//  latch the sie request to read the bdt if the previous write bdt is
//  finished 
            end
         if (rd_bdt_clr_r == 1'b 1)
            begin
            dma_rd_bdt_r <= 1'b 0;	
            end
         else if (sie_dma_req[2] == 1'b 1 & end_cycle_r == 1'b 0 )
            begin
            dma_rd_bdt_r <= 1'b 1;	
//  when sie requests to write the bdt, the transfer is over but if 
//  keep is set we don't bother writing the bdt
            end
         if (wrt_bdt_clr_r == 1'b 1)
            begin
            dma_wrt_bdt_lat_r <= 1'b 0;	
            end
         else if (sie_dma_req[3] == 1'b 1 & keep == 1'b 0 )
            begin
            dma_wrt_bdt_lat_r <= 1'b 1;	
//  request a bdt write
//  for in tokens just do it
//  for out tokens wait til the rx_fifo has been
//  flushed and written to memory
            end
         if (wrt_bdt_clr_r == 1'b 1)
            begin
            dma_wrt_bdt_r <= 1'b 0;	
            end
         else if (dma_wrt_bdt_lat_r == 1'b 1 & txd_token_r == 1'b 1 )
            begin
            dma_wrt_bdt_r <= 1'b 1;	
            end
         else if (dma_wrt_bdt_lat_r == 1'b 1 & rx_empty == 1'b 1 & 
	rx_fifo_state_r == rxfifo_states_RXFIFO_IDLE )
            begin
            dma_wrt_bdt_r <= 1'b 1;	
//  create a signal that tells me that a wrt bdt cycle has started use
//  this to prevent a read bdt from happening until this finished
            end
         if (wrt_bdt_clr_r == 1'b 1)
            begin
            end_cycle_r <= 1'b 0;	
            end
         else if (sie_dma_req[3] == 1'b 1 )
            begin
            end_cycle_r <= 1'b 1;	
//  set bdt valid when the bdt is read clear it on the next request
            end
         if (bdt_ld == 1'b 1)
            begin
            bdt_valid_r <= 1'b 1;	
            end
         else if (dma_rd_bdt_r == 1'b 1 | dma_wrt_bdt_r == 1'b 1 )
            begin
            bdt_valid_r <= 1'b 0;	
//  if the sie requests a write bdt and the rx_fifo_state machine
//  isn't idle, then flush the temp reg
            end
         if (sie_dma_req[3] == 1'b 1 & ~(rx_fifo_state_r == rxfifo_states_RXFIFO_IDLE))
            begin
            rx_fifo_flush_r <= 1'b 1;	
            end
         else if (dma_req_clr_r == 1'b 1 & rx_empty == 1'b 1 )
            begin
            rx_fifo_flush_r <= 1'b 0;	
//  grab the pid at bdt write request
            end
         if (sie_dma_req[3] == 1'b 1)
            begin
            bdt_wrt_pid_r <= bdt_wrt_pid;	
//  update the txd token and odd bits when the sie requests a new bdt
//  but make sure we're finished writing the last bdt
            end
         if (sie_dma_req[2] == 1'b 1 & end_cycle_r == 1'b 0)
            begin
            current_endpt_r <= current_endpt;	
            end
         if (sie_dma_req[2] == 1'b 1 & end_cycle_r == 1'b 0)
            begin
            txd_token_r <= txd_token;	
            end
         if (sie_dma_req[2] == 1'b 1 & end_cycle_r == 1'b 0)
            begin
            odd_bdt_r <= odd_bdt;	
//  update this signal when we get a bdt write request; it's not
//  valid when the bdt read comes along
            end
         if (sie_dma_req[3] == 1'b 1)
            begin
            out_data01_pid_r <= out_data01_pid;	
            end
         end
      end
   end
// -------------------------------------------------------------------------
//  dma counters - byte counter -  transfer counter - dma address -
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : byte_cnt_PROC
   if (rst_a == 1'b 1)
      begin
      byte_cntr_r <= {10{1'b 0}};	
      txfr_cntr_r <= {3{1'b 0}};	
      dma_addr_r <= {32{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         byte_cntr_r <= {10{1'b 0}};	
         txfr_cntr_r <= {3{1'b 0}};	
         dma_addr_r <= {32{1'b 0}};	
//  the byte counter counts the number of bytes transferred for a
//  packet, it gets cleared when the bdt is loaded and is allowed to
//  count for the number of bytes dma'd
         end
      else
         begin
         if (bdt_ld == 1'b 1)
            begin
            byte_cntr_r <= {10{1'b 0}};	
            end
         else if (byte_cnt_inc == 1'b 1 )
            begin
            byte_cntr_r <= byte_cntr_r + 1'b 1;	
//  the transfer counter is loaded with either the byte enable value
//  for receiving data or the least significant bits of the dma
//  address. While the txfr_cntr_r is not equal to zero the dma
//  address counts. Also if we get a byte_count_equal then terminate
//  the counters
            end
         if (dma_req_clr_r == 1'b 1 & txd_token_r == 1'b 0)
            begin
            case (i_be_r)
            4'b 1111:
               begin
               txfr_cntr_r <= 3'b 100;	//  loads 4
               end
            4'b 1110:
               begin
               txfr_cntr_r <= 3'b 011;	//  loads 3
               end
            4'b 0111:
               begin
               txfr_cntr_r <= 3'b 011;	//  loads 3
               end
            4'b 1100:
               begin
               txfr_cntr_r <= 3'b 010;	//  loads 2
               end
            4'b 0011:
               begin
               txfr_cntr_r <= 3'b 010;	//  loads 2
               end
            default:
               begin
               txfr_cntr_r <= 3'b 001;	//  loads 1
               end
            endcase
            end
         else if (dma_req_clr_r == 1'b 1 & txd_token_r == 1'b 1 )
            begin
            case (dma_addr_r[1:0])
            2'b 00:
               begin
               txfr_cntr_r <= 3'b 100;	//  loads 4
               end
            2'b 01:
               begin
               txfr_cntr_r <= 3'b 011;	//  loads 3
               end
            2'b 10:
               begin
               txfr_cntr_r <= 3'b 010;	//  loads 2
               end
            default:
               begin
               txfr_cntr_r <= 3'b 001;	//  loads 1
               end
            endcase
            end
         else if (txfr_cntr_r == 3'b 000 | byte_count_eq == 1'b 1 )
            begin
            txfr_cntr_r <= 3'b 000;	
            end
         else if (byte_cnt_inc == 1'b 1 )
            begin
            txfr_cntr_r <= txfr_cntr_r - 1'b 1;	
//  the dma address is loaded from the data bus during a bdt read,
//  it is allowed to increment by the number of bytes that were dma'd.
            end
         if (bdt_ld == 1'b 1)
            begin
            dma_addr_r <= i_rdata;	
            end
         else if (byte_cnt_inc == 1'b 1 & ninc == 1'b 0 )
            begin
            dma_addr_r <= dma_addr_r + 1'b 1;	
            end
         end
      end
   end
//  decode some outputs from the counters
//  this one allows the counters to increment
assign byte_cnt_inc = txfr_cntr_r != 3'b 000 & byte_count_eq == 1'b 0 & 
	tx_full == 1'b 0 ? 1'b 1 : 
	1'b 0; 
//  DMA byte count equals saved byte count indicating that we have read/written
//  all data from/to memory.
assign byte_count_eq = byte_cnt_r == byte_cntr_r ? 1'b 1 : 
	1'b 0; 
//  DMA buffer overrun Note the data is not written to memory, bufffer is not overrun,
//  but rather the end of the packet is dropped because there was
//  insufficient buffer space allocated.
assign dma_overrun = byte_cnt_inc & byte_count_eq; 
// -------------------------------------------------------------------------
//  tx fifo state machine -
//  This state machine will wait for the dma_rd_en to be set and the own bit
//  from a new bdt load and then start moving data from memory into the tx
//  fifo. The transfer will end when the byte counter expires or when the
//  read enable goes away.
// -------------------------------------------------------------------------
always @(tx_fifo_state_r or dma_addr_r or dma_req_clr_r or tx_full or tx_we_r
 or tx_fifo_cntr or dma_rd_data_r or tx_wdata_r or own or dma_rd_en_r
 or endpt_stall or byte_count_eq or tx_tdata_r)
   begin : tx_fifo_state_nxt_PROC
   tx_fifo_state_nxt <= tx_fifo_state_r;	
   tx_fifo_cntr_nxt <= tx_fifo_cntr;	
   tx_wdata_nxt <= tx_wdata_r;	
   tx_we_nxt <= tx_we_r;	
   dma_rd_data_nxt <= dma_rd_data_r;	
   case (tx_fifo_state_r)
   txfifo_states_TXFIFO_IDLE:
      begin
      if (dma_rd_en_r == 1'b 1 & own == 1'b 1 & 
	endpt_stall == 1'b 0 & byte_count_eq == 1'b 0 & 
	tx_full == 1'b 0)
         begin
         dma_rd_data_nxt <= 1'b 1;	
         tx_fifo_cntr_nxt <= ~dma_addr_r[1:0];	//  save byte cnt
         tx_fifo_state_nxt <= txfifo_states_TXFIFO_WAIT;	
         end
      end
   txfifo_states_TXFIFO_WAIT:
      begin
      if (dma_req_clr_r == 1'b 1)
         begin
         dma_rd_data_nxt <= 1'b 0;	
         tx_fifo_state_nxt <= txfifo_states_TXFIFO_WRT;	
         end
      end
//  wait for dma to finish moving data
//  into the temp register
   txfifo_states_TXFIFO_WRT:
      begin
      if (byte_count_eq == 1'b 0 & tx_full == 1'b 0)
         begin
         tx_we_nxt <= 1'b 1;	
         tx_fifo_cntr_nxt <= tx_fifo_cntr - 1'b 1;	
//  # of bytes dma transfered
         case (tx_fifo_cntr)
         2'b 11:
            begin
            tx_wdata_nxt <= tx_tdata_r[7:0];	
            end
         2'b 10:
            begin
            tx_wdata_nxt <= tx_tdata_r[15:8];	
            end
         2'b 01:
            begin
            tx_wdata_nxt <= tx_tdata_r[23:16];	
            end
         default:
            begin
            tx_wdata_nxt <= tx_tdata_r[31:24];	
            tx_fifo_state_nxt <= txfifo_states_TXFIFO_DONE;	
            end
         endcase
         end
      else if (byte_count_eq == 1'b 0 & tx_full == 1'b 1 )
         begin
         tx_we_nxt <= 1'b 0;	
         end
      else if (byte_count_eq == 1'b 1 )
         begin
         tx_we_nxt <= 1'b 0;	
         tx_fifo_state_nxt <= txfifo_states_TXFIFO_DONE;	
         end
      end
//  now write the data into the fifo
   txfifo_states_TXFIFO_DONE:
      begin
      tx_we_nxt <= 1'b 0;	
      tx_fifo_state_nxt <= txfifo_states_TXFIFO_IDLE;	
      end
//  take away the write after we finished
   default:
      begin
      tx_fifo_state_nxt <= txfifo_states_TXFIFO_IDLE;	
      tx_fifo_cntr_nxt <= 2'b 00;	
      tx_wdata_nxt <= {8{1'b 0}};	
      tx_we_nxt <= 1'b 0;	
      dma_rd_data_nxt <= 1'b 0;	
      end
   endcase
   end
//  sync part of state machine
//  set outputs to default states
always @(posedge clk or posedge rst_a)
   begin : tx_fifo_state_r_PROC
   if (rst_a == 1'b 1)
      begin
      tx_fifo_state_r <= txfifo_states_TXFIFO_IDLE;	
      tx_fifo_cntr <= 2'b 00;	
      dma_rd_data_r <= 1'b 0;	
      tx_wdata_r <= {8{1'b 0}};	
      tx_we_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         tx_fifo_state_r <= txfifo_states_TXFIFO_IDLE;	
         tx_fifo_cntr <= 2'b 00;	
         dma_rd_data_r <= 1'b 0;	
         tx_wdata_r <= {8{1'b 0}};	
         tx_we_r <= 1'b 0;	
         end
      else
         begin
         if (flush == 1'b 1)
            begin
            tx_fifo_state_r <= txfifo_states_TXFIFO_IDLE;	
            tx_fifo_cntr <= 2'b 00;	
            dma_rd_data_r <= 1'b 0;	
            tx_wdata_r <= {8{1'b 0}};	
            tx_we_r <= 1'b 0;	
            end
         else
            begin
            tx_fifo_state_r <= tx_fifo_state_nxt;	
            tx_fifo_cntr <= tx_fifo_cntr_nxt;	
            dma_rd_data_r <= dma_rd_data_nxt;	
            tx_wdata_r <= tx_wdata_nxt;	
            tx_we_r <= tx_we_nxt;	
            end
         end
      end
   end

assign tx_wdata = tx_wdata_r; //  drive tx wdata out
assign tx_we = tx_we_r; //  drive tx read enable out to fifo
// -------------------------------------------------------------------------
//  rx fifo state machine -
//  This state machine monitors the empty flag from the RX FIFO and
//  the rx flush command to move data from the RX FIFO and assemble them
//  into a 32 bit wide holding register. Based on the dma address register
//  bits 1 & 0 it will  load 1, 2, 3 or 4 bytes to handle any odd alignments
//  at the beginning or end of a packet. After assembling the bytes it will
//  tell the bvci_state machine to perform the transfer. When a flush
//  occurs, this state machine will assembly bytes in the holding register
//  and tell the bvci to write them to memory until the fifo is empty.
//  Cycles can't start unless the bvci state machine is in idle.
// -------------------------------------------------------------------------
always @(rx_fifo_state_r or dma_addr_r or rx_empty or rx_re_r or rx_rdata
 or rx_tdata_r or rx_fifo_flush_r or bvci_state_r or dma_wrt_data_r or dma_be_r
 or dma_wrt_en_r or endpt_stall or byte_count_eq or own or rx_fifo_cntr_r
 or dma_req_clr_r or flush_cnt_r)
   begin : rx_fifo_state_nxt_PROC
   rx_fifo_state_nxt <= rx_fifo_state_r;	
   dma_wrt_data_nxt <= dma_wrt_data_r;	
   dma_be_nxt <= dma_be_r;	
   rx_re_nxt <= rx_re_r;	
   rx_tdata_nxt <= rx_tdata_r;	
   rx_fifo_cntr_nxt <= rx_fifo_cntr_r;	
   flush_cnt_nxt <= flush_cnt_r;	
   case (rx_fifo_state_r)
   rxfifo_states_RXFIFO_IDLE:
      begin
      if (dma_wrt_en_r == 1'b 1 & endpt_stall == 1'b 0 & 
	byte_count_eq == 1'b 0 & rx_empty == 1'b 0 & 
	own == 1'b 1 & bvci_state_r == bvci_states_BVCI_IDLE)
         begin
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_READ;	//  there's data to read
         rx_fifo_cntr_nxt <= ~dma_addr_r[1:0];	
         rx_re_nxt <= 1'b 1;	
         end
      end
   rxfifo_states_RXFIFO_READ:
      begin
      rx_fifo_cntr_nxt <= rx_fifo_cntr_r - 1'b 1;	//  dec cntr for next
      rx_re_nxt <= 1'b 0;	
      case (rx_fifo_cntr_r)
      2'b 11:
         begin
         rx_tdata_nxt[7:0] <= rx_rdata;	
         dma_be_nxt[0] <= 1'b 1;	
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_WAIT;	
         end
      2'b 10:
         begin
         rx_tdata_nxt[15:8] <= rx_rdata;	
         dma_be_nxt[1] <= 1'b 1;	
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_WAIT;	
         end
      2'b 01:
         begin
         rx_tdata_nxt[23:16] <= rx_rdata;	
         dma_be_nxt[2] <= 1'b 1;	
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_WAIT;	
         end
      default:
         begin
         rx_tdata_nxt[31:24] <= rx_rdata;	
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_DONE;	
         dma_wrt_data_nxt <= 1'b 1;	
         dma_be_nxt[3] <= 1'b 1;	
         end
      endcase
      end
   rxfifo_states_RXFIFO_WAIT:
      begin
      if (rx_empty == 1'b 0)
         begin
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_READ;	
         rx_re_nxt <= 1'b 1;	
         end
//  go read the next byte
      else if (rx_fifo_flush_r == 1'b 1 )
         begin
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_DONE;	
         dma_wrt_data_nxt <= 1'b 1;	
         end
//  no more data so write it out
      end
   rxfifo_states_RXFIFO_DONE:
      begin
      if (dma_req_clr_r == 1'b 1)
         begin
         rx_fifo_state_nxt <= rxfifo_states_RXFIFO_IDLE;	
         dma_wrt_data_nxt <= 1'b 0;	
         dma_be_nxt <= 4'b 0000;	
         end
      end
   default:
      begin
      rx_fifo_state_nxt <= rxfifo_states_RXFIFO_IDLE;	
      dma_wrt_data_nxt <= 1'b 0;	
      dma_be_nxt <= 4'b 0000;	
      rx_re_nxt <= 1'b 0;	
      rx_tdata_nxt <= {32{1'b 0}};	
      rx_fifo_cntr_nxt <= 2'b 00;	
      flush_cnt_nxt <= 2'b 00;	
      end
   endcase
   end
//  sync part of state machine
//  drive outputs to defaults
always @(posedge clk or posedge rst_a)
   begin : rx_fifo_state_r_PROC
   if (rst_a == 1'b 1)
      begin
      rx_fifo_state_r <= rxfifo_states_RXFIFO_IDLE;	
      dma_wrt_data_r <= 1'b 0;	
      dma_be_r <= 4'b 0000;	
      rx_re_r <= 1'b 0;	
      rx_tdata_r <= {32{1'b 0}};	
      rx_fifo_cntr_r <= 2'b 00;	
      flush_cnt_r <= 2'b 00;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         rx_fifo_state_r <= rxfifo_states_RXFIFO_IDLE;	
         dma_wrt_data_r <= 1'b 0;	
         dma_be_r <= 4'b 0000;	
         rx_re_r <= 1'b 0;	
         rx_tdata_r <= {32{1'b 0}};	
         rx_fifo_cntr_r <= 2'b 00;	
         flush_cnt_r <= 2'b 00;	
         end
      else
         begin
         if (flush == 1'b 1)
            begin
            rx_fifo_state_r <= rxfifo_states_RXFIFO_IDLE;	
            dma_wrt_data_r <= 1'b 0;	
            dma_be_r <= 4'b 0000;	
            rx_re_r <= 1'b 0;	
            rx_tdata_r <= {32{1'b 0}};	
            rx_fifo_cntr_r <= 2'b 00;	
            flush_cnt_r <= 2'b 00;	
            end
         else
            begin
            rx_fifo_state_r <= rx_fifo_state_nxt;	
            dma_wrt_data_r <= dma_wrt_data_nxt;	
            dma_be_r <= dma_be_nxt;	
            rx_re_r <= rx_re_nxt;	
            rx_tdata_r <= rx_tdata_nxt;	
            rx_fifo_cntr_r <= rx_fifo_cntr_nxt;	
            flush_cnt_r <= flush_cnt_nxt;	
            end
         end
      end
   end

assign rx_re = rx_re_r; //  drive rx read enable out to fifo
// -------------------------------------------------------------------------
//  BVCI Initiator State Machine
//  This state machine will handle requests to read/write the Buffer
//  Descriptor Table or read/write data from the buffers from/to the fifo.
//  When reading the BDT, two 4-byte back to back cycles will take place.
//  When writing the BDT, one 4-byte cycle will take place.
//  When transfering data between the buffers and the FIFO, a single 4-byte 
//  cycle will take place unless there is less data to transfer at the
//  beginning or end of packets..
// -------------------------------------------------------------------------
always @(bvci_state_r or dma_rd_bdt_r or dma_rd_data_r or dma_req_clr_r or wrt_bdt_clr_r
 or rd_bdt_clr_r or dma_wrt_bdt_r or dma_wrt_data_r or dma_be_r or bdt_addr
 or bdt_wrt_data or dma_addr_r or bdt_rg0_r or byte_cnt_r or i_addr_r
 or i_be_r or i_cmd_r or i_cmdval_r or i_eop_r or i_wdata_r
 or i_rspval or i_rdata or i_cmdack or rx_tdata_r or txfr_cntr_r
 or tx_tdata_r)
   begin : bvci_state_nxt_PROC
   bvci_state_nxt <= bvci_state_r;	
   i_addr_nxt <= i_addr_r;	
   i_be_nxt <= i_be_r;	
   i_cmd_nxt <= i_cmd_r;	
   i_cmdval_nxt <= i_cmdval_r;	
   i_eop_nxt <= i_eop_r;	
   i_wdata_nxt <= i_wdata_r;	
   bdt_rg0_nxt <= bdt_rg0_r;	
   byte_cnt_nxt <= byte_cnt_r;	
   wrt_bdt_clr_nxt <= wrt_bdt_clr_r;	
   rd_bdt_clr_nxt <= rd_bdt_clr_r;	
   dma_req_clr_nxt <= dma_req_clr_r;	
   tx_tdata_nxt <= tx_tdata_r;	
   case (bvci_state_r)
   bvci_states_BVCI_IDLE:
      begin
      if (dma_wrt_bdt_r == 1'b 1)
         begin
         i_addr_nxt <= bdt_addr;	
         i_be_nxt <= 4'b 1111;	
         i_wdata_nxt <= bdt_wrt_data;	
         i_cmd_nxt <= CMD_WR;	
         i_cmdval_nxt <= 1'b 1;	
         i_eop_nxt <= 1'b 1;	
         wrt_bdt_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_WR_BDT_ACK;	
         end
      else if (dma_rd_bdt_r == 1'b 1 )
         begin
         i_addr_nxt <= bdt_addr;	
         i_be_nxt <= 4'b 1111;	
         i_cmd_nxt <= CMD_RD;	
         i_cmdval_nxt <= 1'b 1;	
         i_eop_nxt <= 1'b 0;	
         rd_bdt_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK1;	
         end
      else if (dma_wrt_data_r == 1'b 1 )
         begin
         i_addr_nxt <= {dma_addr_r[31:2], 2'b 00};	
         i_wdata_nxt <= rx_tdata_r;	//  temp holding register
         i_be_nxt <= dma_be_r;	
         i_cmd_nxt <= CMD_WR;	
         i_cmdval_nxt <= 1'b 1;	
         i_eop_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_WR_DATA_ACK;	
         end
      else if (dma_rd_data_r == 1'b 1 )
         begin
         i_addr_nxt <= {dma_addr_r[31:2], 2'b 00};	
         i_be_nxt <= 4'b 1111;	
         i_cmd_nxt <= CMD_RD;	
         i_cmdval_nxt <= 1'b 1;	
         i_eop_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_RD_CMD_ACK;	
// -------------------------------------------------------------------
//  read bdt states
// -------------------------------------------------------------------
//  sent 1st command waiting for comamnd ack and or data valid
         end
      end
   bvci_states_RD_BDT_WAIT_CMDACK1:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_addr_nxt[2] <= 1'b 1;	//  inc add 2 for the next 4 bytes
         i_eop_nxt <= 1'b 1;	
         bdt_rg0_nxt <= i_rdata[7:0];	
         byte_cnt_nxt <= i_rdata[25:16];	
         rd_bdt_clr_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK2;	
         end
//  accepted cmd, has data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_addr_nxt[2] <= 1'b 1;	//  inc add 2 for the next 4 bytes
         i_eop_nxt <= 1'b 1;	
         rd_bdt_clr_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_DATA1;	
         end
//  accepted cmd, no data
      else if (i_cmdack == 1'b 0 & i_rspval == 1'b 1 )
         begin
         bdt_rg0_nxt <= i_rdata[7:0];	
         byte_cnt_nxt <= i_rdata[25:16];	
         rd_bdt_clr_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK1_D1;	
//  this is a weird state would a target accept data but not the command
         end
//  accepted data not cmd
      end
   bvci_states_RD_BDT_WAIT_CMDACK1_D1:
      begin
      if (i_cmdack == 1'b 1)
         begin
         i_addr_nxt[2] <= 1'b 1;	//  inc add 2 for the next 4 bytes
         i_eop_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK2;	
//  sent 2nd command waiting for 2nd ack & 2nd data valid
         end
//  accepted cmd
      end
   bvci_states_RD_BDT_WAIT_CMDACK2:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
         end
//  accepted cmd has data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_addr_nxt[2] <= 1'b 1;	//  inc add 2 for the next 4 bytes
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         i_eop_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_DATA2;	
         end
//  accepted cmd no data
      else if (i_cmdack == 1'b 0 & i_rspval == 1'b 1 )
         begin
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK2_D2;	
//  this is a weird state would a target accept data but not the command
         end
//  accepted data no cmd
      end
   bvci_states_RD_BDT_WAIT_CMDACK2_D2:
      begin
      if (i_cmdack == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
//  sent 2nd command waiting for 1st data valid
         end
//  accepted cmd
      end
   bvci_states_RD_BDT_WAIT_DATA1:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bdt_rg0_nxt <= i_rdata[7:0];	
         byte_cnt_nxt <= i_rdata[25:16];	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_DATA2;	
         end
//  accepted cmd has data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_DATA1_2;	
         end
//  accepted cmd no data
      else if (i_cmdack == 1'b 0 & i_rspval == 1'b 1 )
         begin
         bdt_rg0_nxt <= i_rdata[7:0];	
         byte_cnt_nxt <= i_rdata[25:16];	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_CMDACK2;	
//  sent both commands waiting for 1st response
         end
//  accepted data no cmd
      end
   bvci_states_RD_BDT_WAIT_DATA1_2:
      begin
      if (i_rspval == 1'b 1)
         begin
         bdt_rg0_nxt <= i_rdata[7:0];	
         byte_cnt_nxt <= i_rdata[25:16];	
         bvci_state_nxt <= bvci_states_RD_BDT_WAIT_DATA2;	
//  waiting for 2nd data valid
         end
//  has data
      end
   bvci_states_RD_BDT_WAIT_DATA2:
      begin
      if (i_rspval == 1'b 1)
         begin
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
// -------------------------------------------------------------------
//  write bdt 
// -------------------------------------------------------------------
//  waiting for ack to command write
         end
//  accepted cmd has data
      end
   bvci_states_BVCI_WR_BDT_ACK:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         wrt_bdt_clr_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
         end
//  accepted cmd, no data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         wrt_bdt_clr_nxt <= 1'b 0;	
         bvci_state_nxt <= bvci_states_BVCI_WR_BDT_WAIT_RSP;	
         end
//  accepted cmd & data
      end
   bvci_states_BVCI_WR_BDT_WAIT_RSP:
      begin
      if (i_rspval == 1'b 1)
         begin
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
// -------------------------------------------------------------------
//  write data
// -------------------------------------------------------------------
//  waiting for ack to command write
         end
      end
   bvci_states_BVCI_WR_DATA_ACK:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         dma_req_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_DMA_TXFR;	
         end
//  acc. cmd, data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_BVCI_WR_DATA_WAIT_RSP;	
         end
//  acc. cmd, no data
      end
   bvci_states_BVCI_WR_DATA_WAIT_RSP:
      begin
      if (i_rspval == 1'b 1)
         begin
         dma_req_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_DMA_TXFR;	
// -------------------------------------------------------------------
//  read data states
// -------------------------------------------------------------------
         end
      end
   bvci_states_BVCI_RD_CMD_ACK:
      begin
      if (i_cmdack == 1'b 1 & i_rspval == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         tx_tdata_nxt <= i_rdata;	
         dma_req_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_DMA_TXFR;	
         end
//  accepted cmd has data
      else if (i_cmdack == 1'b 1 & i_rspval == 1'b 0 )
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_BVCI_RD_DATA;	
         end
//  accepted cmd no data
      else if (i_cmdack == 1'b 0 & i_rspval == 1'b 1 )
         begin
         tx_tdata_nxt <= i_rdata;	
         dma_req_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_RD_DATA_ACK;	
//  this is a weird state I don't think the target will respnd to data
//  before the command, but just in case
         end
//  accepted data not
//  cmd
      end
   bvci_states_BVCI_RD_DATA_ACK:
      begin
      if (i_cmdack == 1'b 1)
         begin
         i_eop_nxt <= 1'b 0;	
         i_cmdval_nxt <= 1'b 0;	
         i_cmd_nxt <= CMD_NOP;	
         bvci_state_nxt <= bvci_states_BVCI_DMA_TXFR;	
         end
//  accepted cmd 
      end
   bvci_states_BVCI_RD_DATA:
      begin
      if (i_rspval == 1'b 1)
         begin
         tx_tdata_nxt <= i_rdata;	
         dma_req_clr_nxt <= 1'b 1;	
         bvci_state_nxt <= bvci_states_BVCI_DMA_TXFR;	
// -------------------------------------------------------------------
//  end of dma cycles allow txfr count to load and then count down
//  before allowing another dma operation
// -------------------------------------------------------------------
         end
      end
   bvci_states_BVCI_DMA_TXFR:
      begin
      dma_req_clr_nxt <= 1'b 0;	
      bvci_state_nxt <= bvci_states_BVCI_DMA_DONE;	
      end
   bvci_states_BVCI_DMA_DONE:
      begin
      if (txfr_cntr_r == 3'b 000)
         begin
         bvci_state_nxt <= bvci_states_BVCI_IDLE;	
// -------------------------------------------------------------------
// default state
// -------------------------------------------------------------------
         end
      end
   default:
      begin
      bvci_state_nxt <= bvci_states_BVCI_IDLE;	
      i_addr_nxt <= {32{1'b 0}};	
      i_be_nxt <= {4{1'b 0}};	
      i_cmd_nxt <= CMD_NOP;	
      i_cmdval_nxt <= 1'b 0;	
      i_eop_nxt <= 1'b 0;	
      i_wdata_nxt <= {32{1'b 0}};	
      bdt_rg0_nxt <= {8{1'b 0}};	
      byte_cnt_nxt <= {10{1'b 0}};	
      wrt_bdt_clr_nxt <= 1'b 0;	
      rd_bdt_clr_nxt <= 1'b 0;	
      dma_req_clr_nxt <= 1'b 0;	
      tx_tdata_nxt <= {32{1'b 0}};	
      end
   endcase
   end
//  generate a load signal when the second read data is valid to grab the
//  dma address and load counters
//  drive outputs to defaults
assign bdt_ld = i_rspval == 1'b 1 & (bvci_state_r == bvci_states_RD_BDT_WAIT_CMDACK2 | 
	bvci_state_r == bvci_states_RD_BDT_WAIT_DATA2) ? 1'b 1 : 
	1'b 0; 
// -------------------------------------------------------------------------
//  synchronous part of the state machine
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : bvci_state_r_PROC
   if (rst_a == 1'b 1)
      begin
      bvci_state_r <= bvci_states_BVCI_IDLE;	
      i_addr_r <= {32{1'b 0}};	
      i_be_r <= {4{1'b 0}};	
      i_cmd_r <= CMD_NOP;	
      i_cmdval_r <= 1'b 0;	
      i_eop_r <= 1'b 0;	
      i_wdata_r <= {32{1'b 0}};	
      bdt_rg0_r <= {8{1'b 0}};	
      byte_cnt_r <= {10{1'b 0}};	
      wrt_bdt_clr_r <= 1'b 0;	
      rd_bdt_clr_r <= 1'b 0;	
      dma_req_clr_r <= 1'b 0;	
      tx_tdata_r <= {32{1'b 0}};	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         bvci_state_r <= bvci_states_BVCI_IDLE;	
         i_addr_r <= {32{1'b 0}};	
         i_be_r <= {4{1'b 0}};	
         i_cmd_r <= CMD_NOP;	
         i_cmdval_r <= 1'b 0;	
         i_eop_r <= 1'b 0;	
         i_wdata_r <= {32{1'b 0}};	
         bdt_rg0_r <= {8{1'b 0}};	
         byte_cnt_r <= {10{1'b 0}};	
         wrt_bdt_clr_r <= 1'b 0;	
         rd_bdt_clr_r <= 1'b 0;	
         dma_req_clr_r <= 1'b 0;	
         tx_tdata_r <= {32{1'b 0}};	
         end
      else
         begin
         bvci_state_r <= bvci_state_nxt;	
         i_addr_r <= i_addr_nxt;	
         i_be_r <= i_be_nxt;	
         i_cmd_r <= i_cmd_nxt;	
         i_cmdval_r <= i_cmdval_nxt;	
         i_eop_r <= i_eop_nxt;	
         i_wdata_r <= i_wdata_nxt;	
         bdt_rg0_r <= bdt_rg0_nxt;	
         byte_cnt_r <= byte_cnt_nxt;	
         wrt_bdt_clr_r <= wrt_bdt_clr_nxt;	
         rd_bdt_clr_r <= rd_bdt_clr_nxt;	
         dma_req_clr_r <= dma_req_clr_nxt;	
         tx_tdata_r <= tx_tdata_nxt;	
         end
      end
   end

assign i_rspack = 1'b 1; //  tie this high      
//  the bdt register gets loaded from this state machine pick off some of
//  the bits with meaningful names
assign own = bdt_rg0_r[7] & bdt_valid_r & ~stat_full; //  0 = micro
//  1 = sie
assign keep = bdt_rg0_r[5]; //  dma does not update the BDT
assign ninc = bdt_rg0_r[4]; //  dma doesn't increment
//  drive out output signals
assign i_address = i_addr_r; 
assign i_be = i_be_r; 
assign i_cmd = i_cmd_r; 
assign i_cmdval = i_cmdval_r; 
assign i_eop = i_eop_r; 
assign i_wdata = i_wdata_r; 
// -------------------------------------------------------------------------
//  endpoint odd bits -
//  these get toggled when the sie sends a token_dne_set indicating that he
//  is finished with a packet.
// -------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : endpt_odd_r_PROC
   if (rst_a == 1'b 1)
      begin
      endpt0_txd_odd_r <= 1'b 0;	
      endpt1_txd_odd_r <= 1'b 0;	
      endpt2_txd_odd_r <= 1'b 0;	
      endpt3_txd_odd_r <= 1'b 0;	
      endpt4_txd_odd_r <= 1'b 0;	
      endpt5_txd_odd_r <= 1'b 0;	
      endpt6_txd_odd_r <= 1'b 0;	
      endpt7_txd_odd_r <= 1'b 0;	
      endpt8_txd_odd_r <= 1'b 0;	
      endpt9_txd_odd_r <= 1'b 0;	
      endpt10_txd_odd_r <= 1'b 0;	
      endpt11_txd_odd_r <= 1'b 0;	
      endpt12_txd_odd_r <= 1'b 0;	
      endpt13_txd_odd_r <= 1'b 0;	
      endpt14_txd_odd_r <= 1'b 0;	
      endpt15_txd_odd_r <= 1'b 0;	
      endpt0_rxd_odd_r <= 1'b 0;	
      endpt1_rxd_odd_r <= 1'b 0;	
      endpt2_rxd_odd_r <= 1'b 0;	
      endpt3_rxd_odd_r <= 1'b 0;	
      endpt4_rxd_odd_r <= 1'b 0;	
      endpt5_rxd_odd_r <= 1'b 0;	
      endpt6_rxd_odd_r <= 1'b 0;	
      endpt7_rxd_odd_r <= 1'b 0;	
      endpt8_rxd_odd_r <= 1'b 0;	
      endpt9_rxd_odd_r <= 1'b 0;	
      endpt10_rxd_odd_r <= 1'b 0;	
      endpt11_rxd_odd_r <= 1'b 0;	
      endpt12_rxd_odd_r <= 1'b 0;	
      endpt13_rxd_odd_r <= 1'b 0;	
      endpt14_rxd_odd_r <= 1'b 0;	
      endpt15_rxd_odd_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         endpt0_txd_odd_r <= 1'b 0;	
         endpt1_txd_odd_r <= 1'b 0;	
         endpt2_txd_odd_r <= 1'b 0;	
         endpt3_txd_odd_r <= 1'b 0;	
         endpt4_txd_odd_r <= 1'b 0;	
         endpt5_txd_odd_r <= 1'b 0;	
         endpt6_txd_odd_r <= 1'b 0;	
         endpt7_txd_odd_r <= 1'b 0;	
         endpt8_txd_odd_r <= 1'b 0;	
         endpt9_txd_odd_r <= 1'b 0;	
         endpt10_txd_odd_r <= 1'b 0;	
         endpt11_txd_odd_r <= 1'b 0;	
         endpt12_txd_odd_r <= 1'b 0;	
         endpt13_txd_odd_r <= 1'b 0;	
         endpt14_txd_odd_r <= 1'b 0;	
         endpt15_txd_odd_r <= 1'b 0;	
         endpt0_rxd_odd_r <= 1'b 0;	
         endpt1_rxd_odd_r <= 1'b 0;	
         endpt2_rxd_odd_r <= 1'b 0;	
         endpt3_rxd_odd_r <= 1'b 0;	
         endpt4_rxd_odd_r <= 1'b 0;	
         endpt5_rxd_odd_r <= 1'b 0;	
         endpt6_rxd_odd_r <= 1'b 0;	
         endpt7_rxd_odd_r <= 1'b 0;	
         endpt8_rxd_odd_r <= 1'b 0;	
         endpt9_rxd_odd_r <= 1'b 0;	
         endpt10_rxd_odd_r <= 1'b 0;	
         endpt11_rxd_odd_r <= 1'b 0;	
         endpt12_rxd_odd_r <= 1'b 0;	
         endpt13_rxd_odd_r <= 1'b 0;	
         endpt14_rxd_odd_r <= 1'b 0;	
         endpt15_rxd_odd_r <= 1'b 0;	
//  Implement endpoint odd address enable bits
         end
      else
         begin
         if (odd_rst == 1'b 1)
            begin
            endpt0_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0000 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt0_txd_odd_r <= ~endpt0_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt1_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0001 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt1_txd_odd_r <= ~endpt1_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt2_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0010 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt2_txd_odd_r <= ~endpt2_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt3_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0011 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt3_txd_odd_r <= ~endpt3_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt4_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0100 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt4_txd_odd_r <= ~endpt4_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt5_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0101 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt5_txd_odd_r <= ~endpt5_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt6_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0110 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt6_txd_odd_r <= ~endpt6_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt7_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0111 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt7_txd_odd_r <= ~endpt7_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt8_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1000 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt8_txd_odd_r <= ~endpt8_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt9_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1001 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt9_txd_odd_r <= ~endpt9_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt10_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1010 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt10_txd_odd_r <= ~endpt10_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt11_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1011 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt11_txd_odd_r <= ~endpt11_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt12_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1100 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt12_txd_odd_r <= ~endpt12_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt13_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1101 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt13_txd_odd_r <= ~endpt13_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt14_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1110 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt14_txd_odd_r <= ~endpt14_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt15_txd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1111 & tx_datpkt_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt15_txd_odd_r <= ~endpt15_txd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt0_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0000 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt0_rxd_odd_r <= ~endpt0_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt1_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0001 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt1_rxd_odd_r <= ~endpt1_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt2_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0010 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt2_rxd_odd_r <= ~endpt2_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt3_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0011 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt3_rxd_odd_r <= ~endpt3_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt4_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0100 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt4_rxd_odd_r <= ~endpt4_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt5_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0101 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt5_rxd_odd_r <= ~endpt5_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt6_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0110 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt6_rxd_odd_r <= ~endpt6_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt7_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 0111 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt7_rxd_odd_r <= ~endpt7_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt8_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1000 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt8_rxd_odd_r <= ~endpt8_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt9_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1001 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt9_rxd_odd_r <= ~endpt9_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt10_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1010 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt10_rxd_odd_r <= ~endpt10_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt11_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1011 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt11_rxd_odd_r <= ~endpt11_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt12_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1100 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt12_rxd_odd_r <= ~endpt12_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt13_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1101 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt13_rxd_odd_r <= ~endpt13_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt14_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1110 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt14_rxd_odd_r <= ~endpt14_rxd_odd_r;	//  Toggle 
            end
         if (odd_rst == 1'b 1)
            begin
            endpt15_rxd_odd_r <= 1'b 0;	//  Reset 
            end
         else if (current_endpt_r == 4'b 1111 & out_token_proc == 1'b 1 & 
	tok_dne_set == 1'b 1 )
            begin
            endpt15_rxd_odd_r <= ~endpt15_rxd_odd_r;	//  Toggle 
            end
         end
      end
   end

assign odd_bdt = txd_token == 1'b 1 ? endpt_txd_odd : 
	endpt_rxd_odd; 
// -------------------------------------------------------------------------
//  Target Read Logic
//  Select read data based on address in.
//  then register the output along with the response valid signal
// -------------------------------------------------------------------------
//  USB Peripheral ID
//  USB Peripheral ID Complement
//  USB Revision (defined in vusb_cfg)
//  USB Additional info
//  USB OTG Interrupt status
//  USB OTG Interrupt Control
//  USB OTG Status register
//  USB OTG Control register
//  Interrupt status register
//  Interrupt enable register
//  Error status register
//  Error enable register
//  Status register
//  Control register
//  Address register
//  BDT Page register (bits 15:8)
//  Frame number low register
//  Frame number high register
//  Token register
//  SOF threshold register
//  BDT Page register (bits 23:16)
//  BDT Page register (bits 31:24)
//  Endpoint control register0
//  Endpoint control register1
//  Endpoint control register2
//  Endpoint control register3
//  Endpoint control register4
//  Endpoint control register5
//  Endpoint control register6
//  Endpoint control register7
//  Endpoint control register8
//  Endpoint control register9
//  Endpoint control register10
//  Endpoint control register11
//  Endpoint control register12
//  Endpoint control register13
//  Endpoint control register14
//  Endpoint control register15
assign add_info = IMPLEMENT_EMBEDED_HOST == 1'b 1 ? {IRQ_NUM, ADD_INFO_HST} : 
	{IRQ_NUM, ADD_INFO_DEV}; 
// ----------------------------------------------------------------------------------------------------------
//  otg signal sync and debounce logic
// ----------------------------------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : otg_sync_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_id_r1 <= 1'b 0;	
      usb_id_r2 <= 1'b 0;	
      usb_sess_vld_r1 <= 1'b 0;	
      usb_sess_vld_r2 <= 1'b 0;	
      usb_b_sess_end_r1 <= 1'b 0;	
      usb_b_sess_end_r2 <= 1'b 0;	
      usb_a_vbus_vld_r1 <= 1'b 0;	
      usb_a_vbus_vld_r2 <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_id_r1 <= 1'b 0;	
         usb_id_r2 <= 1'b 0;	
         usb_sess_vld_r1 <= 1'b 0;	
         usb_sess_vld_r2 <= 1'b 0;	
         usb_b_sess_end_r1 <= 1'b 0;	
         usb_b_sess_end_r2 <= 1'b 0;	
         usb_a_vbus_vld_r1 <= 1'b 0;	
         usb_a_vbus_vld_r2 <= 1'b 0;	
         end
      else
         begin
         usb_id_r2 <= hc_en & usb_id_r1;	
         usb_id_r1 <= hc_en & usb_id;	
         usb_sess_vld_r2 <= hc_en & usb_sess_vld_r1;	
         usb_sess_vld_r1 <= hc_en & usb_sess_vld;	
         usb_b_sess_end_r2 <= hc_en & usb_b_sess_end_r1;	
         usb_b_sess_end_r1 <= hc_en & usb_b_sess_end;	
         usb_a_vbus_vld_r2 <= hc_en & usb_a_vbus_vld_r1;	
         usb_a_vbus_vld_r1 <= hc_en & usb_a_vbus_vld;	
         end
      end
   end

assign hc_usb_id_r2 = hc_en & usb_id_r2; 
assign hc_usb_sess_vld_r2 = hc_en & usb_sess_vld_r2; 
assign hc_usb_b_sess_end_r2 = hc_en & usb_b_sess_end_r2; 
assign hc_usb_a_vbus_vld_r2 = hc_en & usb_a_vbus_vld_r2; 
//  set the stable indicator equal to 1 at the begining of the debounce
//  interval.  If you ever see a change on the signal clear the stable indicator.
always @(posedge clk or posedge rst_a)
   begin : otg_stable_r_PROC
   if (rst_a == 1'b 1)
      begin
      otg_stable_id_r <= 1'b 0;	
      otg_stable_se0_r <= 1'b 0;	
      otg_stable_jstate_r <= 1'b 0;	
      otg_stable_linestate_r <= 1'b 0;	
      otg_stable_sess_vld_r <= 1'b 0;	
      otg_stable_b_sess_end_r <= 1'b 0;	
      otg_stable_a_vbus_vld_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         otg_stable_id_r <= 1'b 0;	
         otg_stable_se0_r <= 1'b 0;	
         otg_stable_jstate_r <= 1'b 0;	
         otg_stable_linestate_r <= 1'b 0;	
         otg_stable_sess_vld_r <= 1'b 0;	
         otg_stable_b_sess_end_r <= 1'b 0;	
         otg_stable_a_vbus_vld_r <= 1'b 0;	
         end
      else if (usb_1msec_r == 1'b 1 )
         begin
         otg_stable_id_r <= hc_en & ~(hc_usb_id_r2 ^ hc_usb_id_last);	
         otg_stable_se0_r <= hc_en & ~(se0 ^ hc_usb_se0_last);	
         otg_stable_jstate_r <= hc_en & ~(rcv ^ hc_usb_jstate_last);	
         otg_stable_linestate_r <= hc_en & otg_stable_linestate;	
         otg_stable_sess_vld_r <= hc_en & ~(hc_usb_sess_vld_r2 ^ hc_usb_sess_vld_last);	
         otg_stable_b_sess_end_r <= hc_en & ~(hc_usb_b_sess_end_r2 ^ hc_usb_b_sess_end_last);	
         otg_stable_a_vbus_vld_r <= hc_en & ~(hc_usb_a_vbus_vld_r2 ^ hc_usb_a_vbus_vld_last);	
//  clear the stable bits if a change is detected.
         end
//  set the stable bits at the start of the debounce 
      else
         begin
         otg_stable_id_r <= hc_otg_stable_id & ~(hc_usb_id_r2 ^ hc_usb_id_last);	
         otg_stable_se0_r <= hc_otg_stable_se0 & ~(se0 ^ hc_usb_se0_last);	
         otg_stable_jstate_r <= hc_otg_stable_jstate & ~(rcv ^ hc_usb_jstate_last);	
         otg_stable_sess_vld_r <= hc_otg_stable_sess_vld & ~(hc_usb_sess_vld_r2 ^ hc_usb_sess_vld_last);	
         otg_stable_b_sess_end_r <= hc_otg_stable_b_sess_end & ~(hc_usb_b_sess_end_r2 ^ hc_usb_b_sess_end_last);	
         otg_stable_a_vbus_vld_r <= hc_otg_stable_a_vbus_vld & ~(hc_usb_a_vbus_vld_r2 ^ hc_usb_a_vbus_vld_last);	
         end
      end
   end

assign hc_otg_stable_id = hc_en & otg_stable_id_r; 
assign hc_otg_stable_se0 = hc_en & otg_stable_se0_r; 
assign hc_otg_stable_jstate = hc_en & otg_stable_jstate_r; 
assign hc_otg_stable_linestate = hc_en & otg_stable_linestate_r; 
assign otg_stable_linestate = hc_en & otg_stable_se0_r & (otg_stable_jstate_r | hc_usb_se0_last); 
//  Noise may cause Jstate to change while SE0 is true.
assign hc_otg_stable_sess_vld = hc_en & otg_stable_sess_vld_r; 
assign hc_otg_stable_b_sess_end = hc_en & otg_stable_b_sess_end_r; 
assign hc_otg_stable_a_vbus_vld = hc_en & otg_stable_a_vbus_vld_r; 
//  if the signal has been stable for 1 msec call the last value debounced
always @(posedge clk or posedge rst_a)
   begin : usb_deb_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_id_deb_r <= 1'b 0;	
      usb_se0_deb_r <= 1'b 0;	
      usb_jstate_deb_r <= 1'b 0;	
      usb_sess_vld_deb_r <= 1'b 0;	
      usb_b_sess_end_deb_r <= 1'b 0;	
      usb_a_vbus_vld_deb_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_id_deb_r <= 1'b 0;	
         usb_se0_deb_r <= 1'b 0;	
         usb_jstate_deb_r <= 1'b 0;	
         usb_sess_vld_deb_r <= 1'b 0;	
         usb_b_sess_end_deb_r <= 1'b 0;	
         usb_a_vbus_vld_deb_r <= 1'b 0;	
         end
      else
         begin
         if ((hc_en & usb_1msec_r & hc_otg_stable_id) == 1'b 1)
            begin
            usb_id_deb_r <= hc_usb_id_last;	
            end
         if ((hc_en & usb_1msec_r & hc_otg_stable_se0) == 1'b 1)
            begin
            usb_se0_deb_r <= hc_usb_se0_last;	
            end
         if ((hc_en & usb_1msec_r & hc_otg_stable_jstate) == 1'b 1)
            begin
            usb_jstate_deb_r <= hc_usb_jstate_last;	
            end
         if ((hc_en & usb_1msec_r & hc_otg_stable_sess_vld) == 1'b 1)
            begin
            usb_sess_vld_deb_r <= hc_usb_sess_vld_last;	
            end
         if ((hc_en & usb_1msec_r & hc_otg_stable_b_sess_end) == 1'b 1)
            begin
            usb_b_sess_end_deb_r <= hc_usb_b_sess_end_last;	
            end
         if ((hc_en & usb_1msec_r & hc_otg_stable_a_vbus_vld) == 1'b 1)
            begin
            usb_a_vbus_vld_deb_r <= hc_usb_a_vbus_vld_last;	
            end
         end
      end
   end

assign hc_usb_id_deb = hc_en & usb_id_deb_r; 
assign hc_usb_se0_deb = hc_en & usb_se0_deb_r; 
assign hc_usb_jstate_deb = hc_en & usb_jstate_deb_r; 
assign hc_usb_sess_vld_deb = hc_en & usb_sess_vld_deb_r; 
assign hc_usb_b_sess_end_deb = hc_en & usb_b_sess_end_deb_r; 
assign hc_usb_a_vbus_vld_deb = hc_en & usb_a_vbus_vld_deb_r; 
//  grab a copy of the synchronize inputs and store it.
always @(posedge clk or posedge rst_a)
   begin : usb_last_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_id_last_r <= 1'b 0;	
      usb_se0_last_r <= 1'b 0;	
      usb_jstate_last_r <= 1'b 0;	
      usb_sess_vld_last_r <= 1'b 0;	
      usb_b_sess_end_last_r <= 1'b 0;	
      usb_a_vbus_vld_last_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_id_last_r <= 1'b 0;	
         usb_se0_last_r <= 1'b 0;	
         usb_jstate_last_r <= 1'b 0;	
         usb_sess_vld_last_r <= 1'b 0;	
         usb_b_sess_end_last_r <= 1'b 0;	
         usb_a_vbus_vld_last_r <= 1'b 0;	
         end
      else if (hc_en == 1'b 1 )
         begin
         usb_id_last_r <= hc_usb_id_r2;	
         usb_se0_last_r <= se0;	
         usb_jstate_last_r <= rcv;	
         usb_sess_vld_last_r <= hc_usb_sess_vld_r2;	
         usb_b_sess_end_last_r <= hc_usb_b_sess_end_r2;	
         usb_a_vbus_vld_last_r <= hc_usb_a_vbus_vld_r2;	
         end
      end
   end

assign hc_usb_id_last = hc_en & usb_id_last_r; 
assign hc_usb_se0_last = hc_en & usb_se0_last_r; 
assign hc_usb_jstate_last = hc_en & usb_jstate_last_r; 
assign hc_usb_sess_vld_last = hc_en & usb_sess_vld_last_r; 
assign hc_usb_b_sess_end_last = hc_en & usb_b_sess_end_last_r; 
assign hc_usb_a_vbus_vld_last = hc_en & usb_a_vbus_vld_last_r; 
// ----------------------------------------------------------------------------------------------------------
//  1 msec prescaler counter used for deboucing otg inputs and also used for software heart beat
// ----------------------------------------------------------------------------------------------------------
always @(posedge clk or posedge rst_a)
   begin : usb_1msec_tmr_r_PROC
   if (rst_a == 1'b 1)
      begin
      usb_1msec_tmr_r <= {14{1'b 0}};	
      usb_1msec_r <= 1'b 0;	
      end
   else
      begin
      if (rst == 1'b 1)
         begin
         usb_1msec_tmr_r <= {14{1'b 0}};	
         usb_1msec_r <= 1'b 0;	
         end
      else
         begin
         if (hc_en == 1'b 1 & usb_1msec_tmr_r == 0 & 
	sys_clken12 == 1'b 1)
            begin
	    usb_1msec_tmr_r <= ONE_MS_TMR_LD;	
            end
         else if (hc_en == 1'b 1 & sys_clken12 == 1'b 1 )
            begin
            usb_1msec_tmr_r <= usb_1msec_tmr_r - 1'b 1;	
            end
         if (hc_en == 1'b 1 & usb_1msec_tmr_r == 0 & 
	sys_clken12 == 1'b 1)
            begin
            usb_1msec_r <= 1'b 1;	
            end
         else
            begin
            usb_1msec_r <= 1'b 0;	
            end
         end
      end
   end

assign hc_usb_1msec = hc_en & usb_1msec_r; 
// -------------------------------------------------------------------------
//  Assign control/data bus inputs from sie
// -------------------------------------------------------------------------
//  Control Data Bus Definitions:
// 
//   cdb_in(40)     : out_data01_pid - This bit is represents the DATA PID
//                    received during a SETUP or Rx Data Packet. If 0 we are
//                    receiving a DATA0 PID, if 1 we are receving a DATA1
//                    PID. This value is written back to memory in the BDT
//                    control byte (bit 6).
//   cdb_in(39:36)  : bdt_wrt_pid - These 4 bits represent the current
//                    token pid value. It is valid when a TOK_DNE is
//                    active.
//   cdb_in(35:25)  : frame_num - These 11 bits represent the last frame
//                    number that was received via a SOF packet. It is
//                    valid after SOF_TOK has gone active.
//   cdb_in(24:21)  : current_endpt - These four bits represent the current
//                    endpoint that the USB is using. This value will be
//                    stored by the up_int in the stat_rg when tok_dne_set=1.
//   cdb_in(20)     : tx_datpkt_proc - This bit indicates that the usb_sie is
//                    processing a tx data packet.
//   cdb_in(19)     : out_token_proc - This bit indicates that the usb_sie is
//                    processing a rx data packet.
//   cdb_in(18:17)  : sie_dma_req - These two bits define the type of DMA
//                    request that the SIE is requesting. The bits are
//                    defined as:
// 
//                     17 16 | Type of DMA request
//                    -------+--------------------------------------
//                      0  1 | BDT read DMA request (i.e. 6 bytes)
//                      1  0 | BDT write DMA request (i.e. 6 bytes)
// 
//                    NOTE: The SIE will only activate one of the request
//                    bits at a time.
// 
//   cdb_in(16)     : dma_early_req - This signal is used to have the DMA
//                    request the bus early. No bus cycles are performed
//                    with this request signal on the bus is requested.
//                    This is useful in design when the bus_gnt latency
//                    could exceed xxx ns, (zzz sie clks).
//   cdb_in(15)     : bts_err_set - This signal when active will set the
//                    BTS_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(14)     : own_err_set - This signal when active will set the
//                    OWN_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(13)     : dma_err_set - This signal when active will set the
//                    DMA_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(12)     : bto_err_set - This signal when active will set the
//                    BTO_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(11)     : dfn8_err_set - This signal when active will set the
//                    DF8N_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(10)     : crc16_err_set - This signal when active will set the
//                    CRC16_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(9)      : crc5_err_set - This signal when active will set the
//                    CRC5_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(8)      : pid_err_set - This signal when active will set the
//                    PID_ERR interrupt in the error status register
//                    (err_stat_rg).
//   cdb_in(7:6)    : RSVD
//   cdb_in(5)      : resume_set - This signal when active will set the
//                    RESUME interrupt in the interrupt status register
//                    (istat_rg).
//   cdb_in(4)      : sleep_set - This signal when active will set the
//                    SLEEP interrupt in the interrupt status register
//                    (istat_rg).
//   cdb_in(3)      : tok_dne_set - This signal when active will set the
//                    TOK_DNE interrupt in the interrupt status register
//                    (istat_rg).
//   cdb_in(2)      : sof_tok_set - This signal when active will set the
//                    SOF_TOK interrupt in the interrupt status register
//                    (istat_rg).
//   cdb_in(1)      : error_set - This signal when active will set the
//                    ERROR interrupt in the interrupt status register
//                    (istat_rg).
//   cdb_in(0)      : usb_rst_set - This signal when active will set the
//                    USB_RST interrupt in the interrupt status register
//                    (istat_rg).
assign txd_token = cdb_in[45]; //  current tx token
assign endpt_stall_clr = cdb_in[44]; //  clear stall
assign endpt_stall_set = cdb_in[43]; //  set stall
assign txdsuspend_tokbusy_clr = cdb_in[42]; //  clear txd suspend
assign txdsuspend_tokbusy_set = cdb_in[41]; //  set txd suspend
assign out_data01_pid = cdb_in[40]; //  0 = data0 pid
assign bdt_wrt_pid = cdb_in[39:36]; //  current pid
assign frm_numh_rg = {5'b 00000, cdb_in[35:33]}; //  frame #
assign frm_numl_rg = cdb_in[32:25]; 
assign current_endpt = cdb_in[24:21]; //  current endpoint
assign tx_datpkt_proc = cdb_in[20]; //  sie processing a tx packet
assign out_token_proc = cdb_in[19]; //  sie processing a rx packet
assign sie_dma_req[3:2] = cdb_in[18:17]; //  dma requests
//  01 = read
//  10 = write
//  dma_early_req           <= cdb_in(16);  -- early dma bus request
assign bts_err_set = cdb_in[15]; //  sets bts error bit
assign own_err_set = cdb_in[14]; //  sets own error bit
assign dma_err_set = cdb_in[13]; //  sets dma error bit
assign bto_err_set = cdb_in[12]; //  sets bto error bit
assign dfn8_err_set = cdb_in[11]; //  sets df8 error bit
assign crc16_err_set = cdb_in[10]; //  sets crc error bit
assign crc5_err_set = cdb_in[9]; //  sets crc error bit
assign pid_err_set = cdb_in[8]; //  sets pid error bit
assign stall_int_set = cdb_in[7]; //  sets stall interrupt
assign hc_attach_set = cdb_in[6]; //  sets attach interrupt
assign resume_set = cdb_in[5]; //  sets resume interrupt
assign sleep_set = cdb_in[4]; //  sets sleep interrupt
assign tok_dne_set = cdb_in[3]; //  sets tok_dne interupt
assign sof_tok_set = cdb_in[2]; //  sets sof_tok interrupt
//  cdb_in(1);   -- used to be error_set
assign usb_rst_set = cdb_in[0]; //  sets usb_rst interrupt
// -------------------------------------------------------------------------
//  assign host control outputs to sie
// -------------------------------------------------------------------------
//  host only bits
assign cdb_out[43] = hc_retry_disable; //  disable retry
assign cdb_out[42] = resume_req; //  generate resume
assign cdb_out[41] = hc_rst_req; //  generate reset
assign cdb_out[40] = txdsuspend_tokbusy_r; //  suspend tx
assign cdb_out[39:32] = hc_sof_thld_rg; //  sof threshold
assign cdb_out[31:28] = hc_token_pid; //  token pid
assign cdb_out[27:24] = hc_token_endpt; //  endpoint #
// -------------------------------------------------------------------------
//  assign device control outputs to sie
// -------------------------------------------------------------------------
//   cdb_out(23:17) : addr(6:0) - This is the USB address that the usb_sie
//                    will compare with token packets.
//   cdb_out(16)    : byte_count_eq - This bit informs the usb_sie that
//                    the DMA engine has reached a terminal byte count.
//                    Data transmission should terminate when all remaining
//                    data has been read from the Tx FIFO.
//   cdb_out(15)    : odd_rst - reset the PING/PONG odd bits.
//   cdb_out(14:13) : RSVD
//   cdb_out(12:8)  : ep_ctl - Endpoint control bits.
// 
//                 12           11         10         9         8
//           +------------+-----------+----------+----------+---------+
//           | ep_ctl_dis | ep_out_en | ep_in_en | ep_stall | ep_hshk |
//           +------------+-----------+----------+----------+---------+
// 
//   cdb_out(7:2)   : bdt(7:2) - These signals are the first byte of
//                    the BDT. They contain the following control bits:
// 
//                       7       6          5       4      3     2
//                    +-----+---------+----------+------+-----+------+
//                    | own | data0/1 | vusb_own | ninc | dts | rsvd |
//                    +-----+---------+----------+------+-----+------+
// 
//   cdb_out(1)     : bdt_valid - When this bit is active high it indicates
//                    that the BDT control bits are valid.
//   cdb_out(0)     : usb_en - This is the USB enable signal from the control
//                    register.
// 
assign cdb_out[23:17] = usb_addr_r[6:0]; //  usb address
assign cdb_out[16] = byte_count_eq; //  byte count equals
assign cdb_out[15] = 1'b 0; //  use to be odd_rst
assign cdb_out[14:13] = 2'b 00; //  reserved
assign cdb_out[12:8] = endpt_ctl; //  12 en_ctl_dis
//  11 ep_out_en
//  10 ep_in_en
//  9  ep_stall
//  8  ep_hshk
assign cdb_out[7] = own; //  own
assign cdb_out[6:2] = bdt_rg0_r[6:2]; //  6 data0/1
//  5 vusb_own
//  4 ninc
//  3 dts
//  2 stall
assign cdb_out[1] = bdt_valid_r; //  valid bdt bits
assign cdb_out[0] = usb_en_int; //  enable interface  
assign endpt_ctl = current_endpt == 4'b 0000 ? endpt0_r : 
	current_endpt == 4'b 0001 ? endpt1_r : 
	current_endpt == 4'b 0010 ? endpt2_r : 
	current_endpt == 4'b 0011 ? endpt3_r : 
	current_endpt == 4'b 0100 ? endpt4_reg : 
	current_endpt == 4'b 0101 ? endpt5_reg : 
	current_endpt == 4'b 0110 ? endpt6_reg : 
	current_endpt == 4'b 0111 ? endpt7_reg : 
	current_endpt == 4'b 1000 ? endpt8_reg : 
	current_endpt == 4'b 1001 ? endpt9_reg : 
	current_endpt == 4'b 1010 ? endpt10_reg : 
	current_endpt == 4'b 1011 ? endpt11_reg : 
	current_endpt == 4'b 1100 ? endpt12_reg : 
	current_endpt == 4'b 1101 ? endpt13_reg : 
	current_endpt == 4'b 1110 ? endpt14_reg : 
	current_endpt == 4'b 1111 ? endpt15_reg : 
	5'b xxxxx; 
assign endpt_txd_odd = current_endpt == 4'b 0000 ? endpt0_txd_odd_r : 
	current_endpt == 4'b 0001 ? endpt1_txd_odd_r : 
	current_endpt == 4'b 0010 ? endpt2_txd_odd_r : 
	current_endpt == 4'b 0011 ? endpt3_txd_odd_r : 
	current_endpt == 4'b 0100 ? endpt4_txd_odd_r : 
	current_endpt == 4'b 0101 ? endpt5_txd_odd_r : 
	current_endpt == 4'b 0110 ? endpt6_txd_odd_r : 
	current_endpt == 4'b 0111 ? endpt7_txd_odd_r : 
	current_endpt == 4'b 1000 ? endpt8_txd_odd_r : 
	current_endpt == 4'b 1001 ? endpt9_txd_odd_r : 
	current_endpt == 4'b 1010 ? endpt10_txd_odd_r : 
	current_endpt == 4'b 1011 ? endpt11_txd_odd_r : 
	current_endpt == 4'b 1100 ? endpt12_txd_odd_r : 
	current_endpt == 4'b 1101 ? endpt13_txd_odd_r : 
	current_endpt == 4'b 1110 ? endpt14_txd_odd_r : 
	current_endpt == 4'b 1111 ? endpt15_txd_odd_r : 
	1'b X; 
assign endpt_rxd_odd = current_endpt == 4'b 0000 ? endpt0_rxd_odd_r : 
	current_endpt == 4'b 0001 ? endpt1_rxd_odd_r : 
	current_endpt == 4'b 0010 ? endpt2_rxd_odd_r : 
	current_endpt == 4'b 0011 ? endpt3_rxd_odd_r : 
	current_endpt == 4'b 0100 ? endpt4_rxd_odd_r : 
	current_endpt == 4'b 0101 ? endpt5_rxd_odd_r : 
	current_endpt == 4'b 0110 ? endpt6_rxd_odd_r : 
	current_endpt == 4'b 0111 ? endpt7_rxd_odd_r : 
	current_endpt == 4'b 1000 ? endpt8_rxd_odd_r : 
	current_endpt == 4'b 1001 ? endpt9_rxd_odd_r : 
	current_endpt == 4'b 1010 ? endpt10_rxd_odd_r : 
	current_endpt == 4'b 1011 ? endpt11_rxd_odd_r : 
	current_endpt == 4'b 1100 ? endpt12_rxd_odd_r : 
	current_endpt == 4'b 1101 ? endpt13_rxd_odd_r : 
	current_endpt == 4'b 1110 ? endpt14_rxd_odd_r : 
	current_endpt == 4'b 1111 ? endpt15_rxd_odd_r : 
	1'b X; 
assign rd_datao = addr_i == ID_FIELD_ADD ? ID_FIELD : 
	addr_i == ID_COMP_ADD ? COMP_ID : 
	addr_i == REV_ADD ? VUSB32_REV : 
	addr_i == ADD_INFO_ADD ? add_info : 
	addr_i == OTG_ISTAT_ADD ? otg_istat : 
	addr_i == OTG_ICTRL_ADD ? otg_ictrl_r : 
	addr_i == OTG_STAT_ADD ? otg_stat : 
	addr_i == OTG_CTRL_ADD ? otg_ctrl_r : 
	addr_i == INT_STAT_ADD ? int_stat_rg : 
	addr_i == INT_ENBL_ADD ? int_enb_r : 
	addr_i == ERR_STAT_ADD ? err_stat_rg : 
	addr_i == ERR_ENBL_ADD ? err_enb_r : 
	addr_i == USB_STAT_ADD ? stat_rdata : 
	addr_i == USB_CTRL_ADD ? ctl_rg_out : 
	addr_i == USB_ADDR_ADD ? usb_addr_r : 
	addr_i == BDT_PAG1_ADD ? bdt_page1_r : 
	addr_i == FRM_NUML_ADD ? frm_numl_rg : 
	addr_i == FRM_NUMH_ADD ? frm_numh_rg : 
	addr_i == HST_TOKN_ADD ? hc_token_r : 
	addr_i == SOF_THLD_ADD ? hc_sof_thld_rg : 
	addr_i == BDT_PAG2_ADD ? bdt_page2_r : 
	addr_i == BDT_PAG3_ADD ? bdt_page3_r : 
	addr_i == END_CTL0_ADD ? {host_wo_hub_int, hc_retry_disable, 1'b 0, 
	endpt0_r} : 
	addr_i == END_CTL1_ADD ? {3'b 000, endpt1_r} : 
	addr_i == END_CTL2_ADD ? {3'b 000, endpt2_r} : 
	addr_i == END_CTL3_ADD ? {3'b 000, endpt3_r} : 
	addr_i == END_CTL4_ADD ? {3'b 000, endpt4_r} : 
	addr_i == END_CTL5_ADD ? {3'b 000, endpt5_r} : 
	addr_i == END_CTL6_ADD ? {3'b 000, endpt6_r} : 
	addr_i == END_CTL7_ADD ? {3'b 000, endpt7_r} : 
	addr_i == END_CTL8_ADD ? {3'b 000, endpt8_r} : 
	addr_i == END_CTL9_ADD ? {3'b 000, endpt9_r} : 
	addr_i == END_CTLA_ADD ? {3'b 000, endpt10_r} : 
	addr_i == END_CTLB_ADD ? {3'b 000, endpt11_r} : 
	addr_i == END_CTLC_ADD ? {3'b 000, endpt12_r} : 
	addr_i == END_CTLD_ADD ? {3'b 000, endpt13_r} : 
	addr_i == END_CTLE_ADD ? {3'b 000, endpt14_r} : 
	addr_i == END_CTLF_ADD ? {3'b 000, endpt15_r} : 
	8'b 00000000; 
// ---------------------------------------------------------------------------
//  Requires the sync_set/reset attribute to insure no Xes in simulation
//  The following line is used when translating to Verilog...
//  _synopsys sync_set_reset "rst"
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
//  constant definitions for usb registers - not the ID register space
// ---------------------------------------------------------------------------
//  Define address constants Look the lower two bits aren't there!
//  ID/Revision/Add_info

endmodule // module vusb_up_int_bvci