TDBIAUSBNNFPOC.v
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// VERSION:1.00 DATE:2002/07/26 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAUSBNNFPOC ( N01, N02, N03, N04, N05, H01, H02, H03, H04, H05, H06, H07, H08 );
inout N01;
output N02;
output N03;
output N04;
output N05;
input H01;
input H02;
input H03;
input H04;
input H05;
input H06;
input H07;
input H08;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
buf ( _H06, H06 );
buf ( _H07, H07 );
buf ( _H08, H08 );
not ( _G001, _H03 );
and ( _G002, _H01, _G001 );
bufif0 ( _G003, _H02, _H04 );
buf ( _G004, _G003 );
bufif1 ( _G005, _G002, _G004 );
bufif1 ( N01F, _G005, _G004 );
buf ( _N01F, N01 );
TDBIAUSBNNFPOC_PECL u1 ( _G006, _N01F, _H05 );
not ( _G0001, _H06 );
or ( _G014, _G006, _G0001 );
bufif0 ( _G007, _G014, _H04 );
buf ( N02F, _G007 );
nor ( _G008, N01, _H05, _H07 );
bufif0 ( _G009, _G008, _H04 );
buf ( N03F, _G009 );
or ( _G010, N01, _H07 );
bufif0 ( _G011, _G010, _H04 );
buf ( N04F, _G011 );
or ( _G012, _H05, _H07 );
bufif0 ( _G013, _G012, _H04 );
buf ( N05F, _G013 );
// *** insert for slow speed xcvr
nor ( _G002S, _H01, _H03 );
and ( _ENA, _H02, _H08 );
bufif1 ( _G003S, _ENA, _H04 );
buf ( _G004S, _G003S );
bufif1 ( _G005S, _G002S, _G004S );
bufif1 ( N01S, _G005S, _G004S );
TDBIAUSBNNLPOC_PECL u2 ( _G006S, _H05, N01 );
and ( _G014S, _G006S, _H06 );
bufif1 ( _G007S, _G014S, _H04 );
buf ( N02S, _G007S );
nor ( _G008S, N01, _H05, _H07 );
bufif1 ( _G009S, _G008S, _H04 );
buf ( N03S, _G009S );
or ( _G010S, N01, _H07 );
bufif1 ( _G011S, _G010S, _H04 );
buf ( N04S, _G011S );
or ( _G012S, _H05, _H07 );
bufif1 ( _G013S, _G012S, _H04 );
buf ( N05S, _G013S );
// *** cover both speed modes
assign
N01 = H04 ? N01S : N01F ,
N02 = H04 ? N02S : N02F ,
N03 = H04 ? N03S : N03F ,
N04 = H04 ? N04S : N04F ,
N05 = H04 ? N05S : N05F ;
defparam u1.PECL_DLY = 40001;
defparam u2.PECL_DLY = 40001;
wire flag_PECL = (u1.flag_PECL & ~H04) | (u2.flag_PECL & H04) ;
specify
specparam DMY_SPC=1:1:1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( H05 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N05 ) = ( DMY_SPC, DMY_SPC );
( H06 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N03 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N04 ) = ( DMY_SPC, DMY_SPC );
( H07 *> N05 ) = ( DMY_SPC, DMY_SPC );
if ( !flag_PECL )
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N03 ) = ( DMY_SPC, DMY_SPC );
( N01 *> N04 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine