// VERSION:1.00 DATE:2001/04/05 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module TDIPAPECR ( H01 );
input H01;

buf (_H01, H01);

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine