// VERSION:1.00 DATE:2002/06/04 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module THVSALVDN ( H01, H02 );
    input H01 ;
    input H02 ;

    buf ( _H01, H01 );
    buf ( _H02, H02 );

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine