vcs.max.com
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#!/bin/csh -f
#
# This is the script to execute opc_verilog.
# Created by OPC_VCS at Fri Oct 18 15:33:50 PDT 2002
vcs \
\
### filename list of HDL files \
# Controle module of simulation \
A5C382CORE_top.v \
\
# User module \
A5C382CORE.v \
\
### options of VCS \
\
# library assignment \
+libext+.v \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/verilog_udp' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/testact' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/clockdriver' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/iobuffer' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/nec_bscan' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/primitive' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/scan' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/special' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/nec_scan' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/gating' \
-y '/opc/cb12_V3.1.0/solaris/lib/common/verilog/oscillator' \
-y '/opc/cb12_V3.1.0/solaris/lib/CB12/cmos_1.5V/vcs/full_model/analog' \
\
# controle of logging \
-V -l vcs.max.log \
\
# list of PLI tables and objects \
-P /opc/cb12_V3.1.0/solaris/lib/common/verilogpli/nec_signoff.vcstab \
\
/opc/cb12_V3.1.0/solaris/lib/common/verilogpli/libpli.a \
/opc/cb12_V3.1.0/solaris/lib/common/verilogpli/libmisc.a \
/opc/cb12_V3.1.0/solaris/lib/common/verilogpli/int64.a \
/opc/cb12_V3.1.0/solaris/lib/common/verilogpli/cpthnd.a \
\
-o simv.max \
\
# incremental compile mode \
-Mupdate \
\
# controle of simulation mode \
+maxdelays # delay mode setting \
\
# disables to issue the warning message \
+nowarnTFNPC # about floating ports \
\
# set the pulse transfer mode \
+transport_path_delays +pulse_r/0 \
+transport_int_delays +pulse_int_r/0 \
\
+pulse_e/100 +pulse_int_e/0 +no_pulse_msg # X spike silently \
\
if ( ${status} ) exit 1
./simv.max \
\
# controle of logging \
-V -a vcs.max.log \
\
+trc \
\