//--------------------------------------------------
//  NOVeA 16w32b SuperCell Verilog Simulation Library for Virage
//  Version: 2.1
//  ------------
//  02/11/05   Version 1.0 Initial release by M.Honma
//			NOTE : based on NEC_Proj_021102.tar.gz from Virage
//  
//  02/11/15   Version 2.0  Changed by Virage new release by M.Honma
//			NOTE : based on ship_nec_110702 from Virage
//
//  02/11/29   Version 2.0a expand Virage Macro's BUS
//  02/12/17   Version 2.1  set "ME" low in TestMode
//                          cell name change from nvcp_nc15gfh_BUS to nvcp_nc15gfh_16x32_BUS
//  03/02/14   Version 2.2  ADD "PU3" Pin to ChargePump and NOVeA
//  
//  Design Unit:
//  ------------
//      Unit    Name  :  nms_sc_16x32
//      Hierarchy     :  nms_sc_16x32
//                           +--------- nvrm_nc15gfh_16x32_BUS (NOVeA Cell)
//                                            +--------nvrm_nc15gfh_16x32   <= Single BIT
//                           +--------- nvcp_nc15gfh_16x32_BUS (Charge Pump)
//                                            +--------nvcp_nc15gfh         <= Single BIT

module nms_sc_16x32 ( 
    CLK,RST,PE,VPPRANGE,VPPSEL3,VPPSEL2,VPPSEL1,VPPSEL0,
    D,CLKE,STORE,VPP,PORST,UNLOCK,
    ADR3,ADR2,ADR1,ADR0,
    D31,D30,D29,D28,D27,D26,D25,D24,
    D23,D22,D21,D20,D19,D18,D17,D16,
    D15,D14,D13,D12,D11,D10,D9,D8,
    D7,D6,D5,D4,D3,D2,D1,D0,
    ME,WE,
    SI,SME,SCLK,SO,
    RECALL,COMP,MRCL0,MRCL1,
    TECC0,TECC1,BIAS0,BIAS1,
    Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24,
    Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16,
    Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8,
    Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,
    MATCH,RCREADY,
// NEC TestBus
    TEST,BUNRI,
    TBI21,TBI20,TBI19,TBI18,TBI17,TBI16,TBI15,TBI14,
    TBI13,TBI12,TBI11,TBI10,TBI9,TBI8,TBI7,TBI6,
    TBI5,TBI4,TBI3,TBI2,TBI1,TBI0,
    TBO4,TBO3,TBO2,TBO1,TBO0
);

//--- Port ---
    // to both charge pump and NOVeA
    input  CLK,STORE ;
    // charge pump
    input  RST,PE,VPPRANGE,VPPSEL3,VPPSEL2,VPPSEL1,VPPSEL0,D,CLKE ;
    output VPP;			// only for monitor in PAD 
    output PORST;
    output UNLOCK;
    // NOVeA
    input  ADR3,ADR2,ADR1,ADR0;
    input  D31,D30,D29,D28,D27,D26,D25,D24;
    input  D23,D22,D21,D20,D19,D18,D17,D16;
    input  D15,D14,D13,D12,D11,D10,D9,D8;
    input  D7,D6,D5,D4,D3,D2,D1,D0;
    input  ME,WE;
    input  SI,SME,SCLK;
    output SO;
    input  RECALL,COMP,MRCL0,MRCL1;
    input  TECC0,TECC1,BIAS0,BIAS1;
    output Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24;
    output Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16;
    output Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8;
    output Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0;
    output MATCH;
    output RCREADY;
    // NEC TestBus
    input  TEST,BUNRI;
    input  TBI21,TBI20,TBI19,TBI18,TBI17,TBI16,TBI15,TBI14;
    input  TBI13,TBI12,TBI11,TBI10,TBI9,TBI8,TBI7,TBI6;
    input  TBI5,TBI4,TBI3,TBI2,TBI1,TBI0;
    output TBO4,TBO3,TBO2,TBO1,TBO0;

//--- wire ---
    wire  n_PU1;		// between charge_pump and NOVeA
    wire  n_PU2;		// between charge_pump and NOVeA
    wire  n_PU3;		// between charge_pump and NOVeA

    wire  t_CLK;
    wire  t_RST;
    wire  t_PE;
    wire  t_VPPRANGE;
    wire  t_VPPSEL3;
    wire  t_VPPSEL2;
    wire  t_VPPSEL1;
    wire  t_VPPSEL0;
    wire  t_D;
    wire  t_CLKE;
    wire  t_STORE;
    wire  t_SI;
    wire  t_SME;
    wire  t_SCLK;
    wire  t_RECALL;
    wire  t_COMP;
    wire  t_MRCL0;
    wire  t_MRCL1;
    wire  t_TECC0;
    wire  t_TECC1;
    wire  t_BIAS0;
    wire  t_BIAS1;

// Output Enable of NOVeA
    wire  t_OE;
    assign t_OE		= 1'b1 ; 	// always enable to prevent Hi-Z 

// NEC Test Enable
    wire  SC_TestEn;	
    assign SC_TestEn 	= BUNRI & TEST ;

// set "ME" low in TestMode
    wire  t_ME;	
    assign t_ME 	= SC_TestEn ? 1'b0 : ME ;

// input MUX for TestBus
    assign t_CLK 	= SC_TestEn ? TBI0 : CLK ;
    assign t_RST 	= SC_TestEn ? TBI1 : RST ;
    assign t_PE 	= SC_TestEn ? TBI2 : PE ;
    assign t_VPPRANGE 	= SC_TestEn ? TBI3 : VPPRANGE ;
    assign t_VPPSEL3 	= SC_TestEn ? TBI4 : VPPSEL3 ;
    assign t_VPPSEL2 	= SC_TestEn ? TBI5 : VPPSEL2 ;
    assign t_VPPSEL1 	= SC_TestEn ? TBI6 : VPPSEL1 ;
    assign t_VPPSEL0 	= SC_TestEn ? TBI7 : VPPSEL0 ;
    assign t_D 		= SC_TestEn ? TBI8 : D ;
    assign t_CLKE 	= SC_TestEn ? TBI9 : CLKE ;
    assign t_STORE 	= SC_TestEn ? TBI10 : STORE ;
    assign t_SI 	= SC_TestEn ? TBI11 : SI ;
    assign t_SME 	= SC_TestEn ? TBI12 : SME ;
    assign t_SCLK 	= SC_TestEn ? TBI13 : SCLK ;
    assign t_RECALL 	= SC_TestEn ? TBI14 : RECALL ;
    assign t_COMP 	= SC_TestEn ? TBI15 : COMP ;
    assign t_MRCL0 	= SC_TestEn ? TBI16 : MRCL0 ;
    assign t_MRCL1 	= SC_TestEn ? TBI17 : MRCL1 ;
    assign t_TECC0 	= SC_TestEn ? TBI18 : TECC0 ;
    assign t_TECC1 	= SC_TestEn ? TBI19 : TECC1 ;
    assign t_BIAS0 	= SC_TestEn ? TBI20 : BIAS0 ;
    assign t_BIAS1 	= SC_TestEn ? TBI21 : BIAS1 ;

// output MUX(AND) for TestBus
    assign TBO0 	= SC_TestEn ? PORST : 1'b0 ;
    assign TBO1 	= SC_TestEn ? UNLOCK : 1'b0 ;
    assign TBO2 	= SC_TestEn ? MATCH : 1'b0 ;
    assign TBO3 	= SC_TestEn ? RCREADY : 1'b0 ;
    assign TBO4 	= SC_TestEn ? SO : 1'b0 ;
  
// charge pump instantiation
    nvcp_nc15gfh_16x32_BUS I_charge_pump (
      .CLK(t_CLK),
      .RST(t_RST),
      .VPPRANGE(t_VPPRANGE),
      .VPPSEL({t_VPPSEL3,t_VPPSEL2,t_VPPSEL1,t_VPPSEL0}),
      .PE(t_PE),
      .D(t_D),
      .CLKE(t_CLKE),
      .STORE(t_STORE),
      .VPP(VPP),
      .UNLOCK(UNLOCK),
      .PU1(n_PU1),
      .PU2(n_PU2),
      .PU3(n_PU3),
      .PORST(PORST)
    );

// NOVeA instantiation
    nvrm_nc15gfh_16x32_BUS I_NOVeA (
      .VPP(VPP),
      .CLK(t_CLK),
      .ADR({ADR3,ADR2,ADR1,ADR0}),
      .D({D31, D30, D29, D28, D27, D26, D25, D24,
          D23, D22, D21, D20, D19, D18, D17, D16, 
          D15, D14, D13, D12, D11, D10, D9, D8,
          D7, D6, D5, D4, D3, D2, D1, D0}),
      .WE(WE),
      .ME(t_ME),
      .OE(t_OE),
      .SI(t_SI),
      .SCLK(t_SCLK),
      .SME(t_SME),
      .COMP(t_COMP),
      .STORE(t_STORE),
      .RECALL(t_RECALL),
      .MRCL0(t_MRCL0),
      .MRCL1(t_MRCL1),
      .TECC0(t_TECC0),
      .TECC1(t_TECC1),
      .BIAS0(t_BIAS0),
      .BIAS1(t_BIAS1),
      .PU1(n_PU1),
      .PU2(n_PU2),
      .PU3(n_PU3),
      .Q({Q31, Q30, Q29, Q28, Q27, Q26, Q25, Q24,
          Q23, Q22, Q21, Q20, Q19, Q18, Q17, Q16,
          Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8,
          Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0}), 
      .SO(SO),
      .MATCH(MATCH),
      .RCREADY(RCREADY)
  );


endmodule

//
// Charge_Pump Bus Model
//
module nvcp_nc15gfh_16x32_BUS ( 
    VPPRANGE, VPPSEL, PE, RST, CLK, D, CLKE, STORE, VPP, UNLOCK, PU1, PU2, PU3, PORST
);

input VPPRANGE;
input  [3:0] VPPSEL;
input PE;
input RST;
input CLK;
input D;
input CLKE;
input STORE;
output VPP;
output UNLOCK;
output PU1;
output PU2;
output PU3;
output PORST;

    nvcp_nc15gfh I_charge_pump_Expand (
      .CLK(CLK),
      .RST(RST),
      .VPPRANGE(VPPRANGE),
      .VPPSEL3(VPPSEL[3]),
      .VPPSEL2(VPPSEL[2]),
      .VPPSEL1(VPPSEL[1]),
      .VPPSEL0(VPPSEL[0]),
      .PE(PE),
      .D(D),
      .CLKE(CLKE),
      .STORE(STORE),
      .VPP(VPP),
      .UNLOCK(UNLOCK),
      .PU1(PU1),
      .PU2(PU2),
      .PU3(PU3),
      .PORST(PORST)
    );

endmodule

//
// NOVeA Bus Model
//
module nvrm_nc15gfh_16x32_BUS ( 
   Q, SO, MATCH, ADR, D, WE, ME, OE, CLK, SI, SCLK, SME, COMP, STORE, RECALL, VPP,
   MRCL0, MRCL1, TECC0, TECC1, BIAS0, BIAS1, RCREADY, PU1, PU2, PU3
);

output  [31:0] Q;
output SO;
output MATCH;
input  [3:0] ADR;
input  [31:0] D;
input WE;
input ME;
input OE;
input CLK;
input SI;
input SCLK;
input SME;
input COMP;
input STORE;
input RECALL;
input VPP;
input MRCL0;
input MRCL1;
input TECC0;
input TECC1;
input BIAS0;
input BIAS1;
output RCREADY;
input PU1;
input PU2;
input PU3;

    nvrm_nc15gfh_16x32 I_NOVeA_Expand (
      .VPP(VPP),
      .CLK(CLK),
      .ADR3(ADR[3]),
      .ADR2(ADR[2]),
      .ADR1(ADR[1]),
      .ADR0(ADR[0]),
      .D31(D[31]),
      .D30(D[30]),
      .D29(D[29]),
      .D28(D[28]),
      .D27(D[27]),
      .D26(D[26]),
      .D25(D[25]),
      .D24(D[24]),
      .D23(D[23]),
      .D22(D[22]),
      .D21(D[21]),
      .D20(D[20]),
      .D19(D[19]),
      .D18(D[18]),
      .D17(D[17]),
      .D16(D[16]),
      .D15(D[15]),
      .D14(D[14]),
      .D13(D[13]),
      .D12(D[12]),
      .D11(D[11]),
      .D10(D[10]),
      .D9(D[9]),
      .D8(D[8]),
      .D7(D[7]),
      .D6(D[6]),
      .D5(D[5]),
      .D4(D[4]),
      .D3(D[3]),
      .D2(D[2]),
      .D1(D[1]),
      .D0(D[0]),
      .WE(WE),
      .ME(ME),
      .OE(OE),
      .SI(SI),
      .SCLK(SCLK),
      .SME(SME),
      .COMP(COMP),
      .STORE(STORE),
      .RECALL(RECALL),
      .MRCL0(MRCL0),
      .MRCL1(MRCL1),
      .TECC0(TECC0),
      .TECC1(TECC1),
      .BIAS0(BIAS0),
      .BIAS1(BIAS1),
      .PU1(PU1),
      .PU2(PU2),
      .PU3(PU3),
      .Q31(Q[31]),
      .Q30(Q[30]),
      .Q29(Q[29]),
      .Q28(Q[28]),
      .Q27(Q[27]),
      .Q26(Q[26]),
      .Q25(Q[25]),
      .Q24(Q[24]),
      .Q23(Q[23]),
      .Q22(Q[22]),
      .Q21(Q[21]),
      .Q20(Q[20]),
      .Q19(Q[19]),
      .Q18(Q[18]),
      .Q17(Q[17]),
      .Q16(Q[16]),
      .Q15(Q[15]),
      .Q14(Q[14]),
      .Q13(Q[13]),
      .Q12(Q[12]),
      .Q11(Q[11]),
      .Q10(Q[10]),
      .Q9(Q[9]),
      .Q8(Q[8]),
      .Q7(Q[7]),
      .Q6(Q[6]),
      .Q5(Q[5]),
      .Q4(Q[4]),
      .Q3(Q[3]),
      .Q2(Q[2]),
      .Q1(Q[1]),
      .Q0(Q[0]),
      .SO(SO),
      .MATCH(MATCH),
      .RCREADY(RCREADY)
  );

endmodule