//==================================================================
// NOVeA Memory System 
//	for 512 (16w x 32b )
//==================================================================

`resetall
`timescale 1 ns / 10 ps

 `define ADR_MSB          3                     /*Address Bus MSB*/
 `define D_MSB            31                    /*Data Bus MSB*/
 `define NB               32                    /*Number of Bits*/
 `define PAR_I_MSB        2                     /*Parallel Instruction MSB*/
 `define NMS_NAME         nms_top_16x32		/*NMS Name*/
 `define NMS_CTRLR_NAME   nvco_nc15gfh_16x32    /*NMS Controller Name*/
 `define NOVEA_NAME       nvrm_nc15gfh_16x32	/*NOVeA Name*/
 `define CHPUMP_NAME      nvcp_nc15gfh		/*Charge Pump Name*/
 `define SC_NAME	  nms_sc_16x32		/*SuperCell Name*/


// ================        `NMS_NAME    (NMS)       ===================
module `NMS_NAME(
      SYS_CK,
      TIME_B,
      WRSTN,
      WRCK,
      WSI,
      UpdateWR,
      ShiftWR,
      SelectWIR,
      ADR_p,
      D_p,
      WE_p,
      ME_p,
      OE_p,
      PAE_p,
      PA_p,
      RA_p,

      WSO,
      Q,		// NOVeA Outputs
      NMS_READY,
      NMS_PASS,
      KEEP_ON,

      OE_NV,		// Output for MUX
      Q_CR		// Config Register Outputs
  );

 input SYS_CK;
 input TIME_B;
 input WRSTN;
 input WRCK;
 input WSI;
 input UpdateWR;
 input ShiftWR;
 input SelectWIR;
 input [`ADR_MSB:0] ADR_p;
 input [`D_MSB:0] D_p;
 input WE_p;
 input ME_p;
 input OE_p;
 input PAE_p;
 input [`PAR_I_MSB:0] PA_p;
 input RA_p;

 output WSO;
 output [`D_MSB:0] Q;		// NOVeA Outputs
 output NMS_READY;
 output NMS_PASS;
 output KEEP_ON;

 output [`D_MSB:0] Q_CR;	// Config Register Outputs
 output OE_NV;			// OutputEnable NOVeA Q Outputs

//  -----------       Wires        --------------
  wire WSO;
  wire NMS_READY;
  wire NMS_PASS;
  wire KEEP_ON;
  wire RCREADY;
  wire SO_NV;
  wire MATCH;
  wire UNLOCK;
  wire PORST;
  wire RST_i;
  wire PE;
  wire VPPRANGE;
  wire [3:0] VPPSEL;
  wire UDATA;
  wire PCLKE;
  wire SI_NV;
  wire SME_NV;
  wire STORE;
  wire COMP;
  wire RECALL;
  wire MRCL0;
  wire MRCL1;
  wire TECC0;
  wire TECC1;
  wire BIAS0;
  wire BIAS1;
  wire PU1;
  wire PU2;
  wire VPP;
  wire WE_NV;
  wire ME_NV;

  wire CLK;
  wire SCLK_NV;
  wire [`ADR_MSB:0] ADR_NV;
  wire [`NB-1:0] D_NV;


// -----------       `NMS_CTRLR_NAME (NMS_Controller)  Instantiation       ----------
  `NMS_CTRLR_NAME U_NMSC (
      .SYS_CK(SYS_CK),
      .TIME_B(TIME_B),
      .WRSTN(WRSTN),
      .WRCK(WRCK),
      .WSI(WSI),
      .UpdateWR(UpdateWR),
      .ShiftWR(ShiftWR),
      .SelectWIR(SelectWIR),
      .PAE_p(PAE_p),
      .PA_p(PA_p),
      .RCREADY(RCREADY),
      .SO_NV(SO_NV),
      .MATCH(MATCH),
      .UNLOCK(UNLOCK),
      .PORST(PORST),
      .ADR_p(ADR_p),
      .D_p(D_p),
      .RA_p(RA_p),
      .WE_p(WE_p),
      .ME_p(ME_p),
      .OE_p(OE_p),

      .WSO(WSO),
      .NMS_READY(NMS_READY),
      .NMS_PASS(NMS_PASS),
      .KEEP_ON(KEEP_ON),
      .RST_i(RST_i),
      .PE(PE),
      .VPPRANGE(VPPRANGE),
      .VPPSEL(VPPSEL),
      .UDATA(UDATA),
      .PCLKE(PCLKE),
      .SI_NV(SI_NV),
      .SME_NV(SME_NV),
      .STORE(STORE),
      .COMP(COMP),
      .RECALL(RECALL),
      .MRCL0(MRCL0),
      .MRCL1(MRCL1),
      .TECC0(TECC0),
      .TECC1(TECC1),
      .BIAS0(BIAS0),
      .BIAS1(BIAS1),
      .Q(Q_CR),		// To Output
      .WE_NV(WE_NV),	
      .OE_NV(OE_NV),	// To Output
      .ME_NV(ME_NV),	
      .CLK(CLK),		
      .SCLK_NV(SCLK_NV),	
      .ADR_NV(ADR_NV),	
      .D_NV(D_NV)	
  );


// -----------       SuperCell  Instantiation       ----------
  `SC_NAME U_SC (
      .CLK(CLK),
      .RST(RST_i),
      .VPPRANGE(VPPRANGE),
      .VPPSEL3(VPPSEL[3]),
      .VPPSEL2(VPPSEL[2]),
      .VPPSEL1(VPPSEL[1]),
      .VPPSEL0(VPPSEL[0]),
      .PE(PE),
      .D(UDATA),
      .CLKE(PCLKE),
      .STORE(STORE),
      .UNLOCK(UNLOCK),
      .PORST(PORST),

      .ADR3(ADR_NV[3]),
      .ADR2(ADR_NV[2]),
      .ADR1(ADR_NV[1]),
      .ADR0(ADR_NV[0]),
      .D31(D_NV[31]),
      .D30(D_NV[30]),
      .D29(D_NV[29]),
      .D28(D_NV[28]),
      .D27(D_NV[27]),
      .D26(D_NV[26]),
      .D25(D_NV[25]),
      .D24(D_NV[24]),
      .D23(D_NV[23]),
      .D22(D_NV[22]),
      .D21(D_NV[21]),
      .D20(D_NV[20]),
      .D19(D_NV[19]),
      .D18(D_NV[18]),
      .D17(D_NV[17]),
      .D16(D_NV[16]),
      .D15(D_NV[15]),
      .D14(D_NV[14]),
      .D13(D_NV[13]),
      .D12(D_NV[12]),
      .D11(D_NV[11]),
      .D10(D_NV[10]),
      .D9(D_NV[9]),
      .D8(D_NV[8]),
      .D7(D_NV[7]),
      .D6(D_NV[6]),
      .D5(D_NV[5]),
      .D4(D_NV[4]),
      .D3(D_NV[3]),
      .D2(D_NV[2]),
      .D1(D_NV[1]),
      .D0(D_NV[0]),
      .WE(WE_NV),
      .ME(ME_NV),
      .SI(SI_NV),
      .SCLK(SCLK_NV),
      .SME(SME_NV),
      .COMP(COMP),
      .RECALL(RECALL),
      .MRCL0(MRCL0),
      .MRCL1(MRCL1),
      .TECC0(TECC0),
      .TECC1(TECC1),
      .BIAS0(BIAS0),
      .BIAS1(BIAS1),
      .Q31(Q[31]),
      .Q30(Q[30]),
      .Q29(Q[29]),
      .Q28(Q[28]),
      .Q27(Q[27]),
      .Q26(Q[26]),
      .Q25(Q[25]),
      .Q24(Q[24]),
      .Q23(Q[23]),
      .Q22(Q[22]),
      .Q21(Q[21]),
      .Q20(Q[20]),
      .Q19(Q[19]),
      .Q18(Q[18]),
      .Q17(Q[17]),
      .Q16(Q[16]),
      .Q15(Q[15]),
      .Q14(Q[14]),
      .Q13(Q[13]),
      .Q12(Q[12]),
      .Q11(Q[11]),
      .Q10(Q[10]),
      .Q9(Q[9]),
      .Q8(Q[8]),
      .Q7(Q[7]),
      .Q6(Q[6]),
      .Q5(Q[5]),
      .Q4(Q[4]),
      .Q3(Q[3]),
      .Q2(Q[2]),
      .Q1(Q[1]),
      .Q0(Q[0]),
      .SO(SO_NV),
      .MATCH(MATCH),
      .RCREADY(RCREADY),

// for NEC TestBus ( Normal Mode Setting )
      .TEST(1'b0),
      .BUNRI(1'b0),
      .TBI21(1'b0),
      .TBI20(1'b0),
      .TBI19(1'b0),
      .TBI18(1'b0),
      .TBI17(1'b0),
      .TBI16(1'b0),
      .TBI15(1'b0),
      .TBI14(1'b0),
      .TBI13(1'b0),
      .TBI12(1'b0),
      .TBI11(1'b0),
      .TBI10(1'b0),
      .TBI9(1'b0),
      .TBI8(1'b0),
      .TBI7(1'b0),
      .TBI6(1'b0),
      .TBI5(1'b0),
      .TBI4(1'b0),
      .TBI3(1'b0),
      .TBI2(1'b0),
      .TBI1(1'b0),
      .TBI0(1'b0),
      .TBO4(),
      .TBO3(),
      .TBO2(),
      .TBO1(),
      .TBO0()
    );

endmodule