cc_add12.synscr
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#!/bin/csh -f
#
# ASICSYN
#
# Phil Gossett
# 6/26/94
#
vlsishell << EOF
set echo on
asicsyn
set autowrite false
set hdl verilog
#
# verilog sources
#
load [v]cc_add12
synthesize
write
set process slow
set temperature 40.0
set vddlevel 3.0
set maxdelay 14.0 * --> *
set maxrampdelay 3.0
set drive 0 gclk
show cellhier
report
qtv
show simparms
trace critical
exit
exit
exit
EOF
#