/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: io_cmd_dma.v,v 1.1 2002/03/28 00:26:13 berndt Exp $

module io_cmd_dma(clock, reset_l,
	cp0_enable, cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
   dma_start, dma_last, dma_grant, read_grant, cbuf_ready, cp0_cmd_select,
   cp0_address, cp0_write, cmd_ready, cmd_busy, pipe_busy, tmem_busy,
   start_gclk,
   dma_request, read_request, cbuf_write, xbus_dmem_select, cmd_read,
   cmd_address, flush, freeze, unfreeze,
   cp0_data, cbus_data);

`include "sp.vh"

parameter MAX_BLOCK = 4'd9;						// max dma transfer - 1
parameter COUNTER_SIZE = 24;						// DP performance counter size
parameter READ_DELAY = 8'd2;

input clock;											// system clock
input reset_l;											// system reset_l

input cp0_enable;										// enable cp0 tristate drivers
input cbus_read_enable;								// enable cbus tristate drivers
input cbus_write_enable;							// enable cbus read mux
input [CBUS_SELECT_SIZE-1:0] cbus_select;		// cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command;	// cbus data type
input dma_start;										// dbus DMA data start
input dma_last;										// dbus DMA data end
input dma_grant;										// DP DMA request granted
input read_grant;										// DP read request granted
input cbuf_ready;										// cbuf ready for write data
input cp0_cmd_select;								// DMA bank address
input [SP_REG_ADDRESS_SIZE-1:0] cp0_address; // DMA register address
input cp0_write;										// enable register write
input cmd_ready;										// DP CMDBUF read ready
input cmd_busy;										// DP CMDBUF is not empty
input pipe_busy;										// DP pipeline is active
input tmem_busy;										// DP TMEM is loading
input start_gclk;				  						// DP control

output dma_request;									// request a DMA cycle
output read_request;									// request a DMA cycle
output cbuf_write;									// command buffer write request
output xbus_dmem_select;							// DMEM dma requested
output cmd_read;										// DP DMEM read request
output [SP_MEM_ADDRESS_SIZE-1:0] cmd_address;// DP DMEM read address
output flush;											// DP control
output freeze;											// DP control
output unfreeze;										// DP control

inout [CP0_DATA_SIZE-1:0] cp0_data;				// CP0 data bus
inout [CBUS_DATA_SIZE-1:0] cbus_data;			// IO bus


// input/output registers
reg dma_request;
reg read_request;
reg cbuf_write;
reg xbus_dmem_select;
reg cmd_read;
reg flush;
reg freeze;
reg unfreeze;
reg [CBUS_COMMAND_SIZE-1:0] cbus_command_in;
reg [CBUS_DATA_SIZE-1:0] cbus_data_in;


// output pseudo registers
reg [CP0_DATA_SIZE-1:0] cp0_data_out;

// internal registers
reg xbus_dmem_dma;
reg xbus_dmem_dma_pl;
reg [SP_CMD_ADDRESS_SIZE-1:0] start_address;
reg [SP_CMD_ADDRESS_SIZE-1:0] end_address;
reg [SP_CMD_ADDRESS_SIZE-1:0] current_address;
reg [SP_CMD_ADDRESS_SIZE-1:0] last_address;
reg [SP_CMD_ADDRESS_SIZE-1:0] request_length;
reg [SP_CMD_LENGTH_SIZE-1:0] transfer_length;
reg [SP_REG_ADDRESS_SIZE-1:0] io_address;
reg start_valid, end_valid;
reg cbuf_write_a1, cbuf_write_a2, cbuf_write_a3;
reg [COUNTER_SIZE-1:0] clock_counter;
reg [COUNTER_SIZE-1:0] cmd_counter;
reg [COUNTER_SIZE-1:0] pipe_counter;
reg [COUNTER_SIZE-1:0] tmem_counter;
reg dma_busy;
reg start_gclk_d1;

// bus state machine
reg [1:0] bus_state;
parameter
	STATE_BUS_IDLE				= 0,
	STATE_BUS_WRITE			= 1,
	STATE_BUS_READ				= 2;


// DMA state machine
reg [3:0] dma_state;
parameter
	STATE_DMA_IDLE				= 0,
	STATE_DMA_DMEM_1			= 1,
	STATE_DMA_DMEM_2			= 2,
	STATE_DMA_WAIT				= 3,
	STATE_DMA_READ				= 4,
	STATE_DMA_DELAY_1			= 5,
	STATE_DMA_DELAY_2			= 6,
	STATE_DMA_DELAY_3			= 7,
	STATE_DMA_DELAY_4			= 8,
	STATE_DMA_DELAY_5			= 9;


// cbus tristate drivers
wire cmd_cp0_enable = cp0_enable & cp0_cmd_select;
cp0_driver cp0_driver_0(cp0_data_out, cmd_cp0_enable, cp0_data);
cbus_driver cbus_driver_0(cbus_data_in, cbus_write_enable, cbus_data);

// dmem read address
assign cmd_address = current_address;

// status return
wire [CBUS_DATA_SIZE-1:0] read_status;
assign read_status = {start_valid, end_valid, dma_busy, cbuf_ready, cmd_busy,
   pipe_busy, tmem_busy, start_gclk_d1, flush, freeze, xbus_dmem_dma};

// SP read mux
always @(cp0_address or start_address or end_address or current_address
  or read_status or clock_counter or cmd_counter  or pipe_counter
  or tmem_counter)
	case (cp0_address)
		SP_CMD_START_ADDRESS :
			cp0_data_out = start_address << DMA_OFFSET_SIZE;
		SP_CMD_END_ADDRESS :
			cp0_data_out = end_address << DMA_OFFSET_SIZE;
		SP_CMD_CURRENT_ADDRESS :
			cp0_data_out = current_address << DMA_OFFSET_SIZE;
		SP_CMD_STATUS :
			cp0_data_out = read_status;
		SP_CMD_CLOCK :
			cp0_data_out = clock_counter;
		SP_CMD_BUSY :
			cp0_data_out = cmd_counter;
		SP_CMD_PIPE_BUSY :
			cp0_data_out = pipe_counter;
		SP_CMD_TMEM_BUSY :
			cp0_data_out = tmem_counter;
		default :
			cp0_data_out = 'bx;
		endcase


always @(posedge clock) begin : pipeline_block
	reg [CBUS_DATA_SIZE-1:0] cbus_data_out;

	request_length <= last_address + ~current_address;
	cbus_command_in <= cbus_command;
	start_gclk_d1 <= start_gclk;

	case (cbus_select)
		CBUS_ADDRESS_SELECT :
		  cbus_data_out = current_address << DMA_OFFSET_SIZE;
		CBUS_LENGTH_SELECT :
		  cbus_data_out
			 = {BUS_DEVICE_DP_CMD, READ_DELAY, HIGH, transfer_length, ~3'b0};
		CBUS_DATA_SELECT :
			case (io_address)
				SP_CMD_START_ADDRESS :
					cbus_data_out = start_address << DMA_OFFSET_SIZE;
				SP_CMD_END_ADDRESS :
					cbus_data_out = end_address << DMA_OFFSET_SIZE;
				SP_CMD_CURRENT_ADDRESS :
					cbus_data_out = current_address << DMA_OFFSET_SIZE;
				SP_CMD_STATUS :
					cbus_data_out = read_status;
				SP_CMD_CLOCK :
					cbus_data_out = clock_counter;
				SP_CMD_BUSY :
					cbus_data_out = cmd_counter;
				SP_CMD_PIPE_BUSY :
					cbus_data_out = pipe_counter;
				SP_CMD_TMEM_BUSY :
					cbus_data_out = tmem_counter;
				default :
				  cbus_data_out = 32'bx;
				endcase
		default :
		  cbus_data_out = 32'bx;
		endcase

	cbus_data_in <= cbus_read_enable ? cbus_data : cbus_data_out;
	end


always @(posedge clock or negedge reset_l) begin
	if (!reset_l) begin
		// resetable registers
		dma_request <= LOW;
		read_request <= LOW;
		cbuf_write <= LOW;
		xbus_dmem_select <= LOW;
		cmd_read <= LOW;
		flush <= LOW;
		freeze <= LOW;
		unfreeze <= LOW;

		xbus_dmem_dma <= LOW;
		xbus_dmem_dma_pl <= LOW;
		current_address <= 0;
		last_address <= 0;
		start_valid <= LOW;
		end_valid <= LOW;
		cbuf_write_a1 <= LOW;
		cbuf_write_a2 <= LOW;
		cbuf_write_a3 <= LOW;

		dma_state <= STATE_DMA_IDLE;
		bus_state <= STATE_BUS_IDLE;

		// non-resetable registers
		start_address <= 'bx;
		end_address <= 'bx;
		transfer_length <= 'bx;
		io_address <= 'bx;
		clock_counter <= 'bx;
		cmd_counter <= 'bx;
		pipe_counter <= 'bx;
		tmem_counter <= 'bx;
		dma_busy <= 'bx;
		end
	else begin : main_loop
		reg cmd_selected; 
		reg load_current_address;
		reg increment_current_address;
		reg dma_idle;
		reg next_cmd_read;
		reg next_dma_cbuf_write;
		reg next_dmem_cbuf_write;
		reg next_unfreeze;
		reg next_read_request;
		reg load_transfer_length;
		reg decrement_transfer_length;
		reg clear_clock_counter;
		reg clear_cmd_counter;
		reg clear_pipe_counter;
		reg clear_tmem_counter;
		reg set_flush, clear_flush;
		reg set_freeze, clear_freeze;
		reg set_xbus_dmem_dma, clear_xbus_dmem_dma;
		reg [SP_REG_ADDRESS_SIZE-1:0] reg_address;
		reg [SP_REG_DATA_SIZE-1:0] reg_data;
		reg dma_reg_write;
		reg io_status_reg_write;
		reg cp0_status_reg_write;

		cmd_selected = (cbus_data_in & BUS_ADDRESS_MASK) == BUS_ADDRESS_CMD;
		load_current_address = LOW;
		increment_current_address = LOW;
		dma_idle = current_address == last_address;
		next_cmd_read = LOW;
		next_dma_cbuf_write = LOW;
		next_dmem_cbuf_write = LOW;
		next_unfreeze = LOW;
		next_read_request = LOW;
		load_transfer_length = LOW;
		decrement_transfer_length = LOW;
		set_flush = LOW;
		clear_flush = LOW;
		set_freeze = LOW;
		clear_freeze = LOW;
		set_xbus_dmem_dma = LOW;
		clear_xbus_dmem_dma = LOW;
		clear_clock_counter = LOW;
		clear_cmd_counter = LOW;
		clear_pipe_counter = LOW;
		clear_tmem_counter = LOW;

		reg_address = cp0_address;
		reg_data = cp0_data;
		dma_reg_write = LOW;
		io_status_reg_write = LOW;
		cp0_status_reg_write = LOW;
		if (cp0_write && cp0_cmd_select) begin
			if (cp0_address[SP_REG_ADDRESS_SIZE-1:0] == SP_CMD_STATUS) begin
				cp0_status_reg_write = HIGH;
				end
			else begin
				dma_reg_write = HIGH;
				end
			end

		// CBUS accesses
		case (bus_state)
			STATE_BUS_IDLE : begin
				case (cbus_command_in)
					CBUS_WRITE_COMMAND : begin
						if (cmd_selected) begin
							io_address <= cbus_data_in >> IO_OFFSET_SIZE;
							bus_state <= STATE_BUS_WRITE;
							end
						else begin
							bus_state <= STATE_BUS_IDLE;
							end
						end

					CBUS_READ_COMMAND : begin
						if (cmd_selected) begin
							next_read_request = HIGH;
							io_address <= cbus_data_in >> IO_OFFSET_SIZE;
							bus_state <= STATE_BUS_READ;
							end
						else begin
							bus_state <= STATE_BUS_IDLE;
							end
						end

					default : begin
						bus_state <= STATE_BUS_IDLE;
						end
					endcase
				end

			STATE_BUS_WRITE : begin
				if (io_address[SP_REG_ADDRESS_SIZE-1:0] == SP_CMD_STATUS) begin
					io_status_reg_write = HIGH;
					end
				else begin
					reg_address = io_address;
					reg_data = cbus_data_in;
					dma_reg_write = HIGH;
					end
				bus_state <= STATE_BUS_IDLE;
				end

			STATE_BUS_READ : begin
				if (read_grant) begin
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					next_read_request = HIGH;
					bus_state <= STATE_BUS_READ;
					end
				end

			default : begin
				bus_state <= 'bx;
				end
			endcase


		if (dma_reg_write) begin
			// write to a DMA register
			case (reg_address)
				SP_CMD_START_ADDRESS : begin
					if (start_valid) begin
						$display( "%m: Panic!  DP start address already valid - %h",
						  reg_data);
						$finish;
						end
					else begin
						start_valid <= HIGH;
						start_address <= reg_data >> DMA_OFFSET_SIZE;
						end
					end

				SP_CMD_END_ADDRESS : begin
					next_unfreeze = HIGH;
					end_address <= reg_data >> DMA_OFFSET_SIZE;
					if (start_valid) begin
						if (dma_idle) begin
							// forward the value straight to the last register
							load_current_address = HIGH;
							start_valid <= LOW;
							end_valid <= LOW;
							last_address <= reg_data >> DMA_OFFSET_SIZE;
							end
						else begin
							end_valid <= HIGH;
							end
						end
					else begin
						// forward the value straight to the last register
						last_address <= reg_data >> DMA_OFFSET_SIZE;
						end
					end

				default : begin
					$display ("Panic!  Illegal CMD register write - <%h>",
					   reg_address);
					$finish;

					if (dma_idle && end_valid) begin
						load_current_address = HIGH;
						start_valid <= LOW;
						end_valid <= LOW;
						last_address <= end_address;
						end
					end
				endcase
			end
		else 	if (dma_idle && end_valid) begin
			load_current_address = HIGH;
			start_valid <= LOW;
			end_valid <= LOW;
			last_address <= end_address;
			end


		// IO status register write
		if (io_status_reg_write) begin : io_status_block
			reg next_clear_clock_counter;
			reg next_clear_cmd_counter;
			reg next_clear_pipe_counter;
			reg next_clear_tmem_counter;
			reg next_set_flush, next_clear_flush;
			reg next_set_freeze, next_clear_freeze;
			reg next_set_xbus_dmem_dma, next_clear_xbus_dmem_dma;

			{
			  next_clear_clock_counter,
			  next_clear_cmd_counter,
			  next_clear_pipe_counter,
			  next_clear_tmem_counter,
			  next_set_flush, next_clear_flush,
			  next_set_freeze, next_clear_freeze,
			  next_set_xbus_dmem_dma, next_clear_xbus_dmem_dma
			} = cbus_data_in;

			clear_clock_counter = next_clear_clock_counter || clear_clock_counter;
			clear_cmd_counter = next_clear_cmd_counter || clear_cmd_counter;
			clear_pipe_counter = next_clear_pipe_counter || clear_pipe_counter;
			clear_tmem_counter = next_clear_tmem_counter || clear_tmem_counter;

			set_flush = next_set_flush || set_flush;
			clear_flush = next_clear_flush || clear_flush;

			set_freeze = next_set_freeze || set_freeze;
			clear_freeze = next_clear_freeze || clear_freeze;

			set_xbus_dmem_dma = next_set_xbus_dmem_dma || set_xbus_dmem_dma;
			clear_xbus_dmem_dma = next_clear_xbus_dmem_dma || clear_xbus_dmem_dma;
			end


		// CP0 status register write
		if (cp0_status_reg_write) begin : cp0_status_block
			reg next_clear_clock_counter;
			reg next_clear_cmd_counter;
			reg next_clear_pipe_counter;
			reg next_clear_tmem_counter;
			reg next_set_flush, next_clear_flush;
			reg next_set_freeze, next_clear_freeze;
			reg next_set_xbus_dmem_dma, next_clear_xbus_dmem_dma;

			{
			  next_clear_clock_counter,
			  next_clear_cmd_counter,
			  next_clear_pipe_counter,
			  next_clear_tmem_counter,
			  next_set_flush, next_clear_flush,
			  next_set_freeze, next_clear_freeze,
			  next_set_xbus_dmem_dma, next_clear_xbus_dmem_dma
			} = cp0_data;

			clear_clock_counter = next_clear_clock_counter || clear_clock_counter;
			clear_cmd_counter = next_clear_cmd_counter || clear_cmd_counter;
			clear_pipe_counter = next_clear_pipe_counter || clear_pipe_counter;
			clear_tmem_counter = next_clear_tmem_counter || clear_tmem_counter;

			set_flush = next_set_flush || set_flush;
			clear_flush = next_clear_flush || clear_flush;

			set_freeze = next_set_freeze || set_freeze;
			clear_freeze = next_clear_freeze || clear_freeze;

			set_xbus_dmem_dma = next_set_xbus_dmem_dma || set_xbus_dmem_dma;
			clear_xbus_dmem_dma = next_clear_xbus_dmem_dma || clear_xbus_dmem_dma;
			end


		// transfer state machine
		case (dma_state)
			STATE_DMA_IDLE : begin
				load_transfer_length = HIGH;

				if (!dma_idle && cbuf_ready) begin
					if (xbus_dmem_dma_pl) begin
						xbus_dmem_select <= HIGH;
						dma_state <= STATE_DMA_DMEM_1;
						end
					else begin
						// we will be in this state for at least three cycles,
						// so transfer_length will be valid before it is needed
						xbus_dmem_select <= LOW;
						if (dma_grant) begin
							dma_request <= LOW;
							dma_state <= STATE_DMA_WAIT;
							end
						else begin
							dma_request <= HIGH;
							dma_state <= STATE_DMA_IDLE;
							end
						end
					end
				else begin
					dma_request <= LOW;
					dma_state <= STATE_DMA_IDLE;
					end
				end

			STATE_DMA_DMEM_1 : begin
				// wait a cycle for transfer_length pipeline
				load_transfer_length = HIGH;
				next_cmd_read = HIGH;
				dma_state <= STATE_DMA_DMEM_2;
				end

			STATE_DMA_DMEM_2 : begin
				if (cmd_ready) begin
					next_dmem_cbuf_write = HIGH;
					increment_current_address = HIGH;
					decrement_transfer_length = HIGH;
					end

				if (transfer_length) begin
					next_cmd_read = HIGH;
					dma_state <= STATE_DMA_DMEM_2;
					end
				else begin
					dma_state <= STATE_DMA_DELAY_5;
					end
				end

			STATE_DMA_WAIT : begin
				if (dma_start) begin
					increment_current_address = HIGH;
					next_dma_cbuf_write = HIGH;
					if (dma_last) begin
						dma_state <= STATE_DMA_DELAY_2;
						end
					else begin
						dma_state <= STATE_DMA_READ;
						end
					end
				else begin
					dma_state <= STATE_DMA_WAIT;
					end
				end

			STATE_DMA_READ : begin
				increment_current_address = HIGH;
				next_dma_cbuf_write = HIGH;

				if (dma_last) begin
					dma_state <= STATE_DMA_DELAY_2;
					end
				else begin
					dma_state <= STATE_DMA_READ;
					end
				end

			STATE_DMA_DELAY_5 : begin
				dma_state <= STATE_DMA_DELAY_4;
				end

			STATE_DMA_DELAY_4 : begin
				dma_state <= STATE_DMA_DELAY_3;
				end

			STATE_DMA_DELAY_3 : begin
				dma_state <= STATE_DMA_DELAY_2;
				end

			STATE_DMA_DELAY_2 : begin
				dma_state <= STATE_DMA_DELAY_1;
				end

			STATE_DMA_DELAY_1 : begin
				dma_state <= STATE_DMA_IDLE;
				end

			default : begin
				dma_state <= 'bx;
				end
			endcase

		if (load_current_address) begin
			xbus_dmem_dma_pl <= xbus_dmem_dma;
			current_address <= start_address;
			end
		else if (increment_current_address) begin
			current_address <= current_address + 1;
			end

		if (load_transfer_length) begin : transfer_loop
			// caluculate the length of the DMA, assuming a 2K byte page
			// boundary and a MAX_BLOCK block boundary
			reg [7:0] max_page;
			max_page = ~current_address;
			if (request_length > MAX_BLOCK) begin
				if (MAX_BLOCK > max_page) begin
					transfer_length <= max_page;
					end
				else begin
					transfer_length <= MAX_BLOCK;
					end
				end
			else begin
				if (request_length > max_page) begin
					transfer_length <= max_page;
					end
				else begin
					transfer_length <= request_length;
					end
				end
			end
		else if (decrement_transfer_length) begin
			transfer_length <= transfer_length - 1;
			end

		unfreeze <= next_unfreeze;

		// DP performance registers
		if (clear_clock_counter) begin
			clock_counter <= 0;
			end
		else begin
			clock_counter <= clock_counter + 1;
			end

		if (clear_cmd_counter) begin
			cmd_counter <= 0;
			end
		else begin
			cmd_counter <= cmd_counter + cmd_busy;
			end

		if (clear_pipe_counter) begin
			pipe_counter <= 0;
			end
		else begin
			pipe_counter <= pipe_counter + start_gclk_d1;
			end

		if (clear_tmem_counter) begin
			tmem_counter <= 0;
			end
		else begin
			tmem_counter <= tmem_counter + tmem_busy;
			end

		case ({set_freeze, clear_freeze})
			2'b10 : freeze <= HIGH;
			2'b01 : freeze <= LOW;
			endcase

		case ({set_flush, clear_flush})
			2'b10 : flush <= HIGH;
			2'b01 : flush <= LOW;
			endcase

		case ({set_xbus_dmem_dma, clear_xbus_dmem_dma})
			2'b10 : xbus_dmem_dma <= HIGH;
			2'b01 : xbus_dmem_dma <= LOW;
			endcase

		cbuf_write_a3 <= next_dmem_cbuf_write;
		cbuf_write_a2 <= cbuf_write_a3;
		cbuf_write_a1 <= cbuf_write_a2;
		cbuf_write <= next_dma_cbuf_write | cbuf_write_a1;
		cmd_read <= next_cmd_read;
		read_request <= next_read_request;
		dma_busy <= !dma_idle || end_valid;
		end
	end
endmodule