rsp.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: rsp.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
// rsp.v: the whole shebang
`timescale 1ns / 10ps
module rsp(clk, reset_l, iddq_test,
sp_cbus_read_enable, sp_cbus_write_enable, mem_cbus_write_enable,
cmd_cbus_read_enable, cmd_cbus_write_enable,
cbus_select, cbus_command,
dma_start, dma_last, sp_dma_grant, sp_read_grant, cmd_dma_grant,
cmd_read_grant, sp_dbus_read_enable, sp_dbus_write_enable, cbuf_ready,
cmd_busy, pipe_busy, tmem_busy,
sp_dma_request, sp_read_request, mem_read_request,
cmd_dma_request, cmd_read_request, flush, freeze, unfreeze, frozen,
sp_interrupt, cbuf_write, xbus_data, cbus_data, dbus_data);
input clk;
input reset_l;
input iddq_test;
// DMA-related IO
input frozen;
input sp_cbus_read_enable;
input sp_cbus_write_enable;
input mem_cbus_write_enable; // *** Use for CPU read of mems
input cmd_cbus_read_enable;
input cmd_cbus_write_enable;
input [1:0] cbus_select;
input [2:0] cbus_command;
input dma_start;
input dma_last;
input sp_dma_grant;
input sp_read_grant;
input cmd_dma_grant;
input cmd_read_grant;
input sp_dbus_read_enable;
input sp_dbus_write_enable;
input cbuf_ready;
input cmd_busy; // DP CMDBUF is not empty
input pipe_busy; // DP pipeline is active
input tmem_busy; // DP TMEM is loading
inout [31:0] cbus_data;
inout [63:0] dbus_data;
output sp_dma_request;
output sp_read_request;
output mem_read_request;
output cmd_dma_request;
output cmd_read_request;
output cbuf_write;
output flush;
output freeze;
output unfreeze;
output sp_interrupt;
output [63:0] xbus_data;
wire [63:0] rd_inst; // imem output
wire [63:0] rd_inst_buf; // imem output buffered in su
wire [11:0] branch_or_addr;
wire [11:3] final_pc; // IF stage
wire [11:2] pc;
wire set_broke;
wire imem_dma_cycle;
wire imem_web;
wire [3:0] rd_base;
wire ls_drive_rd_base;
wire [3:0] rd_offset;
wire [3:0] rd_elem_num;
wire vu_ex_load;
wire vu_ex_store;
wire su_ex_load;
wire su_ex_store;
wire ex_mfc2;
wire ex_mtc2;
wire ex_cfc2;
wire ex_mfc0;
wire [11:0] vu_rd_ld_dec_k;
wire [11:0] vu_rd_st_dec_k;
wire [15:0] vu_bwe;
wire [127:0] ls_data;
wire df_ls_drive_ls_in_wb;
wire df_pass_thru;
wire chip_sel; // suctl -> ls, active high
wire [127:0] df_datain;
wire df_chip_sel_l;
wire [15:0] df_wen_l; // write enable, active low
wire [11:0] df_addr_low;
wire [11:0] df_addr_high;
wire [127:0] dmem_dataout;
wire [63:0] dmem_rd_data;
wire [63:0] mem_write_data;
wire ex_su_byte_ls;
wire ex_su_half_ls;
wire ex_su_uns_ls;
wire imem_csb;
wire su_nop_debug;
wire vu_nop_debug;
wire break_inst_debug;
// SU ctl to VU
wire vu_comp;
wire vu_comp_k;
wire [5:0] vu_func;
wire ex_ctc2_vc0;
wire ex_ctc2_vc1;
wire ex_ctc2_vc2;
wire vu_rd_store_type_k;
wire [3:0] vu_elem;
wire [4:0] vu_ld_addr;
wire [4:0] vu_st_addr;
wire [4:0] vu_st_xpose_addr;
wire [4:0] vs; // RD: reg num for vs read
wire [4:0] vt; // RD: reg num for vt read
wire [4:0] acc_wr_reg; // DF: reg num for datapath writeback
wire acc_wr_en; // DF: write en for dp results
wire store_xpose_rd;
wire load_xpose_wb;
wire rd_cfvc0_k;
wire rd_cfvc1_k;
wire rd_cfvc2_k;
// DMA-related Wires
wire halt;
wire single_step;
wire [11:2] pc_data_in; // from cp0
wire pc_in_wr_en;
wire [31:0] cp0_data; // CP0 data to su
wire [3:0] cp0_address;
wire cp0_write; // CTC2, EX
wire cp0_enable; // CFC2, EX
wire dma_imem_select;
wire [3:0] dma_wen;
wire [11:3] dma_address;
wire ex_dma_rd_to_dm;
wire ex_dma_dm_to_rd;
wire dma_rd_to_dm;
wire dma_dm_to_rd;
wire [1:0] dma_mask;
wire io_read_select;
wire io_write_select;
wire mem_load;
wire io_load;
wire xbus_dmem_select;
wire cmd_read;
wire cmd_ready;
wire [8:0] cmd_address;
wire dma_busy; // In case we want CP0 branch.
wire [63:0] imem_datain;
wire bist_done;
wire [3:0] bist_fail;
wire bist_go;
wire bist_check;
wire debug_df_dma_rd_to_dm;
su su (
.clk (clk),
.reset_l (reset_l),
.halt (halt),
.single_step (single_step),
.pc_in_wr_en (pc_in_wr_en),
.pc_data_in (pc_data_in),
.dma_dm_to_rd (dma_dm_to_rd),
.dma_rd_to_dm (dma_rd_to_dm),
.dma_imem_select (dma_imem_select),
.rd_inst (rd_inst),
.rd_base (rd_base),
.ls_drive_rd_base (ls_drive_rd_base),
.rd_offset (rd_offset),
.rd_elem_num (rd_elem_num),
.chip_sel (chip_sel),
.su_ex_store (su_ex_store),
.su_ex_load (su_ex_load),
.vu_ex_store (vu_ex_store),
.vu_ex_load (vu_ex_load),
.ex_mfc2 (ex_mfc2),
.ex_mtc2 (ex_mtc2),
.ex_cfc2 (ex_cfc2),
.ex_mfc0 (ex_mfc0),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.ex_su_uns_ls (ex_su_uns_ls),
.df_ls_drive_ls_in_wb (df_ls_drive_ls_in_wb),
.df_pass_thru (df_pass_thru),
.imem_dma_cycle (imem_dma_cycle),
.su_nop_debug (su_nop_debug),
.vu_nop_debug (vu_nop_debug),
.pc (pc),
.branch_or_addr (branch_or_addr[11:0]),
.set_broke (set_broke),
.vu_rd_ld_dec_k (vu_rd_ld_dec_k),
.vu_rd_st_dec_k (vu_rd_st_dec_k),
.break_inst_debug (break_inst_debug),
.ls_data (ls_data[127:96]),
// VU controls:
.vu_comp (vu_comp),
.vu_comp_k (vu_comp_k),
.vu_func (vu_func),
.ex_ctc2_vc0 (ex_ctc2_vc0),
.ex_ctc2_vc1 (ex_ctc2_vc1),
.ex_ctc2_vc2 (ex_ctc2_vc2),
.vu_rd_store_type_k (vu_rd_store_type_k),
.vu_elem (vu_elem),
.vu_ld_addr (vu_ld_addr),
.vu_st_addr (vu_st_addr),
.vu_st_xpose_addr (vu_st_xpose_addr),
.vs (vs),
.vt (vt),
.acc_wr_reg (acc_wr_reg),
.acc_wr_en (acc_wr_en),
.store_xpose_rd (store_xpose_rd),
.load_xpose_wb (load_xpose_wb),
.rd_cfvc0_k (rd_cfvc0_k),
.rd_cfvc1_k (rd_cfvc1_k),
.rd_cfvc2_k (rd_cfvc2_k),
.cp0_address (cp0_address),
.cp0_write (cp0_write),
.cp0_enable (cp0_enable),
.rd_inst_buf (rd_inst_buf)
);
vu vu ( // VU inputs:
.clk (clk),
.reset_l (reset_l),
.su_storeinst_rd (vu_rd_store_type_k), // store from VU
.su_instvld_rd (vu_comp), // valid CP2 inst
.su_instvldk_rd (vu_comp_k), // valid CP2 inst
.su_vseqone_rd (vs[0]),
.su_instelem_rd (vu_elem), // inst[elem]
.su_instfunc_rd (vu_func), // inst[func]
.su_rdcryout_rd (rd_cfvc0_k), // read VCO (vc0)
.su_rdcmpcd_rd (rd_cfvc1_k), // read VCC (vc1)
.su_rdcmpcdad_rd (rd_cfvc2_k), // read VCE (vc2)
.su_wrcryout_wb (ex_ctc2_vc0), // write VCO (vc0)
.su_wrcmpcd_wb (ex_ctc2_vc1), // write VCC (vc1)
.su_wrcmpcdad_wb (ex_ctc2_vc2), // write VCE (vc2)
.su_ld_rnum_ac (vu_ld_addr),
.su_st_rnum_rd (vu_st_addr),
.su_xp_rnum_rd (vu_st_xpose_addr),
.su_vs_addr_rd (vs), // reg num for vs read
.su_vt_addr_rd (vt), // reg num for vt read
.su_vd_addr_ac (acc_wr_reg), // reg num for dp writeback
.su_wbv_wr_en_ac (acc_wr_en), // write en for dp results
.su_bwe_ac (vu_bwe), // load port byte wr en
.su_st_xposeop_rd (store_xpose_rd),
.su_ld_xposeop_wb (load_xpose_wb),
.su_data_to_from (ls_data) // 128 bit load/store bus
);
dmemx2 dmemx2(
.clk (clk),
.df_chip_sel_l (iddq_test),
.df_wen_l (df_wen_l),
.df_addr_low (df_addr_low[11:4]),
.df_addr_high (df_addr_high[11:4]),
.df_datain (df_datain),
.dmem_dataout (dmem_dataout)
);
ls ls(
.clk (clk),
.reset_l (reset_l),
.iddq_test (iddq_test),
.halt (halt),
.rd_base (rd_base),
.ls_drive_rd_base (ls_drive_rd_base),
.rd_offset (rd_offset),
.rd_elem_num (rd_elem_num),
.address (branch_or_addr[11:0]),
.df_ls_drive_ls_in_wb (df_ls_drive_ls_in_wb),
.df_pass_thru (df_pass_thru),
.vu_ex_load (vu_ex_load),
.vu_ex_store (vu_ex_store),
.su_ex_store (su_ex_store),
.su_ex_load (su_ex_load),
.ex_mfc2 (ex_mfc2),
.ex_mtc2 (ex_mtc2),
.ex_cfc2 (ex_cfc2),
.cp0_write (cp0_write),
.vu_rd_ld_dec_k (vu_rd_ld_dec_k),
.vu_rd_st_dec_k (vu_rd_st_dec_k),
.chip_sel (chip_sel),
.ex_su_byte_ls (ex_su_byte_ls),
.ex_su_half_ls (ex_su_half_ls),
.ex_su_uns_ls (ex_su_uns_ls),
.ex_dma_rd_to_dm (ex_dma_rd_to_dm),
.ex_dma_dm_to_rd (ex_dma_dm_to_rd),
.dma_wen (dma_wen),
.dma_address (dma_address),
.dmem_dataout (dmem_dataout),
.mem_write_data (mem_write_data),
.ex_mfc0 (ex_mfc0),
.pc (pc),
.vu_bwe (vu_bwe[15:0]),
.df_chip_sel_l (df_chip_sel_l),
.df_wen_l (df_wen_l),
.df_addr_low (df_addr_low[11:0]),
.df_addr_high (df_addr_high[11:0]),
.dmem_rd_data (dmem_rd_data),
.df_datain (df_datain[127:0]),
.debug_df_dma_rd_to_dm (debug_df_dma_rd_to_dm),
.ls_data (ls_data),
.cp0_data (cp0_data)
);
rspbusses rspbusses(
.clk (clk),
.reset_l (reset_l),
.iddq_test (iddq_test),
.cbus_write_enable (mem_cbus_write_enable),
.dbus_read_enable (sp_dbus_read_enable),
.dbus_write_enable (sp_dbus_write_enable),
.io_load (io_load),
.io_read_select (io_read_select),
.io_write_select (io_write_select),
.dma_imem_select (dma_imem_select),
.xbus_dmem_select (xbus_dmem_select),
.dma_dm_to_rd (dma_dm_to_rd),
.dma_rd_to_dm (dma_rd_to_dm),
.dma_address (dma_address),
.dma_mask (dma_mask),
.mem_load (mem_load),
.im_to_rd_data (rd_inst_buf),
.dmem_rd_data (dmem_rd_data),
.pc (pc),
.final_pc (final_pc),
.imem_dma_cycle (imem_dma_cycle),
.bist_go (bist_go),
.bist_check (bist_check),
.cbus_data (cbus_data),
.dbus_data (dbus_data),
.xbus_data (xbus_data),
.ex_dma_rd_to_dm (ex_dma_rd_to_dm),
.ex_dma_dm_to_rd (ex_dma_dm_to_rd),
.mem_write_data (mem_write_data),
.imem_datain (imem_datain),
.imem_web (imem_web),
.imem_csb (imem_csb),
.dma_wen (dma_wen),
.bist_done (bist_done),
.bist_fail (bist_fail)
);
imem imem(
.di (imem_datain),
.a (final_pc),
.csb (iddq_test),
.pcg (clk),
.web (imem_web),
.dout (rd_inst)
);
io_mem_dma io_mem_dma (
.clock (clk),
.reset_l (reset_l),
.cp0_enable (cp0_enable),
.cbus_read_enable (sp_cbus_read_enable),
.cbus_write_enable (sp_cbus_write_enable),
.cbus_select (cbus_select),
.cbus_command (cbus_command),
.dma_start (dma_start),
.dma_last (dma_last),
.dma_grant (sp_dma_grant),
.read_grant (sp_read_grant),
.cp0_cmd_select (cp0_address[3]),
.cp0_address (cp0_address[2:0]),
.cp0_write (cp0_write),
.cp0_read (ex_mfc0),
.set_broke (set_broke),
.cmd_read (cmd_read),
.cmd_address (cmd_address),
.bist_done (bist_done),
.bist_fail (bist_fail),
.dma_request (sp_dma_request),
.reg_read_request (sp_read_request),
.mem_read_request (mem_read_request),
.imem_select (dma_imem_select),
.mem_address (dma_address),
.mem_read (dma_dm_to_rd),
.mem_write (dma_rd_to_dm),
.mem_mask (dma_mask),
.halt (halt),
.single_step (single_step),
.dma_busy (dma_busy),
.cmd_ready (cmd_ready),
.pc_write (pc_in_wr_en),
.pc_data (pc_data_in),
.io_read_select (io_read_select),
.io_write_select (io_write_select),
.mem_load (mem_load),
.io_load (io_load),
.interrupt (sp_interrupt),
.bist_go (bist_go),
.bist_check (bist_check),
.cp0_data (cp0_data),
.cbus_data (cbus_data)
);
io_cmd_dma io_cmd_dma (
.clock (clk),
.reset_l (reset_l),
.start_gclk (frozen),
.cp0_enable (cp0_enable),
.cbus_read_enable (cmd_cbus_read_enable),
.cbus_write_enable (cmd_cbus_write_enable),
.cbus_select (cbus_select),
.cbus_command (cbus_command),
.dma_start (dma_start),
.dma_last (dma_last),
.dma_grant (cmd_dma_grant),
.read_grant (cmd_read_grant),
.cbuf_ready (cbuf_ready),
.cp0_cmd_select (cp0_address[3]),
.cp0_address (cp0_address[2:0]),
.cp0_write (cp0_write),
.cmd_ready (cmd_ready),
.cmd_busy (cmd_busy),
.pipe_busy (pipe_busy),
.tmem_busy (tmem_busy),
.dma_request (cmd_dma_request),
.read_request (cmd_read_request),
.cbuf_write (cbuf_write),
.xbus_dmem_select (xbus_dmem_select),
.cmd_read (cmd_read),
.cmd_address (cmd_address),
.flush (flush),
.freeze (freeze),
.unfreeze (unfreeze),
.cp0_data (cp0_data),
.cbus_data (cbus_data)
);
endmodule