testckt_pads.v
1.64 KB
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module testckt_pads(clk,dir_in,data);
parameter half_clock = 15 ;
input clk, dir_in;
inout data;
tri data;
reg out_data;
reg [9:0] input_word;
reg [9:0] ser_out;
reg [9:0] q;
reg riosc_clk;
reg counter_out;
wire sclk, enable ;
wire tclk, out_bit,tdata;
wire #1 tload ;
always
begin
riosc_clk = 0 ;
while (1) begin
#half_clock riosc_clk = !(riosc_clk&enable);
end
end
assign sclk = clk & dir_in ;
assign enable = clk & !(dir_in) ;
assign data = (dir_in == 1'b1) ? 1'bz : out_bit;
assign tclk = (dir_in ^ clk) ;
assign tdata = !ser_out[9] ;
assign out_bit = (clk == 1'b1) ? out_data: tdata ;
assign tload = clk ;
initial
if (enable == 1'b0) begin
counter_out = 1'b0 ;
end
always @ (enable or sclk) begin
if (enable == 1'b0) begin
#1 q = input_word ;
counter_out = 1'b0;
end
end
always @ (posedge sclk)
begin
input_word = {input_word[8:0],data} ;
end
always @ (posedge tclk)
begin
if (tload == 1'b1) ser_out = ~q ;
else ser_out = {ser_out[8:0], 1'b1} ;
end
always @ (negedge riosc_clk) if (enable) q[0] = !q[0];
always @ (negedge q[0]) if (enable) q[1] = !q[1];
always @ (negedge q[1]) if (enable) q[2] = !q[2];
always @ (negedge q[2]) if (enable) q[3] = !q[3];
always @ (negedge q[3]) if (enable) q[4] = !q[4];
always @ (negedge q[4]) if (enable) q[5] = !q[5];
always @ (negedge q[5]) if (enable) q[6] = !q[6];
always @ (negedge q[6]) if (enable) q[7] = !q[7];
always @ (negedge q[7]) if (enable) q[8] = !q[8];
always @ (negedge q[8]) if (enable) q[9] = !q[9];
always @ (negedge q[9]) if (enable) counter_out = 1'b1 ;
always @ (negedge enable) out_data = counter_out ;
endmodule