/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vurfctl.v,v 1.1 2002/03/28 00:26:14 berndt Exp $

/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vurfctl						*
*	Description:	Control for new 32 word by 128 "custom" 5 port	*
*			register file.					*
*									*
*			This version is for the standard cell		*
*			implementation of the datapath.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		4/6/95						*
*									*
*************************************************************************
*/

// vurfctl.v: 	RSP vector unit top level - instantiation of datapath and control

`timescale 1ns / 10ps

module	vurfctl	(	
			clk,
			reset_l, 
			su_instelem_rd,
			su_bwe_ac,
			su_vd_addr_ac,
			su_ld_rnum_ac,
			su_xposeop_rdac,
			vct_instvld_ac,
			su_wbv_wr_en_ac,
			vct_dvtypop_ac,
			vct_vs_addr_ac,

			su_sclrdatasl_rd,
			su_qrtdatasl_rd,
			su_hlfdatasl_rd,
			su_whldatasl_rd,

			su_vd_addr_wb,
			su_ld_rnum_wb,

			vct_wbv_wr_en_wb,
			su_bwe_wb

		) ;


	input	clk;				/* vu clock */
	input	reset_l;			/* vu active low reset */
	input   [3:0]	su_instelem_rd;		/* element field of instruction */
	input	[15:0]	su_bwe_ac;		/* load port byte write enable */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */
	input	[4:0]	su_ld_rnum_ac;		/* register number for load */
	input	su_xposeop_rdac;		/* transpose op for rd stage (store) */
	input	vct_instvld_ac;			/* valid CP2 instruction for vu */
	input	su_wbv_wr_en_ac;		/* write enable for datapath results */
	input	vct_dvtypop_ac;			/* divide op in ac stage from VU */
	input	[2:0]	vct_vs_addr_ac;		/* vs address in ac stage from VU */

	output	[3:0]	su_sclrdatasl_rd;	/* selcts for vector, quarter, half or whole scalar data */
	output	[1:0]	su_qrtdatasl_rd;	/* selects for scalar quarter data */
	output	[3:0]	su_hlfdatasl_rd;	/* selects for scalar half data */
	output	[7:0]	su_whldatasl_rd;	/* selects for scalar whole data */

	output	[4:0]	su_vd_addr_wb;		/* register number for datapath writeback */
	output	[4:0]	su_ld_rnum_wb;		/* register number for load */

	output	[7:0]	vct_wbv_wr_en_wb;	/* short word write enable for datapath results */
	output	[15:0]	su_bwe_wb;		/* load port byte write enable */

/*
*	Decode the element field to produce selects for quarter tristate buffers 
*	selecting between even and odd slices.
*/

	assign	su_qrtdatasl_rd[0] =	!su_instelem_rd[0] ;

	assign	su_qrtdatasl_rd[1] =	su_instelem_rd[0] ;

/*
*	Decode the element field to produce selects for half tristate buffers 
*	selecting between even and odd slices.
*/

	assign	su_hlfdatasl_rd[0] =	( su_instelem_rd[1:0] == 2'b00 ) ;

	assign	su_hlfdatasl_rd[1] =	( su_instelem_rd[1:0] == 2'b01 ) ;

	assign	su_hlfdatasl_rd[2] =	( su_instelem_rd[1:0] == 2'b10 ) ;

	assign	su_hlfdatasl_rd[3] =	( su_instelem_rd[1:0] == 2'b11 ) ;

/*
*	Decode the element field to produce selects for whole tristate buffers 
*	selecting between even and odd slices.
*/

	assign	su_whldatasl_rd[0] =	( su_instelem_rd[2:0] == 3'b000 ) ;

	assign	su_whldatasl_rd[1] =	( su_instelem_rd[2:0] == 3'b001 ) ;

	assign	su_whldatasl_rd[2] =	( su_instelem_rd[2:0] == 3'b010 ) ;

	assign	su_whldatasl_rd[3] =	( su_instelem_rd[2:0] == 3'b011 ) ;

	assign	su_whldatasl_rd[4] =	( su_instelem_rd[2:0] == 3'b100 ) ;

	assign	su_whldatasl_rd[5] =	( su_instelem_rd[2:0] == 3'b101 ) ;

	assign	su_whldatasl_rd[6] =	( su_instelem_rd[2:0] == 3'b110 ) ;

	assign	su_whldatasl_rd[7] =	( su_instelem_rd[2:0] == 3'b111 ) ;


/*
*	Decode the element field to produce selects for mux selecting between vector, 
*	quarter, half and whole data within register file block.
*/

	assign	su_sclrdatasl_rd[0] =	( su_instelem_rd[3:1] == 3'b000 ) ; 	// vector operand

	assign	su_sclrdatasl_rd[1] =	( su_instelem_rd[3:1] == 3'b001 ) ;	// quarter scalar

	assign	su_sclrdatasl_rd[2] =	( su_instelem_rd[3:2] == 2'b01 ) ;	// half scalar

	assign	su_sclrdatasl_rd[3] =	( su_instelem_rd[3] == 1'b1 ) ;		// whole scalar


/*
*	Register vd port write address	
*/

	asdffen #(5, 0)	vctvdaddrrgwb (su_vd_addr_wb, su_vd_addr_ac, vct_instvld_ac, clk, reset_l );


/*
*	Register load port write address	
*/

        asdff #(5,0) suldrnumrgwb (su_ld_rnum_wb, su_ld_rnum_ac, clk, 1'b1);


/*
*	Decode the element field to produce selects for whole tristate buffers 
*	selecting between even and odd slices.
*/

	wire	su_wbvwrenff_wb;	/* write enable for datapath results */
	wire	vct_dvtypop_wb;			/* divide op in ac stage from VU */
	wire	[2:0]	vct_vs_addr_wb;		/* vs address in ac stage from VU */

	asdff #(1, 0)	vctwbvwrenffwb (su_wbvwrenff_wb, su_wbv_wr_en_ac, clk, reset_l );
	asdffen #(1, 0)	vctdvtypopwb (vct_dvtypop_wb, vct_dvtypop_ac, vct_instvld_ac, clk, reset_l );
	asdffen #(3, 0)	vctvsaddrffwb (vct_vs_addr_wb, vct_vs_addr_ac, vct_instvld_ac, clk, reset_l );

	assign	vct_wbv_wr_en_wb[7] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b000)
					) ;

	assign	vct_wbv_wr_en_wb[6] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b001)
					) ;

	assign	vct_wbv_wr_en_wb[5] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b010)
					) ;

	assign	vct_wbv_wr_en_wb[4] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b011)
					) ;

	assign	vct_wbv_wr_en_wb[3] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b100)
					) ;

	assign	vct_wbv_wr_en_wb[2] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b101)
					) ;

	assign	vct_wbv_wr_en_wb[1] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b110)
					) ;

	assign	vct_wbv_wr_en_wb[0] =	su_wbvwrenff_wb && 
					( !vct_dvtypop_wb || (vct_vs_addr_wb == 3'b111)
					) ;


/*
*	Register byte write enables for loads.
*/

	asdff #(16, 0)	vctbwergwb (su_bwe_wb, su_bwe_ac, clk, reset_l );

endmodule  // vurfctl