ddr_MDQS_MUX02_out.rpt
8.46 KB
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****************************************
Report : timing
-path full
-delay max
-nworst 10
-max_paths 1000
Design : bb
Version: 2001.08-SP1
Date : Mon Feb 24 15:51:37 2003
****************************************
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.195 * 4.316 r
U325/N01 (TBBUFX8) 0.181 * 4.497 r
ddr_d4inv1/N01 (TBINVX4) 0.308 * 4.805 f
ddr_somux1/H02 (TBMXI2X4) <- 0.086 * 4.891 f
ddr_somux1/N01 (TBMXI2X4) 0.165 * 5.056 r
pad_dqs1/N01 (TDBIAST2NNC1) 2.966 * 8.022 r
PAD_MDQS1 (inout) 0.000 8.022 r
data arrival time 8.022
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.195 * 4.316 r
U327/N01 (TBBUFX2) 0.086 * 4.402 r
U328/N01 (TBBUFX6) 0.252 * 4.654 r
U326/N01 (TBBUFX4) 0.208 * 4.862 r
ddr_d4inv0/N01 (TBINVX4) 0.066 * 4.928 f
ddr_somux0/H02 (TBMXI2X4) <- 0.000 * 4.928 f
ddr_somux0/N01 (TBMXI2X4) 0.080 * 5.008 r
pad_dqs0/N01 (TDBIAST2NNC1) 2.996 * 8.004 r
PAD_MDQS0 (inout) 0.000 8.004 r
data arrival time 8.004
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS2 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.195 * 4.316 r
U325/N01 (TBBUFX8) 0.181 * 4.497 r
U323/N01 (TBINVX8) 0.181 * 4.678 f
U324/N01 (TBINVX8) 0.162 * 4.840 r
ddr_d4inv2/N01 (TBINVX4) 0.082 * 4.922 f
ddr_somux2/H02 (TBMXI2X4) <- 0.001 * 4.923 f
ddr_somux2/N01 (TBMXI2X4) 0.082 * 5.005 r
pad_dqs2/N01 (TDBIAST2NNC1) 2.984 * 7.989 r
PAD_MDQS2 (inout) 0.000 7.989 r
data arrival time 7.989
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS3 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.195 * 4.316 r
U325/N01 (TBBUFX8) 0.181 * 4.497 r
ddr_d4inv3/N01 (TBINVX4) 0.054 * 4.551 f
ddr_somux3/H02 (TBMXI2X4) <- 0.001 * 4.552 f
ddr_somux3/N01 (TBMXI2X4) 0.084 * 4.636 r
pad_dqs3/N01 (TDBIAST2NNC1) 2.982 * 7.618 r
PAD_MDQS3 (inout) 0.000 7.618 r
data arrival time 7.618
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.281 * 4.402 f
U325/N01 (TBBUFX8) 0.164 * 4.566 f
ddr_d4inv1/N01 (TBINVX4) 0.510 * 5.076 r
ddr_somux1/H02 (TBMXI2X4) <- 0.092 * 5.168 r
ddr_somux1/N01 (TBMXI2X4) 0.224 * 5.392 f
pad_dqs1/N01 (TDBIAST2NNC1) 1.261 * 6.653 f
PAD_MDQS1 (inout) 0.000 6.653 f
data arrival time 6.653
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS2 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.281 * 4.402 f
U325/N01 (TBBUFX8) 0.164 * 4.566 f
U323/N01 (TBINVX8) 0.200 * 4.766 r
U324/N01 (TBINVX8) 0.149 * 4.915 f
ddr_d4inv2/N01 (TBINVX4) 0.082 * 4.997 r
ddr_somux2/H02 (TBMXI2X4) <- 0.001 * 4.998 r
ddr_somux2/N01 (TBMXI2X4) 0.105 * 5.103 f
pad_dqs2/N01 (TDBIAST2NNC1) 1.263 * 6.366 f
PAD_MDQS2 (inout) 0.000 6.366 f
data arrival time 6.366
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.281 * 4.402 f
U327/N01 (TBBUFX2) 0.111 * 4.513 f
U328/N01 (TBBUFX6) 0.175 * 4.688 f
U326/N01 (TBBUFX4) 0.193 * 4.881 f
ddr_d4inv0/N01 (TBINVX4) 0.064 * 4.945 r
ddr_somux0/H02 (TBMXI2X4) <- 0.000 * 4.945 r
ddr_somux0/N01 (TBMXI2X4) 0.105 * 5.050 f
pad_dqs0/N01 (TDBIAST2NNC1) 1.265 * 6.315 f
PAD_MDQS0 (inout) 0.000 6.315 f
data arrival time 6.315
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: ddr_wr_n_reg
(falling edge-triggered flip-flop clocked by MEMCLK)
Endpoint: PAD_MDQS3 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock network delay (propagated) 4.121 * 4.121
ddr_wr_n_reg/H02 (TBSMDFLQRBX4) 0.000 4.121 f
ddr_wr_n_reg/N01 (TBSMDFLQRBX4) 0.281 * 4.402 f
U325/N01 (TBBUFX8) 0.164 * 4.566 f
ddr_d4inv3/N01 (TBINVX4) 0.049 * 4.615 r
ddr_somux3/H02 (TBMXI2X4) <- 0.001 * 4.616 r
ddr_somux3/N01 (TBMXI2X4) 0.109 * 4.725 f
pad_dqs3/N01 (TDBIAST2NNC1) 1.263 * 5.988 f
PAD_MDQS3 (inout) 0.000 5.988 f
data arrival time 5.988
---------------------------------------------------------------
(Path is unconstrained)
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