bbsoc_min.tcl
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set timing_disable_internal_inout_cell_paths true
set report_default_significant_digits 3
set search_path { . \
/opc/cb12_V3.1.0/solaris/lib/CB12/common/synopsys/analog \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/clockdriver \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/iobuffer \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/nec_bscan \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/nec_scan \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/primitive \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/scan \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/script \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/special \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/testact \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/softmacro \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/gating \
/opc/cb12_V3.1.0/solaris/lib/common/synopsys/oscillator \
/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/ABD3835BM \
/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/USB1 \
/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/BINV \
/netfas5/design/bbsoc/bblib/RevA/SRAM_ROM/current/lib/CB12/cmos_1.5V \
/netfas5/design/bbsoc/bblib/RevA/VR4300/current \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvcp_nc15gfh \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_16x32 \
/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_64x32 \
}
set link_path { * \
\
analog.db \
clockdriver.db \
iobuffer.db \
nec_bscan.db \
nec_scan.db \
primitive.db \
scan.db \
special.db \
testact.db \
gating.db \
oscillator.db \
ABD3835BM.db \
USB1.db \
BINV.db \
WBROMSMHS2048W16C5N01_STA.db \
WBROMSMHS4096W32C5N01_STA.db \
WBSRAMDHDWR32W32C2_STA.db \
WBSRAMDHDWR32W72C2_STA.db \
WBSRAMMDWQR32W8C2_STA.db \
WBSRAMSHS128W8C3_STA.db \
WBSRAMSHS256W16C3B8_STA.db \
WBSRAMSHS256W41C3_STA.db \
WBSRAMSHS256W64C3B8_STA.db \
WBSRAMSHS4096W32C4B8_STA.db \
WBSRAMSHS512W64C3_STA.db \
NB4300V01_MAX_STA.db \
nvcp_nc15gfh_MAX_STA.db \
nvrm_nc15gfh_16x32_MAX_STA.db \
nvrm_nc15gfh_64x32_MAX_STA.db \
}
#################################
# Read Netlist
#################################
read_verilog ../../Verilog_Output/bb_layout.v
current_design bb
link
#################################
# timing analysis at max mode.
#################################
# Complete Sdf
read_sdf \
-analysis_type on_chip_variation \
-max_type sdf_min \
-min_type sdf_min \
../../bb.Universal.sdf1
#################################
# constraints
#################################
source ../sysclk.tcl
source ../memclk.tcl
source ../vclock.tcl
source ../usbclk.tcl
source ../others.tcl
source ../fixes.tcl
#################################
# report
#################################
update_timing
source ../ddr_report.tcl
report_constraint -all_violators -min_delay > rep.min.viol
report_constraint -all_violators -min_delay -verbose > rep.min.viol.verbose
quit