fixes.tcl
1.42 KB
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#/*
# * virage cell libraries have problem from
# * RECALL -> RCREAD
# * COMP -> RCREADY
# * COMP -> MATCH
# */
set_disable_timing nvrm_nc15gfh_64x32_lib/nvrm_nc15gfh_64x32 -from RECALL -to RCREADY
set_disable_timing nvrm_nc15gfh_64x32_lib/nvrm_nc15gfh_64x32 -from COMP -to RCREADY
set_disable_timing nvrm_nc15gfh_64x32_lib/nvrm_nc15gfh_64x32 -from COMP -to MATCH
set_disable_timing nvrm_nc15gfh_16x32_lib/nvrm_nc15gfh_16x32 -from RECALL -to RCREADY
set_disable_timing nvrm_nc15gfh_16x32_lib/nvrm_nc15gfh_16x32 -from COMP -to RCREADY
set_disable_timing nvrm_nc15gfh_16x32_lib/nvrm_nc15gfh_16x32 -from COMP -to MATCH
#/*
# * disable virage SCLK->SO path;
# * virage has a path delay of 142ns on it;
# * but we don't want the rest of the JTAGCLK domain limited to 6MHz;
# * have to keep in mind when using the virage serial interface;
# */
set_disable_timing nvrm_nc15gfh_64x32_lib/nvrm_nc15gfh_64x32 -from SCLK -to SO
set_disable_timing nvrm_nc15gfh_16x32_lib/nvrm_nc15gfh_16x32 -from SCLK -to SO
#
# usb false path
#
set_false_path -from SYSCLK -to [list PAD_USB_DPLUS* PAD_USB_DMINUS* ]
##########################
# Scan & TestBus Setting
##########################
#
#set_ideal_net NEC_NET_*
#
#/* Scan Disable */
#
set_case_analysis 0 PAD_TMC
set_case_analysis 0 PAD_NECTRST
set_case_analysis 1 PAD_NRING_ENL
#
#/* TestAct Disable */
#
set_case_analysis 0 TESTACT_TAPINST/irdec_inst/U16/N01
set_case_analysis 0 NEC_NET_TBUSMODE_BUF/N01