vcs.max.com
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#!/bin/csh -f
#
set BB_NEC_LIB="../../lib/verilog/nec.15"
set BB_CHIP_LIB="../../lib"
vcs \
+optconfigfile+twostate.cfg +define+NEC_TEST_VECTORS \
### filename list of HDL files \
# Controle module of simulation \
top.max.v \
\
# User module \
# Change to Broadon Gatelevel Netlist file \
'../../syn/bb.v' \
\
### options of VCS \
./opc_ROM_ctrl_real.v \
./NOVeA_2K_ROM_ctrl.v \
# library assignmet \
+libext+.v \
+libext+.vp \
-y ${BB_NEC_LIB}/libverilog_udp \
-y ${BB_NEC_LIB}/testact \
-y ${BB_NEC_LIB}/clockdriver \
-y ${BB_NEC_LIB}/iobuffer \
-y ${BB_NEC_LIB}/nec_bscan \
-y ${BB_NEC_LIB}/primitive \
-y ${BB_NEC_LIB}/scan \
-y ${BB_NEC_LIB}/special \
-y ${BB_NEC_LIB}/nec_scan \
-y ${BB_NEC_LIB}/gating \
-y ${BB_NEC_LIB}/oscillator \
-y ${BB_NEC_LIB}/memories \
-y ${BB_NEC_LIB}/verilog_udp \
-y ${BB_CHIP_LIB}/verilog/r4300\
#-y '/vcs/dummy_model/analog' \
# -y /home/product/BBProject/bblib/RevA/CSR/current/lib/common/verilog/BINV \
-y ${BB_CHIP_LIB}/usb_arc/verilog \
# -y /home/product/BBProject/bblib/RevA/SRAM_ROM/current/lib/CB12/cmos_1.5V \
# -y /home/product/BBProject/bblib/RevA/CSR/current/lib/CB12/cmos_1.5V/verilog/dummy_model/ABD3835BM \
-v ${BB_CHIP_LIB}/verilog/virage/nvcp_nc15gfh.v \
-v ${BB_CHIP_LIB}/verilog/virage/NMS_16x32/nvrm_nc15gfh_16x32.v \
-v ${BB_CHIP_LIB}/verilog/virage/NMS_64x32/nvrm_nc15gfh_64x32.v \
-v ${BB_CHIP_LIB}/verilog/virage/nvcp_nc15gfh.v \
-v ${BB_CHIP_LIB}/verilog/virage/NMS_16x32/nvrm_nc15gfh_16x32.v \
-v ${BB_CHIP_LIB}/verilog/virage/NMS_64x32/nvrm_nc15gfh_64x32.v \
-v ${BB_NEC_LIB}/special/AAPLSVRH.vp \
-v ${BB_NEC_LIB}/special/ABPLSSCH_3.vp \
-v ${BB_CHIP_LIB}/verilog/r4300/ABPLSSCH_cpu.vp \
# -v /home/product/BBProject/bblib/RevA/VR4300/current/NB4300V01_ver22b.vp \
\
# controle of logging \
-V -l all_dc.pat0.max.vcs.log \
\
-o simv.max \
\
# incremental compile mode \
-Mupdate \
-Mdirectory=./csrc.max \
\
# controle of simulation mode \
+maxdelays # delay mode setting \
\
# disables to issue the warning message \
+nowarnTFNPC # about floating ports \
\
# set the pulse transfer mode \
+transport_path_delays +pulse_r/0 \
+transport_int_delays +pulse_int_r/0 \
\
+notimingchecks # -timing_xgen & -timing_message off \
+pulse_e/0 +pulse_int_e/0 # spike through mode \
\
if ( ${status} ) exit 1
./simv.max \
\
# controle of logging \
-V -a all_dc.pat0.max.vcs.log \
\
+vcdon \
if ( ${status} ) exit 1