// clk_mon.v v1 Frank Berndt
// clock monitor;
// :set tabstop=4

`timescale 1ps/1ps

module clk_mon (
	sysclk, memclk, reset_l,
);
	input sysclk;
	input memclk;
	input reset_l;

	// monitor alignment of sysclk and memclk;
	// both signals are looked at after the clock tree buffers;

	integer sysclk_time;
	integer memclk_time;
	integer delta;
	integer clock_mon;

	initial begin
		clock_mon = 1;
		if ($test$plusargs("non_clk_mon")) clock_mon=0;
	end



	always @(posedge sysclk)
		sysclk_time = $time;

	always @(posedge memclk)
		memclk_time = $time;

	always @(negedge memclk)
	begin
	if (clock_mon) 
		if((reset_l === 1'b1) & (sysclk === 1'b1) & (sysclk_time !== memclk_time)) begin
			delta = sysclk_time - memclk_time;
			$display("ERROR: %t: %M: sysclk/memclk phase error %0dps", $time, delta);
			$finish;
		end
	end

endmodule