rsp_mon_gate.v
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module rsp_mon_gate(clk,reset_l);
input clk,reset_l;
`define SUpath vsim.bcp.rsp_0_su
reg rsp_display_on;
reg [11:0] pc,su_rd_pc_debug;
reg [31:0] inst_0, inst_1;
reg halt,set_broke,dma_busy;
reg SR_Wen;
reg [31:0] SR_d;
reg [4:0] SR_w_addr;
reg imem_web;
reg [63:0] imem_din;
reg show_imem_on_r1;
reg dmem_we;
reg [15:0] dmem_web;
reg [11:0] dmemh_adr;
reg [11:0] dmeml_adr;
reg [63:0] dmemh_din;
reg [63:0] dmeml_din;
integer i;
initial
begin
pc = 0;
su_rd_pc_debug = 0;
inst_0 = 0;
inst_1 = 0;
halt = 0;
set_broke = 0;
dma_busy = 0;
SR_Wen = 0;
SR_w_addr = 0;
SR_d = 0;
imem_web = 1;
imem_din = 0;
dmem_we = 1;
dmem_web = 16'hFFFF;
dmemh_din = 0;
dmeml_din = 0;
show_imem_on_r1 = 0;
rsp_display_on = 0;
if ($test$plusargs("rsp_mon"))
rsp_display_on = 1;
if ($test$plusargs("show_imem_on_r1"))
show_imem_on_r1 = 1;
end
reg [15:0] tmp_web;
always @(posedge clk)
if (rsp_display_on)
begin
pc <= {vsim.bcp.rsp_0_imem.a,3'b000};
inst_0 <= vsim.bcp.rsp_0_imem.dout[63:32];
inst_1 <= vsim.bcp.rsp_0_imem.dout[31:0];
imem_web <= vsim.bcp.rsp_0_imem.web;
if (vsim.bcp.rsp_0_imem.web===1'b0)
imem_din <= vsim.bcp.rsp_0_imem.di;
tmp_web = {vsim.bcp.rsp_0_dmemx2_dmemLow.web, vsim.bcp.rsp_0_dmemx2_dmemHigh.web};
dmem_web <= tmp_web;
dmem_we <= (tmp_web !==16'hffff);
if (tmp_web!==16'hFFFF) begin
dmemh_din <= vsim.bcp.rsp_0_dmemx2_dmemHigh.di;
dmeml_din <= vsim.bcp.rsp_0_dmemx2_dmemLow.di;
dmemh_adr <= {vsim.bcp.rsp_0_dmemx2_dmemHigh.a,4'b0 };
dmeml_adr <= {vsim.bcp.rsp_0_dmemx2_dmemLow.a,4'b0 };
end
halt <= vsim.bcp.rsp_0_io_logic.halt;
set_broke <= vsim.bcp.rsp_0_io_logic.set_broke;
dma_busy <= vsim.bcp.rsp_0_io_logic.io_mem_dma_dma_busy;
SR_Wen <= vsim.bcp.rsp_0_su_surf_wen;
if (vsim.bcp.rsp_0_su_surf_wen)
begin
SR_w_addr <= vsim.bcp.rsp_0_su_sudp.surf_w;
SR_d[31] <= vsim.bcp.rsp_0_su_sudp.wb_data_31_ ;
SR_d[30] <= vsim.bcp.rsp_0_su_sudp.wb_data_30_ ;
SR_d[29] <= vsim.bcp.rsp_0_su_sudp.wb_data_29_ ;
SR_d[28] <= vsim.bcp.rsp_0_su_sudp.wb_data_28_ ;
SR_d[27] <= vsim.bcp.rsp_0_su_sudp.wb_data_27_ ;
SR_d[26] <= vsim.bcp.rsp_0_su_sudp.wb_data_26_ ;
SR_d[25] <= vsim.bcp.rsp_0_su_sudp.wb_data_25_ ;
SR_d[24] <= vsim.bcp.rsp_0_su_sudp.wb_data_24_ ;
SR_d[23] <= vsim.bcp.rsp_0_su_sudp.wb_data_23_ ;
SR_d[22] <= vsim.bcp.rsp_0_su_sudp.wb_data_22_ ;
SR_d[21] <= vsim.bcp.rsp_0_su_sudp.wb_data_21_ ;
SR_d[20] <= vsim.bcp.rsp_0_su_sudp.wb_data_20_ ;
SR_d[19] <= vsim.bcp.rsp_0_su_sudp.wb_data_19_ ;
SR_d[18] <= vsim.bcp.rsp_0_su_sudp.wb_data_18_ ;
SR_d[17] <= vsim.bcp.rsp_0_su_sudp.wb_data_17_ ;
SR_d[16] <= vsim.bcp.rsp_0_su_sudp.wb_data_16_ ;
SR_d[15] <= vsim.bcp.rsp_0_su_sudp.wb_data_15_ ;
SR_d[14] <= vsim.bcp.rsp_0_su_sudp.wb_data_14_ ;
SR_d[13] <= vsim.bcp.rsp_0_su_sudp.wb_data_13_ ;
SR_d[12] <= vsim.bcp.rsp_0_su_sudp.wb_data_12_ ;
SR_d[11] <= vsim.bcp.rsp_0_su_sudp.wb_data_11_ ;
SR_d[10] <= vsim.bcp.rsp_0_su_sudp.wb_data_10_ ;
SR_d[9] <= vsim.bcp.rsp_0_su_sudp.wb_data_9_ ;
SR_d[8] <= vsim.bcp.rsp_0_su_sudp.wb_data_8_ ;
SR_d[7] <= vsim.bcp.rsp_0_su_sudp.wb_data_7_ ;
SR_d[6] <= vsim.bcp.rsp_0_su_sudp.wb_data_6_ ;
SR_d[5] <= vsim.bcp.rsp_0_su_sudp.wb_data_5_ ;
SR_d[4] <= vsim.bcp.rsp_0_su_sudp.wb_data_4_ ;
SR_d[3] <= vsim.bcp.rsp_0_su_sudp.wb_data_3_ ;
SR_d[2] <= vsim.bcp.rsp_0_su_sudp.wb_data_2_ ;
SR_d[1] <= vsim.bcp.rsp_0_su_sudp.wb_data_1_ ;
SR_d[0] <= vsim.bcp.rsp_0_su_sudp.wb_data_0_ ;
end
su_rd_pc_debug <= {vsim.bcp.rsp_0_su_suctl.pc,2'b00};
end
always @(negedge clk)
begin
SR_Wen <= 0;
imem_web <= 1;
dmem_we <= 0;
end
always @(
pc or
inst_0 or
inst_1 or
su_rd_pc_debug or
halt or
set_broke or
dma_busy or
posedge SR_Wen or
negedge imem_web or
posedge dmem_we
)
if (rsp_display_on)
begin
$display($time, " : RSP: H=%b B=%b D=%b im=%h (H=%h L=%h) npc=%h",
halt, set_broke, dma_busy, pc, inst_0, inst_1, su_rd_pc_debug);
if (imem_web===1'b0)
$display($time, " : RSP: imem dma write : imem_din= %8h_%8h",
imem_din[63:32],imem_din[31:0]);
if (dmem_web!==16'hFFFF)
$display(" dmem write: %2h @%8h %8h_%8h %2h @%8h %8h_%8h",
dmem_web[15:8],
dmemh_adr, dmemh_din[63:32], dmemh_din[31:0],
dmem_web[ 7:0],
dmeml_adr, dmeml_din[63:32], dmeml_din[31:0]);
if (SR_Wen)
begin
$display($time, " : RSP: SU Reg: R%0d = %h", SR_w_addr, SR_d);
if (show_imem_on_r1 && SR_w_addr===5'h1) dump_imem;
end
end
task dump_imem;
reg [9:0] i;
reg [31:0] dh0,dl0,dh1,dl1;
begin
$display("+++++++++++++++++ IMEM DUMP ++++++++++++++++++++++");
for (i=0; i<512; i=i+2)
begin
{ dh0,dl0 } = vsim.bcp.rsp_0_imem.ram_prim[i ];
{ dh1,dl1 } = vsim.bcp.rsp_0_imem.ram_prim[i+1];
$display(" IMEM[0x%3h]=%4h_%4h (hex) IMEM[0x%3h]=%4h_%4h (hex)",
i,dh0,dl0,i+'h1,dh1,dl1);
end
end
endtask
endmodule