/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
				RSP CTRACE TASKS
  
 RSP CTRACE TASKS. Basic running sequence:
	(1) DMA all rsp IMEM and DMEM data to rdram via backdoor
	(2) Let SP dma all data to IMEM and DMEM
	(3) Turn on rsp_ctrace_on
	(4) Polling rsp_ctrace_status
		rsp_ctrace_status:
		bit[15] ---- TimeOut
        bits[14:0] ---- status (4040010)
		bit[16] --- Error detected by rsp_ctrace
		bit[17] --- sp stop by hit break
    (5) Bdoor read all trace data and do comparison

 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ 
`include "rsp_ctrace.vh"

/****** TimeOut counters *******/
reg [23:0] rsp_cycle_count;
reg [23:0] rsp_cycle_count_save;
reg rsp_TimeOut;
reg rsp_single_step;
reg rsp_ctrace_test_on;
reg rsp_Halt;
reg [1:0] rsp_test_type;

initial begin
	rsp_TimeOut = 0;	
	rsp_ctrace_test_on = 0;
	rsp_single_step = 0;
end

always @(posedge sysclk) 
  if (rsp_ctrace_test_on) begin
	if (!rsp_TimeOut)
		rsp_cycle_count <= rsp_cycle_count + 1;
  end

always @(rsp_cycle_count)
	if (rsp_single_step)
    	rsp_TimeOut = (rsp_cycle_count === `TIMEOUT_CNT_SS);
  	else
    	rsp_TimeOut = (rsp_cycle_count === `TIMEOUT_CNT);

task rsp_ctrace_on;
	input single_step;
	input [1:0] test_type;
	begin
		vsim.bb.cpu.swrite('h408_0000, 3, 32'h0);    //clear PC
		rsp_cycle_count <= 0;
		rsp_TimeOut <= 0;
		vsim.bb.cpu.swrite('h404_0010, 3, (single_step<<6) | 32'h5); 
		rsp_single_step = single_step;
		`tr.SingleStep = single_step;

		@(posedge sysclk);
   		`tr.di_monitor_on = 1; 
		`tr.test_on = 1;
		rsp_ctrace_test_on = 1;
		
		rsp_test_type = test_type;
		`tr.break_inst_seen = 0;
	end
endtask

task rsp_ctrace_off;
	begin
		`tr.test_on = 0;
		rsp_ctrace_test_on = 0;
		rsp_single_step = 0;
	end
endtask

task rsp_ctrace_next;
	begin
		rsp_cycle_count <= 0;
		rsp_TimeOut <= 0;
		vsim.bb.cpu.swrite('h404_0010, 3, 32'h5);
	end
endtask

task rsp_ctrace_status;
	output [31:0] status;
	reg [31:0] rsp_status;
	integer ii;
	begin
		vsim.bb.cpu.sread('h404_0010, 3, rsp_status);

		status = rsp_status;
		status[15] = rsp_TimeOut;
		status[16] = `tr.trError | ( rsp_single_step & `tr.SingleStepError);
		status[17] = (rsp_single_step)?(status[1] & `tr.break_inst_seen):0;

		if (status[1]) begin
			`tr.su_mem_data = {20'b0, `tr.sumem_pntr};
        	`tr.su_mem[0] = `tr.su_mem_data;

        	for (ii= 0; ii<32; ii=ii+1) begin
            	`tr.vv_mem_data = {243'b0, `tr.vumem_pntr[ii]};
            	`tr.vu_mem[i*`VR_TRACE_DEPTH] = `tr.vv_mem_data;
        	end

        	`tr.dm_mem_data = {140'b0, `tr.dmmem_pntr};
        	`tr.dm_mem[0] = `tr.dm_mem_data;

			if ((rsp_single_step & status[17]) || (!rsp_single_step)) begin
					// SU test
				if (rsp_test_type == 2'b00 && (`r1 & 32'hff00ffff)===32'h0)
					status[16] = 1'b1;

					// VU test
				if (rsp_test_type == 2'b01 && (`r31 !== 32'hfeed0000))
					status[16] = 1'b1;

					// DM test
				if (rsp_test_type == 2'b11 && (`r1 !== 32'hfeed0000)
					&& (`r1 !== 32'h0000feed)) 
					status[16] = 1'b1;
			end
		end
	end
endtask

task rsp_ctrace_data;
	input  [31:0] addr;
	input  [1:0]  which;
	output [31:0] d0, d1, d2, d3, d4, d5, d6, d7;
	reg [39:0]  su_data;
	reg [256:0] vu_data;
	reg [159:0] dm_data;
	begin
		case (which) 
			2'b00: begin
				su_data = `tr.su_mem[addr];
				d0 = su_data[39:8];
				d1 = {su_data[7:0], 24'b0};
			    end
			2'b01: begin
				vu_data = `tr.vu_mem[addr];
				d0 = {31'b0, vu_data[256]};
				d1 = vu_data[255:224];
				d2 = vu_data[223:192];
				d3 = vu_data[191:160];
				d4 = vu_data[159:128];
				end
			2'b10: begin
				dm_data = `tr.dm_mem[addr];
				d0 = dm_data[159:128];
				d1 = dm_data[127:96];
				d2 = dm_data[95:64];
				d3 = dm_data[63:32];
				d4 = dm_data[31:0];
				end
			2'b11: begin
				vu_data = `tr.vu_mem[addr];
				d0 = vu_data[127:96];
                d1 = vu_data[95:64];
                d2 = vu_data[63:32];
                d3 = vu_data[31:0];
				end
        endcase
	end
endtask

task rsp_imem_load;
	input [31:0] addr;
	input [31:0] data0;
	input [31:0] data1;
	integer i;
	begin
		`rsp_path.imem.sram.memory[addr] = {data0, data1};		
	end
endtask

task rsp_dmem_load;
	input [31:0] addr;
	input [7:0]  wh;
	input [7:0]  data;
	begin
		case (wh)		
			8'h00: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h01: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h02: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h03: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h04: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h05: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h06: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			8'h07: begin
				`rsp_path.dmem.dmem1.memory[addr] = data;
			end
			
			8'h08: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h09: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0a: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0b: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0c: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0d: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0e: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
			8'h0f: begin
				`rsp_path.dmem.dmem0.memory[addr] = data;
			end 
		endcase
	end
endtask