//
//   IPC interfaces to extend USB tests
//   :set tabstop=4

`define CTL1 vsim.usb_tests.ext_host_ctl1.u_host_ctl
`define CTL0 vsim.usb_tests.ext_host_ctl0.u_host_ctl
`define CTL0T vsim.usb_tests.ext_host_ctl0.u_vusb_term
`define CTL1T vsim.usb_tests.ext_host_ctl1.u_vusb_term
`define CTL0AT vsim.usb_tests.ext_host_ctl0.u_vusb_bias
`define CTL1AT vsim.usb_tests.ext_host_ctl1.u_vusb_bias

task bb_usb_term_ctl ;
	input[31:0] which ;
	input[31:0] func ;
	input[31:0] value ;

	begin
		casex({which[0],func[0]})
		   2'b00 : `CTL0T.bb_slave = value[0] ;
		   2'b10 : `CTL1T.bb_slave = value[0] ;

		   2'b01 : `CTL0T.cbl_connect = value[0] ;
		   2'b11 : `CTL1T.cbl_connect = value[0] ;
		endcase
	end
endtask

task bb_usb_bias_ctl ;
	input[31:0] which ;
	input[31:0] func ;
	input[31:0] value ;
	
	begin
		casex ({which[0],func[0]})
		   2'b00 : `CTL0AT.dev_speed = value[0] ;
		   2'b10 : `CTL1AT.dev_speed = value[0] ;

		   2'b01 : `CTL0AT.cbl_connect = value[0] ;
		   2'b11 : `CTL1AT.cbl_connect = value[0] ;
		endcase
	end
endtask

task bb_usb_host_ctl ;
	input[31:0] which ;
	input[31:0] func ;
	input[31:0] value ;

	begin
		casex ({which[0],func[0]})
		   2'b01 : 
				if (`CTL0.lsdev != value[0]) begin
					`CTL0.lsdev = value[0] ;
					`CTL0.bcp_ext_lsdev_setup = 1;
				end
		   2'b11 : 
				if (`CTL1.lsdev != value[0])  begin 
					`CTL1.lsdev = value[0] ;
					`CTL1.bcp_ext_lsdev_setup = 1;
				end
		   2'b00 : `CTL0.tb_is_device = value[0] ;
		   2'b10 : `CTL1.tb_is_device = value[0] ;
		endcase
	end
endtask

// which is used to specified which USB controller
// test     = 0 will start ARC tests
// test[16] =  write bits [7:0] to bcp_test_on
// test[17] =  write bits [15:8] to bcp_test_err
// test[18] =  set packet length
// test[19] =  token pid
// test[20] =  packet pid
// test[21] =  end point
// test[22] =  ack?
// test[23] =  bcp device id

task bb_usb_test_on;
	input [31:0] which;
	input [31:0] test;

	begin
		casex ({which[0], test[23:16]})

			9'b000000000: `CTL0.usb_test_on = 1;
			9'b100000000: `CTL1.usb_test_on = 1;

			9'b000000001: `CTL0.bcp_test_on = test[7:0];
			9'b100000001: `CTL1.bcp_test_on = test[7:0];

			9'b000000010: `CTL0.bcp_test_err = test[15:8];
			9'b100000010: `CTL1.bcp_test_err = test[15:8];

			9'b000000011: begin
					`CTL0.bcp_test_on = test[7:0];
					`CTL0.bcp_test_err = test[15:8];
				end

			9'b100000011: begin
					`CTL1.bcp_test_on = test[7:0];
					`CTL1.bcp_test_err = test[15:8];
				end

			9'b0000001xx: `CTL0.bcp_pkt_length = {21'b0, test[10:0]};
			9'b1000001xx: `CTL1.bcp_pkt_length = {21'b0, test[10:0]};
	
			9'b000001xxx: `CTL0.bcp_token_pid = {24'b0, test[7:0]};
			9'b100001xxx: `CTL1.bcp_token_pid = {24'b0, test[7:0]};
			
			9'b00001xxxx: `CTL0.bcp_pkt_pid = {24'b0, test[7:0]};
			9'b10001xxxx: `CTL1.bcp_pkt_pid = {24'b0, test[7:0]};

			9'b0001xxxxx: `CTL0.bcp_endpt = {28'b0, test[3:0]};
			9'b1001xxxxx: `CTL1.bcp_endpt = {28'b0, test[3:0]};
			
			9'b001xxxxxx: `CTL0.bcp_ack = {24'b0, test[7:0]};
			9'b101xxxxxx: `CTL1.bcp_ack = {24'b0, test[7:0]};

			9'b01xxxxxxx: `CTL0.bcp_device = {24'b0, test[7:0]};
			9'b11xxxxxxx: `CTL1.bcp_device = {24'b0, test[7:0]};

		endcase
			
		/* $display(" * * * * * * 0 * * * * * * * ");
		$display("%x %x %x %x %x %x", `CTL0.bcp_device, `CTL0.bcp_ack,
				`CTL0.bcp_endpt, `CTL0.bcp_pkt_pid, 
				`CTL0.bcp_token_pid, `CTL0.bcp_pkt_length);

		$display(" * * * * * * 1 * * * * * * * ");
		$display("%x %x %x %x %x %x", `CTL1.bcp_device, `CTL1.bcp_ack,
				`CTL1.bcp_endpt, `CTL1.bcp_pkt_pid, 
				`CTL1.bcp_token_pid, `CTL1.bcp_pkt_length); */
	end

endtask


// Return usb bb test stat and read pkt length
// Bits [26:16] --- paket length
// Bits [15:8] --- bcp_test_err
// Bits [7:0] --- bcp_test_on
task bb_usb_stat;
	input [31:0] which;
	output [31:0] data;

	begin
		if (which) 
`ifdef SIMGATE
			data = {4'b0, vsim.bb.bcp.ui.irq_1_,
					`CTL1.bcp_pkt_length[10:0],
					`CTL1.bcp_test_err[7:0],
					`CTL1.bcp_test_on[7:0]};
`else
			data = {4'b0, vsim.bb.bcp.ui.irq[1],
					`CTL1.bcp_pkt_length[10:0],
					`CTL1.bcp_test_err[7:0],
					`CTL1.bcp_test_on[7:0]};
`endif
		else
`ifdef SIMGATE
			data = {4'b0, vsim.bb.bcp.ui.irq_0_,
					`CTL0.bcp_pkt_length[10:0],
                    `CTL0.bcp_test_err[7:0],
                    `CTL0.bcp_test_on[7:0]};	
`else
			data = {4'b0, vsim.bb.bcp.ui.irq[0],
					`CTL0.bcp_pkt_length[10:0],
                    `CTL0.bcp_test_err[7:0],
                    `CTL0.bcp_test_on[7:0]};	
`endif
	end

endtask
// Read BCP USB packet data
// Addr 0-1023 
// size 1-4 : how many bytes
// Data is combined as Big endian
task bb_usb_read_packet;
	input [31:0] addr;
	input [31:0] size;
	input [31:0] which;
	output [31:0] data;	
	integer i;

	begin
		addr = addr & 32'h03FF;
		size = ((size - 1) & 3) + 1; 

		data = 32'h0;
		for (i=0; i<size; i=i+1) begin
			data = data << 8;
			if ((addr + i) <= 1024)
				data[7:0] = (which)? `CTL1.bcp_pkt_data[addr+i]:
								     `CTL0.bcp_pkt_data[addr+i];
		end 

	    if (size < 4) data = data << ((4-size)*8);
	end
endtask

task bb_usb_write_packet;
	input [31:0] addr;
	input [31:0] size;
	input [31:0] which;
	input [31:0] data;
	
	integer i;
	reg [7:0] byte;
	begin
		
		addr = addr & 32'h03FF;
		size = ((size - 1) & 3) + 1; 

		for (i=0; i<size; i=i+1) begin
			byte = data[31:24];
			data = data << 8;

			if ((addr + i) <= 1024) begin
				if (which) `CTL1.bcp_pkt_data[addr+i] = byte;
				else `CTL0.bcp_pkt_data[addr+i] = byte;
			end	
		end
	
		/* $display(" * CTL 0 PKT %2x %2x %2x %2x %2x %2x %2x %2x",
				`CTL0.bcp_pkt_data[0],  `CTL0.bcp_pkt_data[1],
				`CTL0.bcp_pkt_data[2],  `CTL0.bcp_pkt_data[3],
				`CTL0.bcp_pkt_data[4],  `CTL0.bcp_pkt_data[5],
				`CTL0.bcp_pkt_data[6],  `CTL0.bcp_pkt_data[7]);
		$display(" * CTL 1 PKT %2x %2x %2x %2x %2x %2x %2x %2x",
				`CTL1.bcp_pkt_data[0],  `CTL1.bcp_pkt_data[1],
				`CTL1.bcp_pkt_data[2],  `CTL1.bcp_pkt_data[3],
				`CTL1.bcp_pkt_data[4],  `CTL1.bcp_pkt_data[5],
				`CTL1.bcp_pkt_data[6],  `CTL1.bcp_pkt_data[7]); */
	end
endtask