// mi_tests.v v1 Frank Berndt
// mi tests;
// :set tabstop=4

`timescale 1ns/1ns

// definitions for address space support;

`define	MI_MEM_X64L			// lower x64 space (0x01xxxxxx) is implemented;
`define	MI_MEM_X64H			// upper x64 space (0x8xxxxxxx) is implemented;

`define	MI_NA_BROM		14		// # of addr bits on brom;
`define	MI_NA_BRAM		16		// # of addr bits on brom;
`define	MI_NA_IRAM		15		// # of addr bits on brom;
`define	MI_NA_VMEM0		6		// # of addr bits on v0;
`define	MI_NA_VMEM1		6		// # of addr bits on v1;
`define	MI_NA_VMEM2		8		// # of addr bits on v2;
`define	MI_NA_REGS		20		// # of addr bits in register spaces;
`define	MI_NA_RDCFG		24		// # of addr bits in RDRAM cfg space;

`define	MI_N_SUBBLK		8		// # of subblock order random tests;
`define	MI_N_BLKERR		8		// # of random block error tests;
`define	MI_N_MEMRAND	256		// # of random memory tests;

// define MI_ONE_MCFG to run with only one random ddr configuration;

// copy of rom content;
// file is reset every time cpu comes out of reset;

reg [31:0] mi_brom_data [0:4095];
reg [31:0] mi_boot_word;

// pattern seeds for virage cachelines;

reg [31:0] mi_vpat [0:15];

// setup brom_data from initialization file;

initial
	$readmemh("tests/brom.dat", mi_brom_data);

// wire hooks into rtl or gate-level;

	wire [2:0] bb_v_porst;

`ifdef	SIMGATE
	assign bb_v_porst = { vsim.bb.v_porst_2_, vsim.bb.v_porst_1_, vsim.bb.v_porst_0_ };
`else	// SIMGATE
	assign bb_v_porst = vsim.bb.v_porst;
`endif	// SIMGATE

// monitor virage charge-pump porst;

reg [2:0] mi_porst;

initial
	mi_porst = 0;
always @(negedge bb_v_porst[0])
	mi_porst[0] = 1;
always @(negedge bb_v_porst[1])
	mi_porst[1] = 1;
always @(negedge bb_v_porst[2])
	mi_porst[2] = 1;

// time of button push for button tests;

reg [63:0] mi_but_time;

// setup mi cbus request monitor;

task mi_cbus_mon;
	input write;		// cbus writes ok;
	input read;			// cbus reads ok;
	input dma;			// cbus dma ok;
	begin
		vsim.cbus_mon.mi_req.write_ok = write;
		vsim.cbus_mon.mi_req.read_ok = read;
		vsim.cbus_mon.mi_req.dma_ok = dma;
	end
endtask

// check state of reset;

task mi_check_rst;
	input cold;			// expected cold reset;
	input warm;			// expected warm reset;
	input [2:0] div;	// expected divide mode;
	begin
		if(coldrst_l !== cold)
			$display("ERROR: %t: %M: coldrst_l %b exp %b", $time, coldrst_l, cold);
		if(warmrst_l !== warm)
			$display("ERROR: %t: %M: warmrst_l %b exp %b", $time, warmrst_l, warm);
		if(divmode !== div)
			$display("ERROR: %t: %M: divmode %b exp %b", $time, divmode, div);
	end
endtask

// check state of interrupt;

task mi_check_intr;
	input [2:0] intr;	// which intr bit to check;
	input val;			// expected interrupt;
	reg xintr;
	begin
		xintr = int_l >> intr;
		if(xintr !== val)
			$display("ERROR: %t: %M: int_l[%0d] %b exp %b", $time, intr, xintr, val);
	end
endtask

// check state of nmi;

task mi_check_nmi;
	input val;			// expected nmi;
	input [2:0] spc;	// nmi latency in hardware;
	begin
		req_spacing(spc);
		if(nmi_l !== val)
			$display("ERROR: %t: %M: nmi_l %b exp %b", $time, nmi_l, val);
	end
endtask

// check state of secure mode;

task mi_check_secure;
	input val;
	reg secure;
	begin
		secure = vsim.bb.bcp.mi.secure;
		if(secure !== val)
			$display("ERROR: %t: %M: secure mode %b exp %b", $time, secure, val);
	end
endtask

// check secure timer enable;

task mi_check_sec_timer;
	input val;
	reg stim_on;
	begin
		stim_on = vsim.bb.bcp.mi.stim_on;
		if(stim_on !== val)
			$display("ERROR: %t: %M: secure timer %b exp %b", $time, stim_on, val);
	end
endtask

// check status of ai/vi reset;

task mi_avrst_check;
	input exp;			// expected value;
	reg rst;			// signal to check;
	begin
		rst = vsim.bb.bcp.ai.reset_l;
		if(rst !== exp)
			$display("ERROR: %t: %M: ai.reset_l %b exp %b", $time, rst, exp);
		rst = vsim.bb.bcp.ai.reset_l;
		if(rst !== exp)
			$display("ERROR: %t: %M: vi.reset_l %b exp %b", $time, rst, exp);
	end
endtask

// test mi defaults after reset;

task mi_after_reset;
	input [2:0] div;		// expected divmode;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg [31:0] xdata;		// other data;
	reg [31:0] exp;			// expected data;
	begin
		// boot word must be from brom after reset;

		mi_boot_word = mi_brom_data[0];

		// test interrupt lines;
		// INTR_ERR may be active;

		mi_check_intr(`INTR_RCP, 1);
		mi_check_intr(`INTR_DEV, 1);
		mi_check_intr(`INTR_BUT, 1);
		mi_check_intr(`INTR_RSVD, 1);

		// test compatible registers;

		$display("test: %M: MI_MODE");
		sread(`MI_MODE, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		$display("test: %M: MI_VERSION");
		sread(`MI_VERSION, `CPU_SIZE_4, rdata);
		exp = 32'h02_02_b0_b0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		$display("test: %M: MI_INTR");
		sread(`MI_INTR, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		$display("test: %M: MI_MASK");
		sread(`MI_MASK, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		// test new registers;

		$display("test: %M: MI_CTRL");
		sread(`MI_CTRL, `CPU_SIZE_4, rdata);
		exp = { 12'd0, 7'b0000000, 2'b00, div, 8'd0 };
		rd_check(0, exp, 32'hffff_ffff, 0);

		// reset armed the secure mode trigger, but secure mode
		// is not on yet, nmi must not be asserted;
		// single fetch from 1fc0_0000 turns on secure mode;

		$display("test: %M: MI_SEC_MODE");
		mi_sec_mode_enter(1);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		exp = { 5'd0, 3'd0, 16'd0, 8'b0000_0011 };
		rd_check(0, exp, 32'hffff_ffff, 0);

		// leave secure timer off;
		// check that timer value and count are the same;

		$display("test: %M: MI_SEC_TIMER");
		mi_check_sec_timer(0);
		wdata[31:16] = 16'd0;
		wdata[15:0] = $random;
		swrite(`MI_SEC_TIMER, `CPU_SIZE_4, wdata);
		sread(`MI_SEC_TIMER, `CPU_SIZE_4, rdata);
		exp = { wdata[15:0], wdata[15:0] };
		rd_check(0, exp, 32'hffff_ffff, 0);
		mi_check_sec_timer(0);

		// error info register;

		$display("test: %M: MI_ERR_INFO");
		sread(`MI_ERR_INFO, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_fff0, 0);

		// random bit register;

		$display("test: %M: MI_RANDOM");
		sread(`MI_RANDOM, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_fffe, 0);

		// video control register;

		$display("test: %M: MI_AVCTRL");
		mi_avrst_check(0);
		sread(`MI_AVCTRL, `CPU_SIZE_4, rdata);
		exp = { 6'd0, 26'h010_0003 };
		rd_check(0, exp, 32'h03ff_ffff, 0);

		// test extended intr register;

		$display("test: %M: MI_EINTR");
		sread(`MI_EINTR, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		exp[25] = vsim.fl_md;
		exp[24] = vsim.button;
		rd_check(0, exp, 32'hf8ff_ffff, 0);

		// test extended mask register;

		$display("test: %M: MI_EMASK");
		sread(`MI_EMASK, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		// virage time base;
		// check that divider decrements;

		$display("test: %M: MI_SEC_VTIME");
		sread(`MI_SEC_VTIME, `CPU_SIZE_4, rdata);
		exp = 32'd62;
		rd_check(0, exp, 32'h0000_00ff, 0);

		// test virage control registers;
		// test virage nms registers;

		vx_after_reset(0);
		vx_after_reset(1);
		vx_after_reset(2);
	end
endtask

// test virage time base divider;
// give mi 8 sysclk per read;
// test does not work if divider is smaller than two cpu reads;

task mi_sec_vtime;
	input [7:0] div;		// expected divider;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg [31:0] xdata;		// second read data;
	integer n;
	begin
		// write to timer register;
		// this shouls restart the timer clock;

		$display("test: %M: MI_SEC_VTIME divide %0d", div);
		wdata = { 24'bx, div };
		swrite(`MI_SEC_VTIME, `CPU_SIZE_4, wdata);
		sread(`MI_SEC_VTIME, `CPU_SIZE_4, rdata);
		rd_check(0, wdata, 32'h0000_00ff, 0);
		if(rdata[16] !== 1'b0)
			$display("ERROR: %t: %M: vtimer clock %b exp 0", $time, rdata[16]);

		// wait for timer clock to change to 1;

		for(n = div / 8; n > 0; n = n - 1) begin
			sread(`MI_SEC_VTIME, `CPU_SIZE_4, xdata);
			rd_check(0, wdata, 32'h0000_00ff, 0);
			if(rdata[15:8] === xdata[15:8])
				$display("ERROR: %t: %M: vtimer not decrementing, 0x%h", $time, xdata);
			if(xdata[16] === 1'b1)
				n = -1;
		end
		if(n == 0)
			$display("ERROR: %t: %M: vtimer clock %b exp 1", $time, xdata[16]);
	end
endtask

// test mi video control register;

task mi_avctrl;
	reg [31:0] rdata;		// read data;
	reg [31:0] exp;			// expected data;
	begin
		// take av out of reset;

		$display("test: %M: MI_AVCTRL, rw");
		exp = { 6'bx, 26'h2aa_aaaa };
		swrite(`MI_AVCTRL, `CPU_SIZE_4, exp);
		sread(`MI_AVCTRL, `CPU_SIZE_4, rdata);
		rd_check(0, exp, 32'h03ff_ffff, 0);
		mi_avrst_check(1);

		// put av back into reset;

		$display("test: %M: MI_AVCTRL, rw");
		exp = { 6'bx, 26'h155_5555 };
		swrite(`MI_AVCTRL, `CPU_SIZE_4, exp);
		sread(`MI_AVCTRL, `CPU_SIZE_4, rdata);
		rd_check(0, exp, 32'h03ff_ffff, 0);
		mi_avrst_check(0);
	end
endtask


// test mi control register;

task mi_ctrl;
	reg [31:0] wdata;		// write data;
	reg [2:0] div;			// new divmode;
	begin
		// test rw bits;

		test_reg(`MI_CTRL, 32'h000f_e000, 32'hffff_e7ff, 32'd0);
		div = 3'b010;

		// test soft reset;

		$display("test: %M: soft reset");
		wdata = { 12'd0, 7'b0000000, 2'b10, 3'bxxx, 8'd0 };
		swrite(`MI_CTRL, `CPU_SIZE_4, wdata);
		swrite(`MI_CTRL, `CPU_SIZE_4, wdata);
		mi_check_rst(1, 0, 3'b000);
		wait_out_of_reset;
		mi_after_reset(3'b000);

		// test hard reset;

		$display("test: %M: hard reset");
		wdata = { 12'd0, 7'b0000000, 2'bx1, div, 8'd0 };
		swrite(`MI_CTRL, `CPU_SIZE_4, wdata);
		swrite(`MI_CTRL, `CPU_SIZE_4, wdata);
		mi_check_rst(0, 0, div);
		wait_out_of_reset;
		mi_after_reset(div);

	end
endtask

// test interrupt mask register;
// word sfor both MI_MASK or MI_EMASK;

task mi_intr_mask;
	input [31:0] addr;		// register address;
	input [4:0] nmask;		// # of mask bits to test;
	reg [31:0] wdata;		// write data;
	reg [31:0] mask;		// expected intr mask;
	reg [31:0] rdata;		// read data;
	reg [4:0] n;
	begin
		// clear all bits at once;

		$display("test: %M: addr 0x%h", addr);
		$display("test: %M: clear all");
		wdata = 32'h5555_5555;
		swrite(addr, `CPU_SIZE_4, wdata);
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'd0, 32'hffff_ffff, 0);

		// set each bit, one by one;

		mask = 0;
		for(n = 0; n <= 13; n = n + 1) begin
			$display("test: %M: set mask %0d", n);
			wdata = 1 << ((n * 2) + 1);
			swrite(addr, `CPU_SIZE_4, wdata);
			if(n < nmask)
				mask = mask | (1 << n);
			sread(addr, `CPU_SIZE_4, rdata);
			rd_check(0, mask, 32'hffff_ffff, 0);
		end

		// clear all mask bits, on by one;

		for(n = 0; n <= 13; n = n + 1) begin
			$display("test: %M: clear mask %0d", n);
			wdata = 1 << (n * 2);
			swrite(addr, `CPU_SIZE_4, wdata);
			if(n < nmask)
				mask = mask & ~(1 << n);
			sread(addr, `CPU_SIZE_4, rdata);
			rd_check(0, mask, 32'hffff_ffff, 0);
		end

		// set all mask bits at once;
		// test that all 0s and all 1s do not change mask;

		$display("test: %M: no modification");
		wdata = 32'h0aaa_aaaa;
		swrite(addr, `CPU_SIZE_4, wdata);
		swrite(addr, `CPU_SIZE_4, 32'h0000_0000);
		swrite(addr, `CPU_SIZE_4, 32'hffff_ffff);
		sread(addr, `CPU_SIZE_4, rdata);
		mask = 32'hffff_ffff >> (32 - nmask);
		rd_check(0, mask, 32'hffff_ffff, 0);
	end
endtask

// check kick of secure mode;

task mi_sec_mode_kick;
	input exp_nmi;			// expected nmi;
	reg [31:0] rdata;		// read data;
	begin
		$display("%t: %M", $time);
		mi_check_nmi(exp_nmi, 0);
		mi_check_secure(0);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		rd_check(0, 32'd0, 32'hffff_ffff, 0);
		mi_check_nmi(0, 0);
		mi_check_secure(0);
	end
endtask

// check entering of secure mode;

task mi_sec_mode_enter;
	input exp_nmi;			// expected nmi;
	reg [31:0] rdata;		// read data;
	begin
		// nmi should be as expected, but secure mode not on yet;
		// single read from 1fc0_0000 should turn on secure mode;
		// read must return first word from boot space;

		$display("%t: %M", $time);
		mi_check_nmi(exp_nmi, 0);
		mi_check_secure(0);
		sread(`BASE_BOOT, `CPU_SIZE_4, rdata);
		rd_check(0, mi_boot_word, 32'hffff_ffff, 0);
		mi_check_nmi(exp_nmi, 0);
		mi_check_secure(1);
	end
endtask

// set boot word;

task mi_set_boot_word;
	input reset;
	begin
		if(reset)
			mi_boot_word = mi_brom_data[0];
		else
			sread(`MI_BRAM_FLIP, `CPU_SIZE_4, mi_boot_word);
	end
endtask

// check leaving of secure mode;

task mi_sec_mode_leave;
	reg [31:0] mode;		// secure mode data;
	begin
		// nmi should be deasserted after leaving;
		// do not touch IRAM_EN, SBUT_EN and RESET bits;
		// update boot word based on RESET bit;

		$display("%t: %M", $time);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, mode);
		mode[7:2] = 6'd0;
		mode[0] = 0;
		mi_set_boot_word(mode[1]);
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, mode);
		mi_check_nmi(1, 2);
		mi_check_secure(0);
	end
endtask

// check software assertion of nmi;

task mi_check_nmi_force;
	input [7:2] wdata;		// secure mode reg write data;
	reg [31:0] rdata;		// read data;
	reg [31:0] exp;			// expected data;
	reg exp_nmi;			// expect a nmi;
	begin
`ifdef	SIMGATE
		$display("test: %M: Warning: not done on gate-level");
`else	// SIMGATE
		$display("test: %M: 0x%h", wdata);
		exp_nmi = ~|wdata;
		vsim.bb.bcp.mi.sec_mode[7:2] = wdata;
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, { 5'bx, 3'd0, 16'bx, 6'b111111, 2'b01 });
		mi_check_nmi(exp_nmi, 2);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		exp = { 5'd0, 3'd0, 16'd0, wdata, 2'b01 };
		rd_check(0, exp, 32'hffff_ffff, 0);
		mi_check_nmi(exp_nmi, 0);
`endif	// SIMGATE
	end
endtask

// test secure mode functionality;
// returns in secure mode;

task mi_sec_mode;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	begin
		// check that 0ing SFATAL, STIMER and SAPP deassert nmi;
		// clear out all state, except secure mode;

		$display("test: %M: check nmi re-enable");
		wdata = { 5'bx, 3'd0, 16'bx, 8'b0000_0001 };
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, wdata);
		mi_check_nmi(1, 2);

		// check that reading MI_SEC_MODE returns current state
		// and that it does not trigger entering of secure mode
		// in secure mode;

		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		wdata = { 5'd0, 3'd0, 16'd0, 8'b0000_0001 };
		rd_check(0, wdata, 32'hffff_ffff, 0);
		mi_check_nmi(1, 0);

		// check that setting SMD, SBUT, STRAP, SFATAL, STIMER or SAPP assert nmi;

		mi_check_nmi_force(6'b100000);
		mi_check_nmi_force(6'b000000);
		mi_check_nmi_force(6'b010000);
		mi_check_nmi_force(6'b000000);
		mi_check_nmi_force(6'b001000);
		mi_check_nmi_force(6'b000000);
		mi_check_nmi_force(6'b000100);
		mi_check_nmi_force(6'b000000);
		mi_check_nmi_force(6'b000010);
		mi_check_nmi_force(6'b000000);
		mi_check_nmi_force(6'b000001);
		mi_check_nmi_force(6'b000000);
	end
endtask

// check button sts/intr in MI_EINTR;

task mi_button_check;
	input exp_sts;		// expected button status;
	input exp_intr;		// expected button intr;
	reg [31:0] rdata;		// read data;
	begin
		sread(`MI_EINTR, `CPU_SIZE_4, rdata);
		if(rdata[24] !== exp_sts) begin
			$display("ERROR: %t: %M: MI_EINTR button sts %b exp %b",
				$time, rdata[24], exp_sts);
		end
		if(rdata[12] !== exp_intr) begin
			$display("ERROR: %t: %M: MI_EINTR button intr %b exp %b",
				$time, rdata[12], exp_intr);
		end
	end
endtask

// test button interrupt/pre-nmi;
// must be in secure mode to test;

task mi_button_test;
	input trap;				// test button trap;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	integer n;
	begin
		// check button timer;
		// release button press that powered on system;
		// set si joy channel clock to fastest;
		// clear button mask to clear previous interrupts;

		$display("test: %M");
		vsim.button = 0;
		mi_cbus_mon(1, 0, 0);
		swrite(`SI_CONFIG, `CPU_SIZE_4, 32'h0);
		swrite(`MI_EMASK, `CPU_SIZE_4, 32'h0100_0000);
		swrite(`MI_EMASK, `CPU_SIZE_4, 32'h0200_0000);
		mi_check_intr(`INTR_BUT, 1);
		mi_cbus_mon(0, 0, 0);

		// enable secure button trap;
		// assumed to be called in non-secure mode;

		if(trap) begin
			if(vsim.bb.bcp.mi.secure === 0)
				mi_sec_mode_enter(0);
			sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
			rdata[25] = 1;
			rdata[6] = 0;
			swrite(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
			sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
			if(rdata[25] !== 1)
				$display("ERROR: %t: %M: MI_SEC_MODE SBUT_EN %b, exp 1", $time, rdata[25]);
			if(rdata[6] !== 0)
				$display("ERROR: %t: %M: MI_SEC_MODE SBUT %b, exp 0", $time, rdata[6]);
		end

		// push button;
		// check button intr assertion;
		// check MI_EINTR button and interrupt status;

		$display("test: %M: button push");
		vsim.button = 1;
		mi_but_time = $time;
		repeat(5) @(posedge sysclk);
		mi_check_intr(`INTR_BUT, 0);
		mi_button_check(1, 1);

		// release button;
		// check button intr deassertion;
		// check MI_EINTR button and interrupt status;

		$display("test: %M: button release");
		vsim.button = 0;
		repeat(5) @(posedge sysclk);
		mi_check_intr(`INTR_BUT, 0);
		mi_button_check(0, 1);

		// test secure trap;

		if(trap)
			mi_button_finish;

		// clear button interrupt status;
		// check MI_EINTR button and interrupt status;
		// not for button trap testing;

		$display("test: %M: button intr clear");
		swrite(`MI_EMASK, `CPU_SIZE_4, 32'h0100_0000);
		mi_button_check(0, 0);
		mi_check_intr(`INTR_BUT, 1);
	end
endtask

// finish button test;
// this must be run before the button timer expires;

task mi_button_finish;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg [63:0] dt;			// time delta;
	integer n;
	begin
		// leave secure mode;
		// wait for timer to trap, nmi is only indication;
		// timer must tick for 2^20 clocks;

		$display("test: %M: waiting for button trap");
		dt = $time - mi_but_time;
		dt = ((dt * 1000) / vsim.sysclk_period) >> 10;
		if(vsim.bb.bcp.mi.secure === 1)
			mi_sec_mode_leave;
		for(n = 1025 - dt; n >= 0; n = n - 1) begin
			if((nmi_l === 1'b0) & (n > 1))
				$display("ERROR: %t: %M: premature button trap, n=%0d", $time, n);
			repeat(1024) @(posedge sysclk);
		end

		// reenter secure mode;
		// check that button trap is set;

		mi_sec_mode_enter(0);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		if(rdata[6] !== 1)
			$display("ERROR: %t: %M: SBUT %b exp 1", $time, rdata[6]);

		// disable button timer;

		$display("test: %M: disabling button trap");
		rdata[25] = 0;
		rdata[6] = 0;
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		mi_check_nmi(1, 0);
		if(rdata[25] !== 0)
			$display("ERROR: %t: %M: MI_SEC_MODE SBUT_EN %b, exp 0", $time, rdata[25]);
		if(rdata[6] !== 0)
			$display("ERROR: %t: %M: MI_SEC_MODE SBUT %b, exp 0", $time, rdata[6]);
	end
endtask

// test secure mode timer;
// must be called in secure mode;

task mi_sec_timer;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg tdec;				// timer decrements;
	begin
		// initialize secure timer;
		// set fastest pre-scaler, x2;
		// set timer so that the non-secure tests finish
		// before the timer goes off and triggers nmi;

		$display("test: %M: secure timer trigger");
		wdata[31:16] = 16'd1;
		wdata[15:0] = 16'd16;
		swrite(`MI_SEC_TIMER, `CPU_SIZE_4, wdata);

		// check that timer value is corect;
		// check that timer counter decrements;

		req_spacing(4);
		sread(`MI_SEC_TIMER, `CPU_SIZE_4, rdata);
		mi_check_sec_timer(1);
		if(rdata[15:0] !== wdata[15:0]) begin
			$display("ERROR: %t: %M: secure timer value 0x%h exp 0x%h",
				$time, rdata[15:0], wdata[15:0]);
		end
		tdec = (rdata[31:16] < wdata[15:0]) & (rdata[31:16] >= 16'd0);
		if( !tdec) begin
			$display("ERROR: %t: %M: secure timer decrement 0x%h from 0x%h", 
				$time, rdata[31:16], wdata[15:0]);
		end

		// leave secure mode;
		// writes to MI_SEC_TIMER should be dropped;
		// reads must return 0;

		mi_sec_mode_leave;
		swrite(`MI_SEC_TIMER, `CPU_SIZE_4, 32'bx);
		sread(`MI_SEC_TIMER, `CPU_SIZE_4, rdata);
		rd_check(0, 32'd0, 32'hffff_ffff, 0);

		// secure timer should have gone off;
		// enter secure mode by doing the boot fetch;
		// write in non-secure should have been ignored;

		mi_check_sec_timer(1);
		mi_check_nmi(1, 0);
		repeat(16*2) @(posedge sysclk);
		mi_sec_mode_enter(0);
		sread(`MI_SEC_TIMER, `CPU_SIZE_4, rdata);
		rd_check(0, wdata, 32'h0000_ffff, 0);

		// disable secure timer;

		wdata[31:16] = 16'd0;
		wdata[15:0] = $random;
		swrite(`MI_SEC_TIMER, `CPU_SIZE_4, wdata);
		sread(`MI_SEC_TIMER, `CPU_SIZE_4, rdata);
		mi_check_sec_timer(0);
		rd_check(0, wdata, 32'h0000_ffff, 0);
	end
endtask

// targeted test for single requests to memory;

task mi_mem_sglwalk;
	input [31:0] space;			// address space;
	input [5:0] nabits;			// # of address bits;
	input [1:0] size;			// data size;
	input reqspc;				// use random request spacing;
	reg [31:0] addr;			// address;
	reg [31:0] amask;			// address mask;
	reg [31:0] saddr [2:29];	// single address;
	reg [31:0] sdata [2:29];	// single data;
	reg [31:0] smask [2:29];	// single data mask;
	integer n;
	begin
		// test writes;

		$display("test: %M: space 0x%h, size %0d, spacing %b", space, size + 1, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[1:0] = 2'b00;

		// walk one address bit;
		// randomize request spacing and data;

		$display("test: %M: write, addr walking 1");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[1:0] = sgl_addr(size);
			saddr[n] = addr;
			sdata[n] = $random;
			smask[n] = sgl_mask(addr[1:0], size);
			if(reqspc)
				req_spacing($random);
			swrite(addr, size, sdata[n]);
		end

		$display("test: %M: write, addr walking 0");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = saddr[n];
			addr = addr ^ amask;
			if(reqspc)
				req_spacing($random);
			swrite(addr, size, ~sdata[n]);
		end

		// read back single data and check;

		$display("test: %M: compare, addr walking 1");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = saddr[n];
			if(reqspc)
				req_spacing($random);
			sread(addr, size, data[0]);
			rd_check(0, sdata[n], smask[n], 0);
		end

		$display("test: %M: compare, addr walking 0");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = saddr[n];
			addr = addr ^ amask;
			if(reqspc)
				req_spacing($random);
			sread(addr, size, data[0]);
			rd_check(0, ~sdata[n], smask[n], 0);
		end
	end
endtask

// targeted test for single requests to memory;

task mi_mem_blkwalk;
	input [31:0] space;			// address space;
	input [5:0] nabits;			// # of address bits;
	input [1:0] size;			// data size;
	input reqspc;				// use random request spacing;
	reg [31:0] addr;			// address;
	reg [31:0] amask;			// address mask;
	reg [31:0] baddr [2:29];	// block address;
	reg [31:0] bdata [2:29];	// block data;
	integer n;
	begin
		// test writes;

		$display("test: %M: space 0x%h, size %0d, spacing %b", space, 8 << size, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'd0;

		// walk one address bit;
		// randomize request spacing and data;

		$display("test: %M: write, addr walking 1");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[4:2] = blk_addr(size);
			baddr[n] = addr;
			bdata[n] = $random;
			if(reqspc)
				req_spacing($random);
			blk_data(bdata[n]);
			bwrite(addr, size);
		end

		$display("test: %M: write, addr walking 0");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = baddr[n];
			addr = addr ^ amask;
			if(reqspc)
				req_spacing($random);
			blk_data(~bdata[n]);
			bwrite(addr, size);
		end

		// read back block data and check;
		// read through same space it was written into;

		$display("test: %M: compare, addr walking 1");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = baddr[n];
			if(reqspc)
				req_spacing($random);
			bread(addr, size);
			blk_check(size, bdata[n], 0, 3'b000);
		end

		$display("test: %M: compare, addr walking 0");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = baddr[n];
			addr = addr ^ amask;
			if(reqspc)
				req_spacing($random);
			bread(addr, size);
			blk_check(size, ~bdata[n], 0, 3'b000);
		end
	end
endtask

// test sub-block order;
// the r4300 aligns physical addresses on doubleword boundaries;
// address bits [2:0] are always 0;

task mi_mem_subblk;
	input [31:0] space;			// address space;
	input [5:0] nabits;			// # of address bits;
	input [1:0] size;			// data size;
	input reqspc;				// use random request spacing;
	reg [31:0] addr;			// block address;
	reg [31:0] amask;			// address mask;
	reg [4:2] waddr;			// write word address;
	reg [31:0] bdata;			// block data;
	integer nx;					// # of random tests;
	integer n, ndw;				// double word index;
	begin
		// only for block reads;
		// block writes are always sequential;
		// use fixed number of random cachelines;

		$display("test: %M: space 0x%h, size %0d, spacing %b", space, 8 << size, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'd0;

		// write sequential;
		// pick random address and data;

		for(nx = 0; nx < `MI_N_SUBBLK; nx = nx + 1) begin
			addr = space | ($random & amask);
			waddr = blk_addr(size);
			addr[4:2] = waddr;
			$display("test: %M: write sequential, addr 0x%h", addr);
			bdata = $random;
			blk_data(bdata);
			if(reqspc)
				req_spacing($random);
			bwrite(addr, size);

			// read and compare all subblock orders;

			ndw = (1 << size);
			for(n = 0; n < ndw; n = n + 1) begin
				addr[4:2] = waddr | (n << 1);
				$display("test: %M: read subblock %h", addr[4:3]);
				if(reqspc)
					req_spacing($random);
				bread(addr, size);
				blk_check(size, bdata, 0, n << 1);
			end
		end
	end
endtask

// check rom with single reads;

task mi_rom_sgl;
	input [31:0] space;		// address space;
	input [5:0] nabits;		// # of address bits;
	input [1:0] size;		// data size;
	input reqspc;			// use random request spacing;
	reg [31:0] addr;		// address;
	reg [31:0] amask;		// address mask;
	reg [31:0] smask;		// byte mask;
	reg [13:2] raddr;		// rom address;
	integer n;
	begin
		$display("test: %M: size %0d, spacing %b", size + 1, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[1:0] = 2'b00;

		$display("test: %M: compare, addr walking 1");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[1:0] = sgl_addr(size);
			smask = sgl_mask(addr[1:0], size);
			raddr = addr[13:2];
			if(reqspc)
				req_spacing($random);
			sread(addr, size, data[0]);
			rd_check(0, mi_brom_data[raddr], smask, 0);
		end

		$display("test: %M: compare, addr walking 0");
		for(n = 2; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[1:0] = sgl_addr(size);
			addr = addr ^ amask;
			smask = sgl_mask(addr[1:0], size);
			raddr = addr[13:2];
			if(reqspc)
				req_spacing($random);
			sread(addr, size, data[0]);
			rd_check(0, mi_brom_data[raddr], smask, 0);
		end
	end
endtask

// check rom block response;

task mi_rom_blk_check;
	input [1:0] size;		// data size;
	input [13:2] raddr;		// rom address;
	input err;				// expect error;
	integer n;
	begin
		if(size == `CPU_SIZE_RSVD)
			$display("ERROR: %t: %M: blk size %b", $time, size);
		rd_check(0, mi_brom_data[raddr ^ 0], 32'hffffffff, err);
		rd_check(1, mi_brom_data[raddr ^ 1], 32'hffffffff, err);
		if((size == `CPU_SIZE_16) | (size == `CPU_SIZE_32)) begin
			rd_check(2, mi_brom_data[raddr ^ 2], 32'hffffffff, err);
			rd_check(3, mi_brom_data[raddr ^ 3], 32'hffffffff, err);
		end
		if(size == `CPU_SIZE_32) begin
			rd_check(4, mi_brom_data[raddr ^ 4], 32'hffffffff, err);
			rd_check(5, mi_brom_data[raddr ^ 5], 32'hffffffff, err);
			rd_check(6, mi_brom_data[raddr ^ 6], 32'hffffffff, err);
			rd_check(7, mi_brom_data[raddr ^ 7], 32'hffffffff, err);
		end
	end
endtask

// check rom with block reads;

task mi_rom_blk;
	input [31:0] space;		// address space;
	input [5:0] nabits;		// # of address bits;
	input [1:0] size;		// data size;
	input reqspc;			// use random request spacing;
	reg [31:0] addr;		// address;
	reg [31:0] amask;		// address mask;
	reg [13:2] raddr;		// rom address;
	integer n;
	begin
		$display("test: %M: size %0d, spacing %b", size + 1, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'b00;

		// read back block data and check;
		// read through same space it was written into;

		$display("test: %M: compare, addr walking 1");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[4:2] = blk_addr(size);
			if(reqspc)
				req_spacing($random);
			bread(addr, size);
			mi_rom_blk_check(size, addr[13:2], 0);
		end

		$display("test: %M: compare, addr walking 0");
		for(n = 5; n < nabits; n = n + 1) begin
			addr = space | (1 << n);
			addr[4:2] = blk_addr(size);
			addr = addr ^ amask;
			if(reqspc)
				req_spacing($random);
			bread(addr, size);
			mi_rom_blk_check(size, addr[13:2], 0);
		end
	end
endtask

// test rom sub-block order;

task mi_rom_subblk;
	input [31:0] space;			// address space;
	input [5:0] nabits;			// # of address bits;
	input [1:0] size;			// data size;
	input reqspc;				// use random request spacing;
	reg [31:0] addr;			// block address;
	reg [31:0] amask;			// address mask;
	reg [4:2] waddr;			// write word address;
	integer nx;					// # of random tests;
	integer n, ndw;				// double word index;
	begin
		// only for block reads;
		// block writes are always sequential;
		// use fixed number of random cachelines;

		$display("test: %M: space 0x%h, size %0d, spacing %b", space, 8 << size, reqspc);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'd0;

		// pick random addresses;
		// read and compare all subblock orders;

		for(nx = 0; nx < `MI_N_SUBBLK; nx = nx + 1) begin
			addr = space | ($random & amask);
			waddr = blk_addr(size);
			ndw = (1 << size);
			for(n = 0; n < ndw; n = n + 1) begin
				addr[4:2] = waddr | (n << 1);
				$display("test: %M: read subblock %h", addr[4:3]);
				if(reqspc)
					req_spacing($random);
				bread(addr, size);
				mi_rom_blk_check(size, addr[13:2], 0);
			end
		end
	end
endtask

// fill memory with pattern;
// increasing number of 1s in address;
// fill with d-cache writes (sequential);
// used for touch test;

task mi_mem_fill_pat;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input [31:0] pxor;		// patterrn xor;
	integer n;
	begin
		$display("test: %M: space 0x%h", addr);
		addr = addr & (32'hffff_ffff << nabits);
		for(n = 4; n <= nabits; n = n + 1) begin
			req_spacing($random);
			blk_data(addr ^ pxor);
			bwrite(addr, `CPU_SIZE_16);
			addr = addr | (1 << n);
			pxor = { pxor[30:0], pxor[31] };
		end
	end
endtask

// compare memory with pattern;
// increasing number of 1s in address;
// read d-cache size with random sub-block order;
// used for touch test;

task mi_mem_cmp_pat;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input [31:0] pxor;		// patterrn xor;
	reg [2:0] sbo;			// subblock order;
	integer n;
	begin
		$display("test: %M: space 0x%h", addr);
		addr = addr & (32'hffff_ffff << nabits);
		sbo[2] = 0;
		for(n = 4; n <= nabits; n = n + 1) begin
			sbo[1:0] = $random;
			req_spacing($random);
			addr[3:2] = sbo[1:0];
			bread(addr, `CPU_SIZE_16);
			addr[3:2] = 2'b00;
			blk_check(`CPU_SIZE_16, addr ^ pxor, 0, sbo);
			addr = addr | (1 << n);
			pxor = { pxor[30:0], pxor[31] };
		end
	end
endtask

// check that memory pattern is 0;
// increasing number of 1s in address;
// block reads with random size and sub-block order;
// randomize lower address bits for cover more space;
// used for touch test;

task mi_mem_cmp_zero;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	reg [1:0] size;			// request size;
	integer n, w;
	begin
		$display("test: %M: space 0x%h", addr);
		addr = addr & (32'hffff_ffff << nabits);
		for(n = 5; n <= nabits; n = n + 1) begin
			size = $random;
			while(size == 2'b11)
				size = $random;
			addr = addr ^ ($random & (32'hffff_ffff >> (32 - n)));
			addr[2:0] = 3'd0;
			req_spacing($random);
			bread(addr, size);
			addr[4:3] = 2'b00;
			for(w = 0; w < (2 << size); w = w + 1)
				rd_check(0, 32'd0, 32'hffffffff, 0);
			addr = addr | (1 << n);
		end
	end
endtask

// check access rights of memory region;
// must be called in secure mode;

task mi_mem_access;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input nsena;			// device enabled in non-secure mode;
	input [31:0] pxor;		// patterrn xor;
	reg [31:0] rdata;		// read data;
	begin
		// setup test pattern;
		// leave secure mode;

		$display("test: %M: space 0x%h, nsena %b", addr, nsena);
		mi_mem_fill_pat(addr, nabits, pxor);
		mi_sec_mode_leave;

		// if device is enabled in non-secure mode;
		// then pattern should match;

		if(nsena)
			mi_mem_cmp_pat(addr, nabits, pxor);

		// if device is disabled in non-secure mode;
		// writes with new test pattern should be ignored;
		// reads from region should return 0;

		else begin
			mi_mem_fill_pat(addr, nabits, $random);
			mi_mem_cmp_zero(addr, nabits);
		end

		// enter secure mode by application;
		// check that original pattern is unmodified;

		mi_sec_mode_kick(1);
		mi_sec_mode_enter(0);
		mi_mem_cmp_pat(addr, nabits, pxor);
	end
endtask

// check access rights of rom region;
// must be called in secure mode;

task mi_rom_access;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input [31:0] pxor;		// patterrn xor;
	reg [31:0] rdata;		// read data;
	begin
		// leave secure mode;

		$display("test: %M: space 0x%h", addr);
		mi_sec_mode_leave;

		// writes should be dropped in secure mode;
		// reads from region should return 0;

		mi_mem_cmp_zero(addr, nabits);

		// enter secure mode by application;
		// check that original pattern is unmodified;

		mi_sec_mode_kick(1);
		mi_sec_mode_enter(0);
	end
endtask

// test brom;
// must be in secure mode;

task mi_brom;
	reg [31:0] wdata;	// write data;
	integer sz;			// request size;
	begin
		// set RESET bit in MI_SEC_MODE register;
		// test bram in reset space;

		wdata = { 5'bx, 3'd0, 16'bx, 8'b0000_0011 };
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, wdata);

		$display("test: %M: reset space, single reads");
		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_rom_sgl(`MI_BROM_RST, `MI_NA_BROM, sz, 0);
			mi_rom_sgl(`MI_BROM_RST, `MI_NA_BROM, sz, 1);
		end

		$display("test: %M: reset space, block reads");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_rom_blk(`MI_BROM_RST, `MI_NA_BROM, sz, 0);
			mi_rom_blk(`MI_BROM_RST, `MI_NA_BROM, sz, 1);
		end

		$display("test: %M: reset space, subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_rom_subblk(`MI_BROM_RST, `MI_NA_BROM, sz, 0);
			mi_rom_subblk(`MI_BROM_RST, `MI_NA_BROM, sz, 1);
		end

		// check access restrictions;

		mi_rom_access(`MI_BROM_RST, `MI_NA_BROM, $random);

		// clear RESET bit to flip address spaces;
		// test bram in flip space;

		wdata = { 5'bx, 3'd0, 16'bx, 8'b0000_0001 };
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, wdata);

		$display("test: %M: flip space, single requests");
		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_rom_sgl(`MI_BROM_FLIP, `MI_NA_BROM, sz, 0);
			mi_rom_sgl(`MI_BROM_FLIP, `MI_NA_BROM, sz, 1);
		end

		$display("test: %M: flip space, block requests");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_rom_blk(`MI_BROM_FLIP, `MI_NA_BROM, sz, 0);
			mi_rom_blk(`MI_BROM_FLIP, `MI_NA_BROM, sz, 1);
		end

		$display("test: %M: flip space, subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_rom_subblk(`MI_BROM_FLIP, `MI_NA_BROM, sz, 0);
			mi_rom_subblk(`MI_BROM_FLIP, `MI_NA_BROM, sz, 1);
		end

		// check access restrictions;

		mi_rom_access(`MI_BROM_FLIP, `MI_NA_BROM, $random);
	end
endtask

// test bram;
// must be in secure mode;

task mi_bram;
	reg [31:0] wdata;	// write data;
	integer sz;			// request size;
	begin
		// set RESET bit in MI_SEC_MODE register;
		// test bram in reset space;

		wdata = { 5'bx, 3'd0, 16'bx, 8'b0000_0011 };
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, wdata);

		$display("test: %M: reset space, single requests");
		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_mem_sglwalk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 0);
			mi_mem_sglwalk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 1);
		end

		$display("test: %M: reset space, block requests");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_blkwalk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 0);
			mi_mem_blkwalk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 1);
		end

		$display("test: %M: reset space, subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_subblk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 0);
			mi_mem_subblk(`MI_BRAM_RST, `MI_NA_BRAM, sz, 1);
		end

		// check access restrictions;

		mi_mem_access(`MI_BRAM_RST, `MI_NA_BRAM, 0, $random);

		// clear RESET bit to flip address spaces;
		// test bram in flip space;

		wdata = { 5'bx, 3'd0, 16'bx, 8'b0000_0001 };
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, wdata);

		$display("test: %M: flip space, single requests");
		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_mem_sglwalk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 0);
			mi_mem_sglwalk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 1);
		end

		$display("test: %M: flip space, block requests");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_blkwalk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 0);
			mi_mem_blkwalk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 1);
		end

		$display("test: %M: flip space, subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_subblk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 0);
			mi_mem_subblk(`MI_BRAM_FLIP, `MI_NA_BRAM, sz, 1);
		end

		// check access restrictions;

		mi_mem_access(`MI_BRAM_FLIP, `MI_NA_BRAM, 0, $random);
	end
endtask

// test iram;

task mi_iram;
	integer sz;			// request size;
	reg [31:0] val;		// read/write value;
	begin
		// check access types;

		$display("test: %M: single requests");
		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_mem_sglwalk(`MI_IRAM, `MI_NA_IRAM, sz, 0);
			mi_mem_sglwalk(`MI_IRAM, `MI_NA_IRAM, sz, 1);
		end

		$display("test: %M: block requests");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_blkwalk(`MI_IRAM, `MI_NA_IRAM, sz, 0);
			mi_mem_blkwalk(`MI_IRAM, `MI_NA_IRAM, sz, 1);
		end

		$display("test: %M: subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_subblk(`MI_IRAM, `MI_NA_IRAM, sz, 0);
			mi_mem_subblk(`MI_IRAM, `MI_NA_IRAM, sz, 1);
		end

		// check access restrictions;
		// based on IRAM_EN bit in MI_SEC_MODE;

		sread(`MI_SEC_MODE, `CPU_SIZE_4, val);
		val[24] = 0;
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, val);
		mi_mem_access(`MI_IRAM, `MI_NA_IRAM, 0, $random);
		val[24] = 1;
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, val);
		mi_mem_access(`MI_IRAM, `MI_NA_IRAM, 1, $random);
	end
endtask

// test virage registers after reset;

task vx_after_reset;
	input [1:0] vspc;	// virage space;
	reg [31:0] addr;	// address;
	reg [31:0] exp;		// expected data;
	reg [31:0] rdata;	// read data;
	begin
		// test control register default;
		// charge-pump porst has gone inactive before here;
		// nms reset to charge-pump must be 1;

		$display("test: %M: MI_VCTRL%0d", vspc);
		if(mi_porst[vspc] !== 1)
			$display("ERROR: %t: %M: v_porst[%0d] did not pulse", $time, vspc);
		addr = `MI_VCTRL0;
		addr[17:16] = vspc;
		sread(addr, `CPU_SIZE_4, rdata);
		if(vspc == 2) begin
			exp = 32'b10x0_0000_xx10_x000_0001_10xx_xxxx_0000;
			rd_check(0, exp, 32'hdf37_fc0f, 0);
		end else begin
			exp = 32'b00x0_0000_xx00_x000_0001_10xx_xxxx_0000;
			rd_check(0, exp, 32'hdf37_fc0f, 0);
		end

		// clear v2 bypass mode;

		if(vspc == 2)
			swrite(addr, `CPU_SIZE_4, 32'd0);

		// test nms register defaults;
		// this works independent of nms bypass;

		addr = `MI_VREG0;
		addr[17:16] = vspc;

		$display("test: %M: MI_VREG%0d CRSTO_0", vspc);
		addr[4:2] = 0;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b0000_0001, 32'h0000_00ff, 0);

		$display("test: %M: MI_VREG%0d CRSTO_1", vspc);
		addr[4:2] = 1;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b0001_0010, 32'h0000_00ff, 0);

		$display("test: %M: MI_VREG%0d CRM_0", vspc);
		addr[4:2] = 2;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b1001_0000, 32'h0000_00ff, 0);

		$display("test: %M: MI_VREG%0d CRM_1", vspc);
		addr[4:2] = 3;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b1001_0110, 32'h0000_00ff, 0);

		$display("test: %M: MI_VREG%0d CRM_2", vspc);
		addr[4:2] = 4;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b0101_1001, 32'h0000_00ff, 0);

		$display("test: %M: MI_VREG%0d CRM_3", vspc);
		addr[4:2] = 5;
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'b0001_0101, 32'h0000_00ff, 0);
	end
endtask

// test virage memories;

task mi_vmem;
	input [1:0] vspc;	// virage space;
	input [5:0] nabits;	// # of address bits;
	reg [31:0] addr;	// address;
	integer sz;			// request size;
	begin
		// only 32-bit single requests are supported;

		$display("test: %M: v%0d, single requests", vspc);
		addr = `MI_VMEM0;
		addr[17:16] = vspc;
		mi_mem_sglwalk(addr, nabits, 3, 0);
		mi_mem_sglwalk(addr, nabits, 3, 1);

		$display("test: %M: block requests");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_blkwalk(addr, nabits, sz, 0);
			mi_mem_blkwalk(addr, nabits, sz, 1);
		end

		$display("test: %M: subblock order");
		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_subblk(addr, nabits, sz, 0);
			mi_mem_subblk(addr, nabits, sz, 1);
		end

		// check access restrictions;

		mi_mem_access(addr, nabits, 0, $random);
	end
endtask

// fill virage sram with randoms;

task mi_fill_vmem;
	input [31:0] addr;	// virage address;
	input save_pat;		// save pattern seeds;
	reg [1:0] vspc;		// virage space;
	integer ndc;		// # of data cachelines;
	integer n;
	begin
		vspc = addr[17:16];
		$display("%t: %M: v%0d", $time, vspc);
		ndc = vspc[1]? 16 : 4;
		addr[15:0] = `MI_VMEM;
		for(n = 0; n < ndc; n = n + 1) begin
			mi_vpat[n] = $random;
			if(save_pat)
				blk_data(mi_vpat[n]);
			bwrite(addr, `CPU_SIZE_16);
			addr = addr + 16;
		end
	end
endtask

// compare virage sram with pattern;

task mi_cmp_vmem;
	input [31:0] addr;	// virage address;
	reg [1:0] vspc;		// virage space;
	integer ndc;		// # of data cachelines;
	integer n;
	begin
		vspc = addr[17:16];
		$display("%t: %M: v%0d", $time, vspc);
		ndc = vspc[1]? 16 : 4;
		addr[15:0] = `MI_VMEM;
		for(n = 0; n < ndc; n = n + 1) begin
			bread(addr, `CPU_SIZE_16);
			blk_check(`CPU_SIZE_16, mi_vpat[n], 0, 3'b000);
			addr = addr + 16;
		end
	end
endtask

// wait for nms ready;

task mi_nms_wait;
	input [1:0] vspc;	// virage space;
	input [31:0] to;	// timeout in time base ticks;
	reg [31:0] addr;	// address;
	reg [31:0] rdata;	// read data;
	integer n;
	begin
		$display("%t: %M: v%0d, to %0d ticks", $time, vspc, to);
		addr = `MI_VCTRL0;
		addr[17:16] = vspc;
		for(n = to; n > 0; n = n - 1) begin
			sread(addr, `CPU_SIZE_4, rdata);
			if(rdata[30] === 1) begin
				$display("%t: %M: nms ready", $time);
				n = 0;
			end else begin
				@(posedge vsim.bb.v_time);
			end
		end
		if(rdata[30] !== 1)
			$display("ERROR: %t: %M: nms ready timeout", $time);
	end
endtask

// test one nms command;

task mi_nms_cmd;
	input [1:0] vspc;	// virage space;
	input [2:0] cmd;	// command to test;
	input [31:0] to;	// ready timeout, us;
	input pass;			// expected pass status;
	reg [31:0] addr;	// address of ctrl reg;
	reg [31:0] wdata;	// write data;
	reg [31:0] rdata;	// read data;
	reg keep;			// keep mode expected;
	integer n;
	begin
		// check nms status;

		$display("test: %M: v%0d, cmd %0d", vspc, cmd);
		addr = `MI_VCTRL0;
		addr[17:16] = vspc;
		sread(addr, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 0)
			$display("ERROR: %t: %M: nms bypass %b", $time, rdata[31]);
		if(rdata[30] !== 1)
			$display("ERROR: %t: %M: nms ready %b exp 1", $time, rdata[30]);

		// issue command;
		// check controller busy;

		wdata[31:24] = { 5'd0, cmd };
		wdata[23:0] = $random;
		addr[13] = 1;
		swrite(addr, `CPU_SIZE_4, wdata);
		sread(addr, `CPU_SIZE_4, rdata);
		if(rdata[30] !== 0)
			$display("ERROR: %t: %M: nms ready %b exp 0", $time, rdata[30]);

		// wait for nms ready;
		// check status;

		mi_nms_wait(vspc, to);
		sread(addr, `CPU_SIZE_4, rdata);
		if(rdata[29] !== pass)
			$display("ERROR: %t: %M: nms pass %b exp %b", $time, rdata[29], pass);
		keep = (cmd == `VCMD_KEEP);
		if(rdata[28] !== keep)
			$display("ERROR: %t: %M: nms keep %b exp %b", $time, rdata[28], keep);
	end
endtask

// test virage controllers;

task mi_vx_ctrl;
	input [1:0] vspc;	// virage space;
	input [5:0] nabits;	// # of address bits;
	reg [31:0] addr;	// address;
	reg [31:0] wdata;	// write data;
	reg [31:0] rdata;	// read data;
	reg [31:0] cmd;		// nms command;
	integer n;
	begin
		// set virage time base;

		$display("test: %M: v%0d", vspc);
		wdata = 1000000 / vsim.sysclk_period;
		$display("%t: %M: setting vtime divider %0d", $time, wdata);
		swrite(`MI_SEC_VTIME, `CPU_SIZE_4, wdata);

		// wait for charge-pump power-on reset to drop;
		// wait up to 1msec according to virage spec;

		addr = `MI_VCTRL0;
		addr[17:16] = vspc;
		for(n = 1000; n > 0; n = n - 1) begin
			sread(addr, `CPU_SIZE_4, rdata);
			if(rdata[0] === 0) begin
				$display("%t: %M: v%0d charge-pump out of reset", $time, vspc);
				n = 0;
			end else begin
				@(posedge vsim.bb.v_time);
			end
		end
		if(rdata[0] !== 0)
			$display("ERROR: %M: v%0d charge-pump porst %b", $time, vspc, rdata[0]);

		// wait for nms ready;
		// delay is 8 time base clocks according to virage spec;

		mi_nms_wait(vspc, 50);

		// test nms idle command;
		// check that sram stays unmodified;

		$display("test: %M: v%0d: nms idle cmd", vspc);
		addr = `MI_VCTRL0;
		addr[17:16] = vspc;
		mi_fill_vmem(addr, 1);
		mi_nms_cmd(vspc, `VCMD_IDLE, 10, 1);
		mi_cmp_vmem(addr);

		// keep mode should not modify sram;
		// writes to sram should be dropped in keep mode;

		$display("test: %M: v%0d: nms keep mode on", vspc);
		mi_nms_cmd(vspc, `VCMD_KEEP, 40, 1);
		mi_cmp_vmem(addr);
		mi_fill_vmem(addr, 0);
		mi_cmp_vmem(addr);

		$display("test: %M: v%0d: nms keep mode off", vspc);
		mi_nms_cmd(vspc, `VCMD_IDLE, 10, 1);
		mi_cmp_vmem(addr);

		// store to novea;
		// check that sram stays unmodified;

		$display("test: %M: v%0d: nms full store", vspc);
		mi_nms_cmd(vspc, `VCMD_FSTORE, 8000, 1);
		mi_cmp_vmem(addr);

		// compare novea with sram;
		// check that sram stays unmodified;

		$display("test: %M: v%0d: nms normal compare", vspc);
		mi_nms_cmd(vspc, `VCMD_NCOMP, 10, 1);
		mi_cmp_vmem(addr);

		// fill sram with new pattern, then recall;
		// original data pattern should be restored;

		$display("test: %M: v%0d: nms normal recall", vspc);
		mi_fill_vmem(addr, 0);
		mi_nms_cmd(vspc, `VCMD_NRECALL, 10, 1);
		mi_cmp_vmem(addr);
	end
endtask

// test dram single requests;
// in all address spaces, all sizes;
// witout and with random request spacing;

task mi_dram_sgl;
	input [5:0] nabits;		// # of address bits in x64 space;
	integer sz;				// current size;
	begin
		// test all sizes through all spaces;

		for(sz = 0; sz < 4; sz = sz + 1) begin
			mi_mem_sglwalk(`BASE_DRAM36, nabits - 1, sz, 0);
			mi_mem_sglwalk(`BASE_DRAM36, nabits - 1, sz, 1);
`ifdef	MI_MEM_X64L
			mi_mem_sglwalk(`BASE_DRAM64L, nabits, sz, 0);
			mi_mem_sglwalk(`BASE_DRAM64L, nabits, sz, 1);
`endif	// MI_MEM_X64L
`ifdef	MI_MEM_X64H
			mi_mem_sglwalk(`BASE_DRAM64H, nabits, sz, 0);
			mi_mem_sglwalk(`BASE_DRAM64H, nabits, sz, 1);
`endif	// MI_MEM_X64L
		end
	end
endtask

// test dram block requests;
// in all address spaces, all sizes;
// witout and with random request spacing;

task mi_dram_blk;
	input [5:0] nabits;		// # of address bits in x64 space;
	integer sz;				// current size;
	begin
		// test all sizes through all spaces;

		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_blkwalk(`BASE_DRAM36, nabits - 1, sz, 0);
			mi_mem_blkwalk(`BASE_DRAM36, nabits - 1, sz, 1);
`ifdef	MI_MEM_X64L
			mi_mem_blkwalk(`BASE_DRAM64L, nabits, sz, 0);
			mi_mem_blkwalk(`BASE_DRAM64L, nabits, sz, 1);
`endif	// MI_MEM_X64L
`ifdef	MI_MEM_X64H
			mi_mem_blkwalk(`BASE_DRAM64H, nabits, sz, 0);
			mi_mem_blkwalk(`BASE_DRAM64H, nabits, sz, 1);
`endif	// MI_MEM_X64H
		end
	end
endtask

// test dram subblock order;
// in all address spaces, all sizes;
// witout and with random request spacing;

task mi_dram_subblk;
	input [5:0] nabits;		// # of address bits in x64 space;
	integer sz;				// current size;
	begin
		// test all sizes through all spaces;

		for(sz = 0; sz < 3; sz = sz + 1) begin
			mi_mem_subblk(`BASE_DRAM36, nabits - 1, sz, 0);
			mi_mem_subblk(`BASE_DRAM36, nabits - 1, sz, 1);
`ifdef	MI_MEM_X64L
			mi_mem_subblk(`BASE_DRAM64L, nabits, sz, 0);
			mi_mem_subblk(`BASE_DRAM64L, nabits, sz, 1);
`endif	// MI_MEM_X64L
`ifdef	MI_MEM_X64H
			mi_mem_subblk(`BASE_DRAM64H, nabits, sz, 0);
			mi_mem_subblk(`BASE_DRAM64H, nabits, sz, 1);
`endif	// MI_MEM_X64H
		end
	end
endtask

// measure cacheline read/write bandwidth;
// write pattern is address;
// read pattern is checked, so do write before read;

task mi_rwbw;
	input [3:0] mcfg;		// memory configuration;
	input [31:0] addr;		// address space;
	input write;			// measure write bandwidth;
	input [1:0] size;		// block size;
	integer nb;				// # of byte in cacheline;
	integer t0, t;			// time stamps;
	integer n;				// loop count;
	reg [31:0] addr;		// cacheline address;
	begin
		nb = 8 << size;
		$display("test: %M: mcfg %0d, addr 0x%h, size %0d, %s bw",
			mcfg, addr, nb, write? "write" : "read");
		t0 = $time;
		for(n = 0; n < 64; n = n + 1) begin
			if(write) begin
				blk_data(addr);
				bwrite(addr, size);
			end else begin
				bread(addr, size);
				blk_check(size, addr, 0, 3'b000);
			end
			addr = addr + nb;
		end
		t = $time - t0;
		$display("test: %M: addr 0x%h, size %0d, %s bw %0dMB/sec",
			addr, nb, write? "write" : "read", (64 * nb * 1000) / t);
	end
endtask

// setup for error testing;

task mi_err_setup;
	input [5:0] ena;		// error enables;
	input exitsec;			// exit secure mode;
	reg [31:0] rdata;		// read data;
	begin
		$display("%t: %M: pif %b, bnm %b", $time, ena[5:3], ena[2:0]);
		sread(`MI_CTRL, `CPU_SIZE_4, rdata);
		rdata[18:13] = ena;
		swrite(`MI_CTRL, `CPU_SIZE_4, rdata);

		// read MI_ERR_INFO to enable capture;
		// clear any pending secure mode triggers;

		sread(`MI_ERR_INFO, `CPU_SIZE_4, rdata);
		sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		rdata[7:2] = 6'd0;
		if(exitsec)
			rdata[0] = 0;
		mi_set_boot_word(rdata[1]);
		swrite(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
		mi_check_nmi(1, 2);
		mi_check_secure(~exitsec);
	end
endtask

// read test for bus errors;

task mi_bus_err;
	input [31:0] space;		// address space;
	input [5:0] nabits;		// # of address bits;
	input exp_berr;			// expect bus error;
	input wen;				// writeable space;
	input [1:0] size;		// block size;
	reg [31:0] addr;		// address;
	reg [31:0] amask;		// address mask;
	reg [31:0] bdata;		// block data pattern;
	reg [2:0] sbo;			// subblock order;
	integer n;
	begin
		// use random addresses within space;
		// fill and compare data if writeable space;
		// else, just check the error bit;

		$display("test: %M: space 0x%h, nabits %0d, size %0d, berr %b",
			space, nabits, 8 << size, exp_berr);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'd0;
		for(n = 0; n < `MI_N_BLKERR; n = n + 1) begin
			addr = space | ($random & amask);
			addr[4:2] = blk_addr(size);
			if(wen) begin
				bdata = $random;
				blk_data(bdata);
				bwrite(addr, size);
			end
			sbo = sbo_addr(size);
			addr[4:2] = addr[4:2] ^ sbo;
			req_spacing($random);
			bread(addr, size);
			if(wen)
				blk_check(size, bdata, 0, sbo);
			else
				berr_check(exp_berr);
		end
	end
endtask

// test block reads of all request sizes;

task mi_blk_rdacc;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input exp_berr;			// expect bus error;
	input wen;				// writeable space;
	integer sz;
	begin
		for(sz = 0; sz < 3; sz = sz + 1)
			mi_bus_err(addr, nabits, exp_berr, wen, sz);
	end
endtask

// test legality of block reads;

task mi_blk_reads;
	input exp_berr;			// expect bus error;
	input [5:0] nadram;		// # of memory address bits, x64 space;
	begin
		// setup mi control register;

		$display("test: %M: berr %b", exp_berr);
		mi_cbus_mon(0, 0, 0);
		mi_err_setup({ 3'b000, 2'b00, exp_berr }, 0);

		// cacheable memory spaces should never return an erorr;
		// only dma request should be on cbus;

		mi_cbus_mon(0, 0, 1);
		mi_blk_rdacc(`BASE_DRAM36, nadram - 1, 0, 1);
`ifdef	MI_MEM_X64L
		mi_blk_rdacc(`BASE_DRAM64L, nadram, 0, 1);
`endif	// MI_MEM_X64L
`ifdef	MI_MEM_X64H
		mi_blk_rdacc(`BASE_DRAM64H, nadram, 0, 1);
`endif	// MI_MEM_X64L
		mi_cbus_mon(0, 0, 0);
		mi_blk_rdacc(`MI_BROM_FLIP, `MI_NA_BROM, 0, 0);
		mi_blk_rdacc(`MI_BRAM_FLIP, `MI_NA_BRAM, 0, 1);
		mi_blk_rdacc(`MI_IRAM, `MI_NA_IRAM, 0, 1);
		mi_blk_rdacc(`MI_VMEM0, `MI_NA_VMEM0, 0, 1);
		mi_blk_rdacc(`MI_VMEM1, `MI_NA_VMEM1, 0, 1);
		mi_blk_rdacc(`MI_VMEM2, `MI_NA_VMEM2, 0, 1);

		// test old rdram config space and register spaces;

		mi_blk_rdacc(`BASE_RDCFG, `MI_NA_RDCFG, exp_berr, 0);
		mi_blk_rdacc(`BASE_SP, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_CMD, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_SPAN, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_MI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_VI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_AI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_PI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_RI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_SI, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_USB0, `MI_NA_REGS, exp_berr, 0);
		mi_blk_rdacc(`BASE_USB1, `MI_NA_REGS, exp_berr, 0);

		// test io spaces;

		mi_blk_rdacc(`BASE_IO05, 24, exp_berr, 0);
		mi_blk_rdacc(`BASE_IO06, 25, exp_berr, 0);
		mi_blk_rdacc(`BASE_IO08, 27, exp_berr, 0);
		mi_blk_rdacc(`BASE_IO10, 27, exp_berr, 0);

		// none of the above should have triggered a write error;

		mi_check_nmi(1, 2);
		mi_check_intr(`INTR_ERR, 1);
	end
endtask

// write test for write errors;

task mi_write_err;
	input [31:0] space;		// address space;
	input [5:0] nabits;		// # of address bits;
	input exp_wei;			// expect write error interrupt;
	input exp_ski;			// expect secure kernel trap;
	input wen;				// writeable space;
	input [1:0] size;		// block size;
	reg [31:0] addr;		// address;
	reg [31:0] amask;		// address mask;
	reg mult;				// force multiple error;
	reg [31:0] bdata;		// block data;
	reg [31:0] rdata;		// read data;
	reg [31:0] info;		// error info;
	reg [2:0] sbo;			// subblock order;
	integer n;
	begin
		// use random addresses within space;

		$display("test: %M: space 0x%h, nabits %0d, size %0d, wei %b, ski %b",
			space, nabits, 8 << size, exp_wei, exp_ski);
		amask = 32'hffff_ffff >> (32 - nabits);
		amask[4:0] = 5'd0;

		// run write tests;

		for(n = 0; n < `MI_N_BLKERR; n = n + 1) begin
			addr = space | ($random & amask);
			addr[4:2] = blk_addr(size);
			bdata = $random;
			blk_data(bdata);
			bwrite(addr, size);
			mult = $random;
			if(mult)
				bwrite(addr, size);

			// if writeable space then check read data;

			if(wen) begin
				sbo = sbo_addr(size);
				addr[4:2] = addr[4:2] ^ sbo;
				bread(addr, size);
				blk_check(size, bdata, 0, sbo);
			end

			// check write error interrupt and secure trap;
			// error registers must be updated for either;

			mi_check_nmi(~exp_ski, 2);
			mi_check_intr(`INTR_ERR, ~exp_wei);

			if(exp_wei | exp_ski) begin
				sread(`MI_ERR_ADDR, `CPU_SIZE_4, rdata);
				rd_check(0, addr, 32'hffff_ffff, 0);
				sread(`MI_ERR_INFO, `CPU_SIZE_4, rdata);
				info = { 27'd0, 1'b1, mult, 1'b1, size };
				rd_check(0, info, 32'hffff_ffff, 0);
			end

			// check write error intr clearance;
			// reading MI_ERR_INFO above should have cleared write error intr;
			// reading it again should have the WEVAL bit cleared;

			if(exp_wei) begin
				mi_check_intr(`INTR_ERR, 1);
				sread(`MI_ERR_INFO, `CPU_SIZE_4, rdata);
				info = { 27'd0, 1'b0, 1'bx, 1'bx, 2'bx };
				rd_check(0, info, 32'hffff_fff0, 0);
			end

			// check secure trap bit;
			// clear secure triggers to re-enable nmi;

			if(exp_ski) begin
				sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
				if(rdata[5] !== 1)
					$display("ERROR: %t: %M: STRAP %b exp 1", $time, rdata[5]);
				rdata[7:2] = 6'd0;
				swrite(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
				mi_check_nmi(1, 2);
			end

		end
	end
endtask

// test block writes of all request sizes;

task mi_blk_wracc;
	input [31:0] addr;		// address space;
	input [5:0] nabits;		// # of address bits;
	input exp_wei;			// expect write error interrupt;
	input exp_ski;			// expect secure kernel trap;
	input wen;				// writeable space;
	integer sz;
	begin
		for(sz = 0; sz < 3; sz = sz + 1)
			mi_write_err(addr, nabits, exp_wei, exp_ski, wen, sz);
	end
endtask

// test legality of block writes;

task mi_blk_writes;
	input exp_wei;			// expect write error intr;
	input exp_ski;			// expect secure kernel trap;
	input [5:0] nadram;		// # of memory address bits, x64 space;
	reg [31:0] rdata;		// read data;
	begin
		// setup mi control register;

		$display("test: %M: wei %b, ski %b", exp_wei, exp_ski);
		mi_cbus_mon(0, 0, 0);
		mi_err_setup({ 3'b000, exp_ski, exp_wei, 1'b0 }, 0);

		// cacheable memory spaces should never cause an erorr;
		// only dma request should be on cbus;

		mi_cbus_mon(0, 0, 1);
		mi_blk_wracc(`BASE_DRAM36, nadram - 1, 0, 0, 1);
`ifdef	MI_MEM_X64L
		mi_blk_wracc(`BASE_DRAM64L, nadram, 0, 0, 1);
`endif	// MI_MEM_X64L
`ifdef	MI_MEM_X64H
		mi_blk_wracc(`BASE_DRAM64H, nadram, 0, 0, 1);
`endif	// MI_MEM_X64L
		mi_cbus_mon(0, 0, 0);
		mi_blk_wracc(`MI_BROM_FLIP, `MI_NA_BROM, 0, 0, 0);
		mi_blk_wracc(`MI_BRAM_FLIP, `MI_NA_BRAM, 0, 0, 1);
		mi_blk_wracc(`MI_IRAM, `MI_NA_IRAM, 0, 0, 1);
		mi_blk_wracc(`MI_VMEM0, `MI_NA_VMEM0, 0, 0, 1);
		mi_blk_wracc(`MI_VMEM1, `MI_NA_VMEM1, 0, 0, 1);
		mi_blk_wracc(`MI_VMEM2, `MI_NA_VMEM2, 0, 0, 1);

		// test old rdram config space and register spaces;

		mi_blk_wracc(`BASE_RDCFG, `MI_NA_RDCFG, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_SP, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_CMD, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_SPAN, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_MI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_VI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_AI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_PI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_RI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_SI, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_USB0, `MI_NA_REGS, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_USB1, `MI_NA_REGS, exp_wei, exp_ski, 0);

		// test io spaces;

		mi_blk_wracc(`BASE_IO05, 24, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_IO06, 25, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_IO08, 27, exp_wei, exp_ski, 0);
		mi_blk_wracc(`BASE_IO10, 27, exp_wei, exp_ski, 0);

	end
endtask

// pif read access test;

task mi_pif_rdacc;
	input exp_berr;			// expect bus error;
	input blkreq;			// block request;
	input [1:0] size;		// block size;
	reg [31:0] addr;		// address;
	reg [31:0] rdata;		// block data pattern;
	integer n;
	begin
		// use random addresses within space;
		// just check the error bit;

		$display("test: %M: size %0d, berr %b",
			blkreq? (8 << size) : (size + 1), exp_berr);
		addr = `BASE_PIF;
		addr[5:2] = $random;
		addr[1:0] = 2'b00;
		if(blkreq) begin
			addr[2] = 0;
			bread(addr, size);
		end else
			sread(addr, size, rdata);
		berr_check(exp_berr);
	end
endtask

// test pif read trapping;

task mi_pif_reads;
	input exp_berr;			// expect bus error;
	begin
		// non of below requests should go on cbus;

		mi_cbus_mon(0, 0, 0);

		// check no trapping in secure mode;

		mi_err_setup({ 2'b00, exp_berr, 3'b000 }, 0);
		mi_pif_rdacc(0, 0, `CPU_SIZE_1);
		mi_pif_rdacc(0, 0, `CPU_SIZE_2);
		mi_pif_rdacc(0, 0, `CPU_SIZE_3);
		mi_pif_rdacc(0, 0, `CPU_SIZE_4);
		mi_pif_rdacc(0, 1, `CPU_SIZE_8);
		mi_pif_rdacc(0, 1, `CPU_SIZE_16);
		mi_pif_rdacc(0, 1, `CPU_SIZE_32);

		// check trapping in non-secure mode;

		mi_err_setup({ 2'b00, exp_berr, 3'b000 }, 1);
		mi_pif_rdacc(exp_berr, 0, `CPU_SIZE_1);
		mi_pif_rdacc(exp_berr, 0, `CPU_SIZE_2);
		mi_pif_rdacc(exp_berr, 0, `CPU_SIZE_3);
		mi_pif_rdacc(exp_berr, 0, `CPU_SIZE_4);
		mi_pif_rdacc(exp_berr, 1, `CPU_SIZE_8);
		mi_pif_rdacc(exp_berr, 1, `CPU_SIZE_16);
		mi_pif_rdacc(exp_berr, 1, `CPU_SIZE_32);

		// re-enter secure mode;

		mi_sec_mode_kick(1);
		mi_sec_mode_enter(0);
	end
endtask

// pif write access test;

task mi_pif_wracc;
	input exp_ski;			// expect secure kernel trap;
	input exp_wei;			// expect write error interrupt;
	input blkreq;			// block request;
	input [1:0] size;		// block size;
	input exitsec;			// exit secure mode;
	reg [31:0] addr;		// address;
	reg [31:0] maddr;		// multiple address;
	reg mult;				// force multiple error;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg [31:0] info;		// error info;
	integer n;
	begin
		// leave secure mode is required;

		$display("test: %M: size %0d, ski %b, wei %b",
			blkreq? (8 << size) : (size + 1), exp_ski, exp_wei);
		if(exitsec)
			mi_sec_mode_leave;

		// use random addresses within space;
		// issue different write type for multiple test;

		addr = `BASE_PIF;
		addr[5:2] = $random;
		mult = $random;
		wdata = $random;

		if(blkreq) begin
			addr[4:3] = blk_addr(size);
			addr[2:0] = 0;
			blk_data(wdata);
			bwrite(addr, size);
			if(mult) begin
				maddr = addr;
				maddr[5] = ~maddr[5];
				swrite(maddr, ~size, $random);
			end
		end else begin
			addr[1:0] = sgl_addr(size);
			swrite(addr, size, wdata);
			if(mult) begin
				maddr = addr;
				maddr[5] = ~maddr[5];
				maddr[4:3] = blk_addr(`CPU_SIZE_16);
				maddr[2:0] = 0;
				blk_data($random);
				bwrite(maddr, `CPU_SIZE_16);
			end
		end

		// check write error interrupt and secure trap;
		// error registers must be updated for either;

		mi_check_nmi(~exp_ski, 2);
		mi_check_intr(`INTR_ERR, ~exp_wei);

		if(exp_wei | exp_ski) begin
			sread(`MI_ERR_ADDR, `CPU_SIZE_4, rdata);
			rd_check(0, addr, 32'hffff_ffff, 0);
			sread(`MI_ERR_INFO, `CPU_SIZE_4, rdata);
			info = { 27'd0, 1'b1, mult, blkreq, size };
			rd_check(0, info, 32'hffff_ffff, 0);
			if( ~blkreq) begin
				sread(`MI_ERR_DATA, `CPU_SIZE_4, rdata);
				rd_check(0, wdata, 32'hffff_ffff, 0);
			end
		end

		// check secure trap bit;
		// re-enter secure mode;
		// clear secure triggers to re-enable nmi;

		if(exitsec) begin
			mi_sec_mode_kick(~exp_ski);
			mi_sec_mode_enter(0);
		end
		if(exp_ski) begin
			sread(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
			if(rdata[5] !== 1)
				$display("ERROR: %t: %M: STRAP %b exp 1", $time, rdata[5]);
			if(rdata[2] !== 1)
				$display("ERROR: %t: %M: SAPP %b exp 1", $time, rdata[2]);
			rdata[7:2] = 6'd0;
			swrite(`MI_SEC_MODE, `CPU_SIZE_4, rdata);
			mi_check_nmi(1, 2);
		end
	end
endtask

// test pif write trapping;

task mi_pif_writes;
	input exp_ski;			// expect secure kernel trap;
	input exp_wei;			// expect write error interrupt;
	integer n;
	begin
		// setup error handling;
		// non of below requests should go on cbus;

		mi_cbus_mon(0, 0, 0);
		mi_err_setup({ exp_ski, exp_wei, 1'b0, 3'b000 }, 0);

		// check no trapping in secure mode;

		mi_pif_wracc(0, 0, 0, `CPU_SIZE_1, 0);
		mi_pif_wracc(0, 0, 0, `CPU_SIZE_2, 0);
		mi_pif_wracc(0, 0, 0, `CPU_SIZE_3, 0);
		mi_pif_wracc(0, 0, 0, `CPU_SIZE_4, 0);
		mi_pif_wracc(0, 0, 1, `CPU_SIZE_8, 0);
		mi_pif_wracc(0, 0, 1, `CPU_SIZE_16, 0);
		mi_pif_wracc(0, 0, 1, `CPU_SIZE_32, 0);

		// check trapping in non-secure mode;

		mi_pif_wracc(exp_ski, exp_wei, 0, `CPU_SIZE_1, 1);
		mi_pif_wracc(exp_ski, exp_wei, 0, `CPU_SIZE_2, 1);
		mi_pif_wracc(exp_ski, exp_wei, 0, `CPU_SIZE_3, 1);
		mi_pif_wracc(exp_ski, exp_wei, 0, `CPU_SIZE_4, 1);
		mi_pif_wracc(exp_ski, exp_wei, 1, `CPU_SIZE_8, 1);
		mi_pif_wracc(exp_ski, exp_wei, 1, `CPU_SIZE_16, 1);
		mi_pif_wracc(exp_ski, exp_wei, 1, `CPU_SIZE_32, 1);
	end
endtask

// random memory test;
// for all r/w memories that support single and block requests;

task mi_mem_random;
	input [3:0] mcfg;		// memory configuration;
	input [5:0] nadram;		// # of dram address bits, x64 space;
	reg [2:0] spc;			// address space;
	reg [31:0] addr;		// address;
	reg [31:0] amask;		// address mask;
	reg [5:0] nabits;		// # of address bits;
	reg blkreq;				// block request;
	reg wrreq;				// write to fill data;
	reg [1:0] size;			// request size;
	reg [31:0] wdata;		// write data;
	reg [2:0] sbo;			// subblock order;
	reg [31:0] smask;		// single compare mask;
	integer n;
	begin
		// run over the following memory spaces;
		// x36, x64l, x64h, bram, iram, v0, v1, v2;

		$display("test: %M: mcfg %0d, nadram %0d", mcfg, nadram);
		for(n = 0; n < `MI_N_MEMRAND; n = n + 1) begin

			// pick random space;
			// make random address within that space;

			spc = $random;
			case(spc)
				0: { addr, nabits } = { `BASE_DRAM36, nadram - 1 };
				1: { addr, nabits } = { `BASE_DRAM64L, nadram };
				2: { addr, nabits } = { `BASE_DRAM64H, nadram };
				3: { addr, nabits } = { `MI_BRAM_FLIP, `MI_NA_BRAM };
				4: { addr, nabits } = { `MI_IRAM, `MI_NA_IRAM };
				5: { addr, nabits } = { `MI_VMEM0, `MI_NA_VMEM0 };
				6: { addr, nabits } = { `MI_VMEM1, `MI_NA_VMEM1 };
				7: { addr, nabits } = { `MI_VMEM2, `MI_NA_VMEM2 };
			endcase
			amask = 32'hffff_ffff >> (32 - nabits);
			amask[1:0] = 2'b00;
			addr = addr | ($random & amask);

			// pick random request type;

			{ size, blkreq, wrreq } = $random;
			while(blkreq & (size == 2'b11))
				size = $random;

			// write random data for wrreq;

			if(wrreq) begin
				wdata = $random;
				if(blkreq) begin
					addr[4:2] = blk_addr(size);
					blk_data(wdata);
					bwrite(addr, size);
				end else
					swrite(addr, size, wdata);
			end

			// read back data;
			// if block request, the use random subblock order;
			// check only if write had been issued;

			if(blkreq) begin
				sbo = sbo_addr(size);
				addr[4:2] = addr[4:2] ^ sbo;
				bread(addr, size);
				if(wrreq)
					blk_check(size, wdata, 0, sbo);
			end else begin
				sread(addr, size, data[0]);
				if(wrreq) begin
					smask = sgl_mask(addr[1:0], size);
					rd_check(0, wdata, smask, 0);
				end
			end
		end
	end
endtask

// test mi debug interface;

task mi_debug;
	begin
		$display("test: %M: XXX");
	end
endtask

// run all mi tests;

task test_mi;
	reg [31:0] pxor;		// test pattern xor;
	reg [5:0] nadram;		// # of dram address bits, x64 space;
	integer mcfg;			// current ddr configuration id;
	begin
		// run register related tests;
		// no cbus requests should be issued;

		mi_cbus_mon(0, 0, 0);
		mi_after_reset(3'b000);			// test mi defaults after reset;
		mi_avctrl;						// test audio/video control register;
		mi_ctrl;						// test control register;
		mi_intr_mask(`MI_MASK, 6);		// test interrupt mask register;
		mi_intr_mask(`MI_EMASK, 14);	// test extended mask register;
		mi_sec_mode;					// test secure mode functionality;
		mi_sec_timer;					// test secure timer;
		mi_sec_vtime(62);				// test virage timer;
		mi_sec_vtime(100);				// test virage timer;
		mi_button_test(0);				// test button intr;

		// test mi internal memories;
		// test single and block requests, subblock order;
		// no cbus requests should be issued;

		mi_cbus_mon(0, 0, 0);
		mi_brom;				// test brom;
		mi_bram;				// test bram;
		mi_iram;				// test iram;
		mi_vmem(0, 6);			// test virage 0, 512bits;
		mi_vmem(1, 6);			// test virage 1, 512bits;
		mi_vmem(2, 8);			// test virage 2, 2kbits;

		// fill all mi internal memories with address pattern;
		// then read all back and compare;
		// this tests read/write interference among those memories;

		pxor = $random;
		mi_mem_fill_pat(`MI_BRAM_FLIP, `MI_NA_BRAM, pxor);
		mi_mem_fill_pat(`MI_IRAM, `MI_NA_IRAM, pxor);
		mi_mem_fill_pat(`MI_VMEM0, `MI_NA_VMEM0, pxor);
		mi_mem_fill_pat(`MI_VMEM1, `MI_NA_VMEM1, pxor);
		mi_mem_fill_pat(`MI_VMEM2, `MI_NA_VMEM2, pxor);

		mi_mem_cmp_pat(`MI_BRAM_FLIP, `MI_NA_BRAM, pxor);
		mi_mem_cmp_pat(`MI_IRAM, `MI_NA_IRAM, pxor);
		mi_mem_cmp_pat(`MI_VMEM0, `MI_NA_VMEM0, pxor);
		mi_mem_cmp_pat(`MI_VMEM1, `MI_NA_VMEM1, pxor);
		mi_mem_cmp_pat(`MI_VMEM2, `MI_NA_VMEM2, pxor);

		// mi internal performance tests;
		// measure write bandwidth first, which fills patterns;
		// then read and measure read bandwidth;

		mi_rwbw(0, `MI_IRAM, 1, `CPU_SIZE_16);
		mi_rwbw(0, `MI_IRAM, 0, `CPU_SIZE_16);
		mi_rwbw(0, `MI_IRAM, 1, `CPU_SIZE_32);
		mi_rwbw(0, `MI_IRAM, 0, `CPU_SIZE_32);

		// test main memory of all configurations;
		// block read tests needs main memory;

		nadram = vsim.MEM_NADDR;
		for(mcfg = 0; mcfg < 16; mcfg = mcfg + 1) begin
`ifdef	MI_ONE_MCFG
			mcfg = $random;
`endif	// MI_ONE_MCFG
			mi_cbus_mon(1, 1, 1);
			ri_config_ddr(mcfg, $random);

			// test request error detection;

			mi_blk_reads(0, nadram);		// block reads without bus error;
			mi_blk_reads(1, nadram);		// block reads with bus error;
			mi_blk_writes(0, 0, nadram);	// block writes dropped;
			mi_blk_writes(0, 1, nadram);	// block writes with write error intr;
			mi_blk_writes(1, 0, nadram);	// block writes with secure kernel trap;

			// test pif emulation trapping;

			mi_pif_reads(0);				// reads without bus error;
			mi_pif_reads(1);				// reads with bus error;
			mi_pif_writes(0, 0);			// writes dropped;
			mi_pif_writes(0, 1);			// writes with write error intr;
			mi_pif_writes(1, 0);			// writes with secure kernel trap;

			// test mi access to main memory (ri);

			mi_cbus_mon(0, 0, 1);
			mi_dram_sgl(nadram);			// targeted single requests;
			mi_dram_blk(nadram);			// targeted block requests;
			mi_dram_subblk(nadram);			// targeted sub-block orders;

			//XXX targeted test through x64 mirror spaces;
			// write one space, read from another;

			// random memory tests;
			// random address and request types;

			mi_mem_random(mcfg, nadram);

			// mi dram performance tests;
			// measure write bandwidth first, which fills patterns;
			// then measure read bandwidth;

			mi_rwbw(mcfg, `BASE_DRAM36, 1, `CPU_SIZE_16);
			mi_rwbw(mcfg, `BASE_DRAM36, 0, `CPU_SIZE_16);
			mi_rwbw(mcfg, `BASE_DRAM36, 1, `CPU_SIZE_32);
			mi_rwbw(mcfg, `BASE_DRAM36, 0, `CPU_SIZE_32);

			mi_rwbw(mcfg, `BASE_DRAM64L, 1, `CPU_SIZE_16);
			mi_rwbw(mcfg, `BASE_DRAM64L, 0, `CPU_SIZE_16);
			mi_rwbw(mcfg, `BASE_DRAM64L, 1, `CPU_SIZE_32);
			mi_rwbw(mcfg, `BASE_DRAM64L, 0, `CPU_SIZE_32);

`ifdef	MI_ONE_MCFG
			mcfg = 100;
`endif	// MI_ONE_MCFG
		end

		// button trap test;

		mi_button_test(1);				// launch button timer trap;

		// test virage store controllers and bypass;
		// run as late as possible for charge-pump to
		// finish 1msec power-on reset;

`ifdef	XXX
		mi_vx_ctrl(0, 6);			// test virage 0, 512bits;
		mi_vx_ctrl(1, 6);			// test virage 1, 512bits;
		mi_vx_ctrl(2, 8);			// test virage 2, 2kbits;

		// test rcp interrupts; XXX

		// test new device interrupts; XXX

		// test debug interface;

		mi_debug;
`endif
	end
endtask

// run only the memory random stress test;
// mainly to help debug the ri;

task test_mem_rand;
	reg [5:0] nadram;		// # of dram address bits, x64 space;
	integer mcfg;			// current ddr configuration id;
	begin
		// test main memory of all configurations;
		// block read tests needs main memory;

		nadram = vsim.MEM_NADDR;
		for(mcfg = 0; mcfg < 16; mcfg = mcfg + 1) begin
			mi_cbus_mon(1, 1, 1);
			ri_config_ddr(mcfg, $random);
			mi_mem_random(mcfg, nadram);
		end
	end
endtask