// pi_test.v v1 Frank Berndt
// pi verilog tests;
// :set tabstop=4

`timescale 1ns/1ns

// aes buffers;
// here because memory cannot be passed into tasks;

reg [31:0] aes_init [0:3];		// cbc init vector;
reg [31:0] aes_ekey [0:43];		// expanded key;
reg [31:0] aes_ctext [0:255];	// cipher text;
reg [31:0] aes_ptext [0:255];	// plain text;

// flash configuration;

reg [3:0] flash_present;		// devices present;
reg [31:0] flash_size [0:3];	// flash sizes in MB;
reg [31:0] flash_amask [0:3];	// flash address mask per device;
reg [3:0] flash_adph [0:3];		// # of address phases per flash;

// flash ready times;
// FLASH_FAST is defined in define.vh;

`ifdef	FLASH_FAST
`define	FL_RDY_READ		1000		// 1 usec;
`define	FL_RDY_ERASE	5000		// 5 usec;
`define	FL_RDY_PROG		5000		// 5 usec;
`define	FL_RDY_RESET	5000		// 5 usec;
`else	/* FLASH_FAST */
`define	FL_RDY_READ		20000		// 20 usec;
`define	FL_RDY_ERASE	4000000		// 4 msec;
`define	FL_RDY_PROG		500000		// 500 usec;
`define	FL_RDY_RESET	1000000		// 1 msec;
`endif	/* FLASH_FAST */

`define	N_PI_FLASH_PARTIAL	4		// # of partial flash random tests;
`define	N_PI_ATB_RAND		8		// # of atb random lookups;
`define	N_PI_ECC_PAGES		8		// # of random ecc test pages;

// must serialize erase/program cmds for toshiba fix;

`define	FL_EP_SERIAL	1

// flash pattern buffer;
// one buffer per possible device;
// read from ./External_File.txt that preload the flash v models;
// needed for comparison to flash content;

reg [7:0] flash_pat [0:528*8-1];

// dma pattern buffer;

reg [31:0] pi_dma_pat [0:255];		// size of pi buffer;

// get a random memory address within space;
// make sure requested block does not wrap;

function [31:0] pi_mem_addr;
	input [7:0] space;		// memory space;
	input [23:0] size;		// size of block;
	input [23:0] align;		// alignment;
	reg [31:0] mask;		// address mask;
	reg [31:0] addr;		// address;
	begin
		mask = vsim.MEM_SIZE - 1;
		if(space == 8'h00)
			mask = mask >> 1;
		addr = $random & mask;
		while((addr + size) > mask)
			addr = $random & mask;
		addr = addr & ~(align - 1);
		pi_mem_addr = addr;
	end
endfunction

// get a random device address;
// make sure requested block does not wrap;
// limit device address to 16MB block of virtual flash;

function [31:0] pi_dev_addr;
	input [23:0] size;		// size of block;
	input [23:0] align;		// alignment;
	reg [31:0] mask;		// address mask;
	reg [31:0] addr;		// address;
	begin
		mask = (16*1024*1024 - 1);
		addr = $random & mask;
		while((addr + size) > mask)
			addr = $random & mask;
		addr = addr & ~(align - 1);
		pi_dev_addr = addr;
	end
endfunction

// fill flash_pat buffer with randoms;

task pi_flash_buf_rand;
	input [2:0] pbidx;		// page buffer to use;
	integer n;
	begin
		for(n = 0; n < 528; n = n + 1)
			flash_pat[n + (528 * pbidx)] = $random;
	end
endtask

// copy pattern buffer into another one;

task pi_flash_copy_pb;
	input [2:0] pbsrc;		// source buffer;
	input [2:0] pbdst;		// destination buffer;
	integer n, soff, doff;
	begin
		soff = 528 * pbsrc;
		doff = 528 * pbdst;
		for(n = 0; n < 528; n = n + 1)
			flash_pat[n + doff] = flash_pat[n + soff];
	end
endtask

// setup randoms in main memory through backdoor;

task pi_mem_rand;
	input [31:0] maddr;		// memory address;
	input [31:0] size;		// # of bytes;
	begin
		maddr[1:0] = 2'b00;
		size = size >> 2;
		while(size > 0) begin
			vsim.mem_swrite(maddr, `CPU_SIZE_4, $random);
			size = size - 1;
			maddr = maddr + 4;
		end
	end
endtask

// configure bb nand flash model;

task pi_nflash_conf;
	input [1:0] dev;		// device id;
	input [31:0] size;		// size in MB, 0 disables;
	input [2:0] nadph;		// # of address phases;
	input [2:0] nid;		// # of id bytes;
	begin
		case(dev)
`ifdef	NFLASH3
			3: begin
				vsim.mm.nflash3.size = size;
				vsim.mm.nflash3.nadph = nadph;
				vsim.mm.nflash3.nid = nid;
			end
`endif	// NFLASH
		endcase
	end
endtask

// set pi access rights;

task pi_access;
	input [7:0] acc;		// access rights;
	reg secure;				// secure mode;
	reg [31:0] rold;		// old state;
	reg [31:0] rdata;		// read data;
	reg [31:0] exp;			// expected data;
	begin
		secure = vsim.bb.bcp.mi.secure;
		$display("%t: %M: secure %b, acc 0x%h", $time, secure, acc);
		if( !secure)
			sread(`PI_ACCESS, `CPU_SIZE_4, rold);
		swrite(`PI_ACCESS, `CPU_SIZE_4, { 24'bx, acc });
		sread(`PI_ACCESS, `CPU_SIZE_4, rdata);
		exp = { 24'd0, acc };
		if( !secure)
			exp = exp & rold;
		rd_check(0, exp, 32'hffff_ffff, 0);
	end
endtask

// test pi defaults after reset;

task pi_after_reset;
	reg [31:0] rdata;		// read data;
	reg [31:0] exp;			// expected data;
	begin
		// enter secure mode;
		// must turn on access rights for all pi hardware;

		mi_set_boot_word(1);
		mi_sec_mode_enter(1);
		$display("test: %M: PI_ACCESS");
		sread(`PI_ACCESS, `CPU_SIZE_4, rdata);
		exp = { 24'bx, 8'd0 };
		rd_check(0, exp, 32'h0000_00ff, 0);
		pi_access(8'hff);

		// test reset defaults in registers;

		$display("test: %M: PI_STATUS");
		sread(`PI_STATUS, `CPU_SIZE_4, rdata);
		exp = { 29'bx, 3'b000 };
		rd_check(0, exp, 32'h0000_0007, 0);

		$display("test: %M: PI_AES_CTRL");
		sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
		exp = { 2'b00, 30'bx };
		rd_check(0, exp, 32'hc000_0000, 0);

		$display("test: %M: PI_FLASH_CONF");
		sread(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);
		exp = { 1'b1, 3'd7, 1'b0, 3'd5, 8'b00111110, 8'b00111110, 8'b11111111 };
		rd_check(0, exp, 32'hffff_ffff, 0);

		$display("test: %M: PI_FLASH_CTRL");
		sread(`PI_FLASH_CTRL, `CPU_SIZE_4, rdata);
		exp = { 2'b0, 30'bx };
		rd_check(0, exp, 32'hc000_0000, 0);

		$display("test: %M: PI_GPIO");
		sread(`PI_GPIO, `CPU_SIZE_4, rdata);
		exp = { vsim.board_id, 8'd0, 4'b0011, 4'bxx00 };
		rd_check(0, exp, 32'hffff_00f3, 0);

		$display("test: %M: PI_IDE_CONF");
		sread(`PI_IDE_CONF, `CPU_SIZE_4, rdata);
		exp = { 1'b1, 5'd8, 5'd7, 5'd2, 6'd9, 5'd8, 5'd1 };
		rd_check(0, exp, 32'hffff_ffff, 0);

		// XXX PI_IDE_CTRL;

		$display("test: %M: PI_ERROR");
		sread(`PI_ERROR, `CPU_SIZE_4, rdata);
		exp = { 2'b00, 22'bx, 3'd0, 5'd0 };
		rd_check(0, exp, 32'hc000_00ff, 0);

		// all pi interrupts should be 0;
		// enable all pi interrupts in mi;

		$display("test: %M: enabling pi interrupts");
		sread(`MI_EINTR, `CPU_SIZE_4, rdata);
		exp = { 21'd0, 5'b00000, 6'b000000 };
		rd_check(0, exp, 32'h0000_01d0, 0);
		swrite(`MI_EMASK, `CPU_SIZE_4, 22'b0000101010_001000000000);
		sread(`MI_EMASK, `CPU_SIZE_4, rdata);
		exp = { 21'd0, 5'b00111, 6'b010000 };
		rd_check(0, exp, exp, 0);
	end
endtask

// test pi registers;

task pi_regs;
	reg [31:0] rdata;		// read data;
	begin
		// test compatible registers;
		// cannot test PI_READ_LEN and PI_WRITE_LEN, because of side effects;

		$display("test: %M: compatible registers");
		test_reg(`PI_DRAM_ADDR, 32'h03fffffe, 32'hffff_ffff, 32'd0);
		test_reg(`PI_DEV_ADDR, 32'h3ffffffe, 32'hffff_ffff, 32'd0);

		// test new registers;
		// must save PI_FLASH_CONF value;

		$display("test: %M: new registers");
		test_reg(`PI_FLASH_ADDR, 32'h3fff_ffff, 32'hffff_ffff, 32'd0);
		sread(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);
		test_reg(`PI_FLASH_CONF, 32'hffff_ffff, 32'hffff_ffff, 32'd0);
		swrite(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);
		test_reg(`PI_FLASH_CTRL, 32'h3fff_f3ff, 32'h3fff_ffff, 32'd0);
		test_reg(`PI_AES_CTRL, 32'h003f_feff, 32'h3fff_ffff, 32'd0);
	end
endtask

// check pi interrupts;
// interrupt location on cpu int_l is hard-coded;

	wire [4:0] bb_int_l;

`ifdef	SIMGATE
	assign bb_int_l = { vsim.bb.int_l_4_, vsim.bb.int_l_3_,
		vsim.bb.int_l_2_, vsim.bb.int_l_1_, vsim.bb.int_l_0_ };
`else	// SIMGATE
	assign bb_int_l = vsim.bb.int_l;
`endif	// SIMGATE

task pi_intr_check;
	input [3:0] inbr;		// interrupt number in MI_EINTR;
	input intr;				// expected intr value;
	reg [31:0] rdata;		// read data;
	reg [3:0] idx;			// interupt index;
	reg iline;				// value of cpu interrupt line;
	begin
		$display("%t: %M: inbr %0d intr %b", $time, inbr, intr);
		sread(`MI_EINTR, `CPU_SIZE_4, rdata);
		if(rdata[inbr] !== intr) begin
			$display("ERROR: %t: %M: mi_intr[%0d] %b exp %b",
				$time, inbr, rdata[inbr], intr);
		end
		if(inbr < 6)
			idx = 0;
		else if(inbr < 11)
			idx = 1;
		else
			idx = 'bx;
		iline = bb_int_l[idx];
		if(iline !== ~intr) begin
			$display("ERROR: %t: %M: int_l[%0d] %b exp %b",
				$time, idx, iline, ~intr);
		end
	end
endtask

// check upper atb bits;

task pi_atb_check;
	input [31:0] addr;		// atb address;
	input [8:0] exp;		// expected atb bits;
	reg [31:0] atb;			// atb read word;
	reg [8:0] atbu;			// atb read bits;
	begin
		addr[11] = 1;
		sread(addr, `CPU_SIZE_4, atb);
		atbu = addr[2]? atb[8:0] : atb[24:16];
		if((atbu !== exp) | data_err) begin
			$display("ERROR: %t: %M: atb miscompare 0x%h/%b exp 0x%h/0",
				$time, atbu, data_err, exp);
		end
	end
endtask

// test pio access to pibuf;
// also test the upper atb bits;
// 2kbyte buffer, 256x80;

task pi_buf_pio_tests;
	reg [31:0] addr;			// current address;
	reg [31:0] saddr [2:10];	// addresses used;
	reg [31:0] sdata [2:10];	// data at address;
	reg [8:0] satbu [2:10];		// upper atb write bits;
	integer n;
	begin
		// write with walking 0 and 1;

		$display("test: %M: writes");
		addr = `PI_BUF;
		for(n = 2; n < 11; n = n + 1) begin
			addr[10:0] = (1 << n);
			saddr[n] = addr;
			satbu[n] = $random;
			swrite(`PI_ATBU, `CPU_SIZE_4, satbu[n]);
			sdata[n] = $random;
			swrite(addr, `CPU_SIZE_4, sdata[n]);
			addr[10:2] = ~addr[10:2];
			swrite(`PI_ATBU, `CPU_SIZE_4, ~satbu[n]);
			swrite(addr, `CPU_SIZE_4, ~sdata[n]);
		end

		// read and compare;

		$display("test: %M: read and compare");
		for(n = 2; n < 11; n = n + 1) begin
			addr = saddr[n];
			sread(addr, `CPU_SIZE_4, data[0]);
			rd_check(0, sdata[n], 32'hffffffff, 0);
			pi_atb_check(addr, satbu[n]);
			addr[10:2] = ~addr[10:2];
			sread(addr, `CPU_SIZE_4, data[0]);
			rd_check(0, ~sdata[n], 32'hffffffff, 0);
			pi_atb_check(addr, ~satbu[n]);
		end
	end
endtask

// check flash cmd with monitor recordings;

task pi_flash_mon_check;
	input [31:0] daddr;		// device address;
	input [31:0] ctrl;		// command;
	reg [7:0] mon_cmd;
	integer mon_naph;		// # of address phases;
	integer mon_ndph;		// # of data phases;
	reg mon_wrdy;
	integer exp_aph;		// expected address phases;
	integer exp_dph;		// expected data phases;
	begin
		exp_aph = ctrl[24];
		if(ctrl[25])
			exp_aph = exp_aph + 1;
		if(ctrl[26])
			exp_aph = exp_aph + 1;
		if(ctrl[27])
			exp_aph = exp_aph + 1;
		if(ctrl[29:28] === 2'b00)
			exp_dph = 0;
		else begin
			exp_dph = 528 - daddr[8:0];
			if(ctrl[9:0] < exp_dph)
				exp_dph = ctrl[9:0];
		end
		case(ctrl[13:12])
			2'd0: begin
				mon_cmd = vsim.io_mon.fl_mon0.cmd;
				mon_naph = vsim.io_mon.fl_mon0.naph;
				mon_ndph = vsim.io_mon.fl_mon0.ndph;
				mon_wrdy = vsim.io_mon.fl_mon0.wrdy;
			end
			2'd1: begin
				mon_cmd = vsim.io_mon.fl_mon1.cmd;
				mon_naph = vsim.io_mon.fl_mon1.naph;
				mon_ndph = vsim.io_mon.fl_mon1.ndph;
				mon_wrdy = vsim.io_mon.fl_mon1.wrdy;
			end
			2'd2: begin
				mon_cmd = vsim.io_mon.fl_mon2.cmd;
				mon_naph = vsim.io_mon.fl_mon2.naph;
				mon_ndph = vsim.io_mon.fl_mon2.ndph;
				mon_wrdy = vsim.io_mon.fl_mon2.wrdy;
			end
			2'd3: begin
				mon_cmd = vsim.io_mon.fl_mon3.cmd;
				mon_naph = vsim.io_mon.fl_mon3.naph;
				mon_ndph = vsim.io_mon.fl_mon3.ndph;
				mon_wrdy = vsim.io_mon.fl_mon3.wrdy;
			end
		endcase
		if(daddr[8])
			ctrl[16] = 1;
		if(mon_cmd != ctrl[23:16]) begin
			$display("ERROR: %t: %M: cmd mismatch 0x%h exp 0x%h",
				$time, mon_cmd, ctrl[23:16]);
		end
		if(mon_naph != exp_aph) begin
			$display("ERROR: %t: %M: address phase mismatch %0d exp %0d",
				$time, mon_naph, exp_aph);
		end
		if(mon_ndph != exp_dph) begin
			$display("ERROR: %t: %M: data phase mismatch %0d exp %0d",
				$time, mon_ndph, exp_dph);
		end
		if(ctrl[15] & (mon_wrdy !== 1))
			$display("ERROR: %t: %M: missing ready", $time);
	end
endtask

// setup flash timing config;
// reduces simulator time and tests timing;
// leave write-protect on;
// read back and check;

task pi_flash_config;
	input wp;				// write protected;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	begin
		wdata[31] = wp;
		wdata[27] = 'b0;
		if(vsim.sysclk_period > 15000) begin
			wdata[30:28] = 3'd2;
			wdata[26:24] = 3'd2;
			wdata[23:16] = 8'b00000111;
			wdata[15:8] = 8'b00000111;
			wdata[7:0] = 8'b00011111;
		end else if(vsim.sysclk_period >= 10000) begin
`ifdef TOSHIBA_64MB
			$display("NOTE: Toshiba flash config 0x753e1f3f");
			wdata[30:28] = 3'd7;
			wdata[26:24] = 3'd5;
			wdata[23:16] = 8'b00111110;
			wdata[15:8] = 8'b00011111;
			wdata[7:0] = 8'b00111111;
`else
			wdata[30:28] = 3'd4;
			wdata[26:24] = 3'd3;
			wdata[23:16] = 8'b00001111;
			wdata[15:8] = 8'b00001111;
			wdata[7:0] = 8'b00111111;
`endif
		end else begin
			$display("ERROR: %t: %M: sysclk period %0dps not supported",
				$time, vsim.sysclk_period);
		end
		$display("%t: %M: configuring flash timing: 0x%x", $time, wdata);
		swrite(`PI_FLASH_CONF, `CPU_SIZE_4, wdata);
		sread(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);
		rd_check(0, wdata, 32'hffff_ffff, 0);
	end
endtask

// issue flash command;

task pi_flash_cmd;
	input [31:0] daddr;		// device address;
	input [31:0] ctrl;		// flash control;
	input [31:0] rdyto;		// ready timeout;
	input [11:10] eccsts;	// ecc error status;
	reg [31:0] rdata;		// read data;
	integer to;				// timeout in sysclks;
	integer tx;				// time snap shot;
	integer nb;
	reg rreq;				// random read request;
	reg [1:0] dev;			// flash device;
	begin
		// check that flash controller is idle;
		// check that address is within bounds of device;

		dev = ctrl[13:12];
		$display("test: %M: dev %d, addr 0x%h, ctrl 0x%h", dev, daddr, ctrl);
		sread(`PI_FLASH_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 0)
			$display("%t: %M: flash ctrl not idle %b", $time, rdata[31]);
		if((daddr & ~flash_amask[dev]) !== 32'h0)
			$display("ERROR: %t: %M: addr 0x%h out of bounds", $time, daddr);

		// issue request;
		// check that flash controller is busy;

		swrite(`PI_FLASH_ADDR, `CPU_SIZE_4, daddr);
		swrite(`PI_FLASH_CTRL, `CPU_SIZE_4, ctrl);
		sread(`PI_FLASH_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 1)
			$display("%t: %M: flash ctrl not busy %b", $time, rdata[31]);
		if(rdata[11:10] !== 2'b00)
			$display("%t: %M: ecc status %b, not cleared", $time, rdata[11:10]);

		// spin on flash busy status;
		// issue random intervening pi buffer operations;
		// scratch into atb buffer;
		// one data byte takes up to 10 clocks in slowest timing config;
		// add one more clock for pi buffer access;
		// five more bytes for command and address phases;
		// add busy time depending on the wait ready bit;
		// allow 50 more clocks for pi buffer stealing;

		nb = ctrl[9:0] + 5;
		to = 12 * nb;
		if(ctrl[15])
			to = to + ((rdyto * 1000) / vsim.sysclk_period);
		to = (to + 50) * (vsim.sysclk_period / 1000);
		while((to > 0) & (rdata[31] === 1)) begin
			tx = $time;
			rreq = $random;
			if(rreq)
				sread(`PI_BUF_ATB, `CPU_SIZE_4, rdata);
			else
				swrite(`PI_BUF_ATB, `CPU_SIZE_4, rdata);
			req_spacing($random);
			sread(`PI_FLASH_CTRL, `CPU_SIZE_4, rdata);
			to = to - ($time - tx);
		end
		if(to < 0)
			$display("ERROR: %t: %M: flash busy timeout %b", $time, rdata[31]);

		// check that interrupt is as requested;

		pi_intr_check(`MI_INTR_FLASH, ctrl[30]);
		if(rdata[30] !== ctrl[30])
			$display("ERROR: %t: %M: intr %b exp %b", $time, rdata[30], ctrl[30]);

		// check if sbe/dbe are as expected;

		if(rdata[11] !== eccsts[11])
			$display("ERROR: %t: %M: sbe %b exp %b", $time, rdata[11], eccsts[11]);
		if(rdata[10] !== eccsts[10])
			$display("ERROR: %t: %M: dbe %b exp %b", $time, rdata[10], eccsts[10]);

		// stop flash controller;
		// also clears interrupt, sbe and dbe;
		// don't modify multi-cycle bit as it would break those comands;

		ctrl[31] = 0;
		ctrl[30] = 0;
		swrite(`PI_FLASH_CTRL, `CPU_SIZE_4, ctrl);

		// check that interrupt is cleared;

		pi_intr_check(`MI_INTR_FLASH, 0);
		sread(`PI_FLASH_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 0)
			$display("ERROR: %t: %M: unexpected busy %b", $time, rdata[31]);
		if(rdata[30] !== 0)
			$display("ERROR: %t: %M: unexpected intr %b", $time, rdata[30]);

		// check statistics recorded by flash monitor;

		pi_flash_mon_check(daddr, ctrl);
	end
endtask

// test flash id read;

task pi_flash_read_id;
	input [1:0] dev;		// device;
	input bufid;			// buffer to use;
	reg [31:0] ctrl;		// flash command;
	reg [31:0] addr;		// cpu address;
	reg [31:0] rdata;		// read data;
	reg [7:0] mfg;			// mfg code;
	reg [7:0] devid;		// device id;
	integer flsz;			// size of flash;
	begin
		$display("test: %M: dev %d", dev);
		ctrl[31] = 1;
		ctrl[30] = 0;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 1;			// read data phase;
		ctrl[27:24] = 4'b0001;	// one address phase;
		ctrl[23:16] = 8'h90;	// read mfg and device id;
		ctrl[15] = 0;			// no ready;
		ctrl[14] = bufid;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = 2;			// two byte read phase;
		pi_flash_cmd(0, ctrl, 0, 0);

		// read id bytes from pi buffer;
		// check all supported devices;

		addr = `PI_BUF0;
		addr[9] = bufid;
		sread(addr, `CPU_SIZE_4, rdata);
		mfg = rdata[31:24];
		devid = rdata[23:16];
		flash_present[dev] = 1;
`ifdef TOSHIBA_64MB
		flash_adph[dev] = 4'b1111;
`else
		flash_adph[dev] = 4'b0111;
`endif
		case({mfg, devid})
			// special bb model;
			{ 8'hfb, 8'd8 }: flsz = devid;
			{ 8'hfb, 8'd16 }: flsz = devid;
			{ 8'hfb, 8'd32 }: flsz = devid;
			{ 8'hfb, 8'd64 }: flsz = devid;
			// samsung models;
			{ 8'hec, 8'he6 }: flsz = 8;		// samsung 8MB;
			{ 8'hec, 8'h73 }: flsz = 16;	// samsung 16MB;
			{ 8'hec, 8'h75 }: flsz = 32;	// samsung 32MB;
			{ 8'hec, 8'h76 }: flsz = 64;	// samsung 64MB;
			// Toshiba 
			{ 8'h98, 8'h73 }: flsz = 16; 
			{ 8'h98, 8'h75 }: flsz = 32; 
			{ 8'h98, 8'h76 }: flsz = 64; 
			default: begin
				flsz = 'bx;
				flash_present[dev] = 0;
				flash_amask[dev] = 0;
				$display("ERROR: %t: %M: dev %d, unknown mfg 0x%h dev 0x%h id",
					$time, dev, mfg, devid);
			end
		endcase
		flash_size[dev] = flsz;
		if(flsz >= 64)
			flash_adph[dev] = 4'b1111;
		if(flash_present[dev] == 1) begin
			flash_amask[dev] = (flsz << 20) - 1;
			$display("%t: %M: dev %d, mfg 0x%h dev 0x%h id, size %0dMB",
				$time, dev, mfg, devid, flsz);
		end
	end
endtask

// test flash status read;

task pi_flash_status;
	input [1:0] dev;		// device;
	input bufid;			// buffer to use;
	output [7:0] status;	// status byte;
	reg [31:0] ctrl;		// flash command;
	reg [31:0] addr;		// cpu address;
	reg [31:0] rdata;		// read data;
	begin
		$display("test: %M: dev %d", dev);
		ctrl[31] = 1;
		ctrl[30] = 0;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 1;			// read data phase;
		ctrl[27:24] = 4'd0;		// no address phases;
		ctrl[23:16] = 8'h70;	// read status;
		ctrl[15] = 0;			// no ready;
		ctrl[14] = bufid;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = 1;			// one byte status read phase;
		pi_flash_cmd(0, ctrl, 0, 0);

		// read status from pi buffer;

		addr = `PI_BUF0;
		addr[9] = bufid;
		sread(addr, `CPU_SIZE_4, rdata);
		status = rdata[31:24];
	end
endtask

// test flash page read;

task pi_flash_read_page;
	input [1:0] dev;		// device;
	input bufid;			// buffer id;
	input [31:0] daddr;		// device address;
	input [9:0] nbytes;		// # of bytes;
	input [3:0] adph;		// address phase mask;
	input ecc;				// enable ecc;
	input intr;				// use interrupt;
	input [11:10] eccsts;	// expected ecc status;
	reg [31:0] ctrl;
	begin
		$display("test: %M: dev %d, addr 0x%h, %0d bytes", dev, daddr, nbytes);
		ctrl[31] = 1;
		ctrl[30] = intr;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 1;			// read data phase;
		ctrl[27:24] = adph;		// address phases;
		ctrl[23:16] = 8'h00;	// read page;
		ctrl[15] = 1;			// require ready;
		ctrl[14] = bufid;
		ctrl[13:12] = dev;
		ctrl[11] = ecc;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = nbytes;
		pi_flash_cmd(daddr, ctrl, `FL_RDY_READ, eccsts);
	end
endtask

// test flash spare read;

task pi_flash_read_spare;
	input [1:0] dev;		// device;
	input bufid;			// buffer id;
	input [31:0] daddr;		// device address;
	input [9:0] nbytes;		// # of bytes;
	input [3:0] adph;		// address phase mask;
	input intr;				// use interrupt;
	reg [31:0] ctrl;
	begin
		$display("test: %M: dev %d, addr 0x%h, %0d bytes", dev, daddr, nbytes);
		ctrl[31] = 1;
		ctrl[30] = intr;		// no interrupt;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 1;			// read data phase;
		ctrl[27:24] = adph;		// address phases;
		ctrl[23:16] = 8'h50;	// read spare;
		ctrl[15] = 1;			// require ready;
		ctrl[14] = bufid;
		ctrl[13:12] = dev;
		ctrl[11] = 0;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = nbytes;
		pi_flash_cmd(daddr, ctrl, `FL_RDY_READ, 0);
	end
endtask

// test flash block erase;

task pi_flash_erase;
	input [1:0] dev;		// device;
	input [31:0] daddr;		// device address;
	input [3:0] adph;		// address phase mask;
	input intr;				// use interrupt;
	input wrdy;				// wait for ready;
	reg [31:0] ctrl;		// flash controller command;
	reg [7:0] status;		// status byte;
	begin
		// issue read status command to check write-protection;

		pi_flash_status(dev, $random, status);
		if(status[7] !== 1)
			$display("ERROR: %t: %M: wp %b not 1", $time, status[7]);
		if(status[6] !== 1)
			$display("ERROR: %t: %M: ryby %b not 1", $time, status[6]);

		$display("test: %M: dev %d, addr 0x%h setup", dev, daddr);
		ctrl[31] = 1;
		ctrl[30] = 0;			// no intr for erase setup;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 0;			// no read data phase;
		adph[0] = 0;
		ctrl[27:24] = adph;		// address phases;
		ctrl[23:16] = 8'h60;	// block erase setup;
		ctrl[15] = 0;			// setup does not require ready;
		ctrl[14] = $random;		// don't care about buffer;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 1;			// multi-cycle command;
		ctrl[9:0] = 0;			// no data;
		daddr[8] = 0;			// must be 0;
		daddr[7:0] = 8'hxx;		// don't care;
		pi_flash_cmd(daddr, ctrl, 0, 0);

		$display("test: %M: dev %d, addr 0x%h erase", dev, daddr);
		ctrl[31] = 1;
		ctrl[30] = intr;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 0;			// no read data phase;
		ctrl[27:24] = 4'd0;		// no address phases;
		ctrl[23:16] = 8'hd0;	// block erase execute;
		ctrl[15] = wrdy;
		ctrl[14] = $random;		// don't care about buffer;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// last of multi-cycle command;
		ctrl[9:0] = 0;			// no data;
		daddr[8] = 0;			// must be 0;
		pi_flash_cmd(daddr, ctrl, `FL_RDY_ERASE, 0);
	end
endtask

// test flash page program;

task pi_flash_program;
	input [1:0] dev;		// device;
	input bufid;			// buffer id;
	input [31:0] daddr;		// device address;
	input [9:0] nbytes;		// # of bytes;
	input [3:0] adph;		// address phase mask;
	input intr;				// use interrupt;
	input wrdy;				// wait for ready;
	input ecc;				// let hardware calculate ecc;
	reg [31:0] ctrl;		// flash controller command;
	reg [7:0] status;		// status byte;
	begin
		// issue read status command to check write-protection;

		pi_flash_status(dev, ~bufid, status);
		if(status[7] !== 1)
			$display("ERROR: %t: %M: wp %b not 1", $time, status[7]);
		if(status[6] !== 1)
			$display("ERROR: %t: %M: ryby %b not 1", $time, status[6]);

		$display("test: %M: dev %d, addr 0x%h setup", dev, daddr);
		ctrl[31] = 1;
		ctrl[30] = 0;			// no intr for program setup;
		ctrl[29] = 1;			// write data phase;
		ctrl[28] = 0;			// no read data phase;
		ctrl[27:24] = adph;		// address phases;
		ctrl[23:16] = 8'h80;	// page program setup;
		ctrl[15] = 0;			// setup does not require ready;
		ctrl[14] = bufid;		// pi buffer with write data;
		ctrl[13:12] = dev;
		ctrl[11] = ecc;			// no ecc;
		ctrl[10] = 1;			// multi-cycle command;
		ctrl[9:0] = nbytes;		// write data;
		daddr[8] = 0;			// must be 0;
		pi_flash_cmd(daddr, ctrl, 0, 0);

		$display("test: %M: dev %d, addr 0x%h program", dev, daddr);
		ctrl[31] = 1;
		ctrl[30] = intr;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 0;			// no read data phase;
		ctrl[27:24] = 4'd0;		// no address phases;
		ctrl[23:16] = 8'h10;	// program execute;
		ctrl[15] = wrdy;
		ctrl[14] = $random;		// don't care about buffer;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// last of multi-cycle command;
		ctrl[9:0] = 0;			// no data;
		daddr[8] = 0;			// must be 0;
		pi_flash_cmd(daddr, ctrl, `FL_RDY_PROG, 0);
	end
endtask

// start a flash command;
// does not wait for ready and has no data phases;
// used by reset test;

task pi_flash_start_cmd;
	input [1:0] dev;		// device;
	input [3:0] adph;		// address phase mask;
	input [7:0] cmd;		// flash command;
	reg [31:0] ctrl;		// flash controller command;
	begin
		$display("test: %M: dev %d, cmd 0x%h", dev, cmd);
		ctrl[31] = 1;
		ctrl[30] = 0;			// no intr;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 0;			// no read data phase;
		ctrl[27:24] = adph;		// address phases;
		ctrl[23:16] = cmd;		// command;
		ctrl[15] = 0;			// don't wait for ready;
		ctrl[14] = $random;		// don't care about buffer;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = $random;	// don't care;
		pi_flash_cmd(0, ctrl, 0, 0);
	end
endtask

// test flash reset;

task pi_flash_reset;
	input [1:0] dev;		// device;
	reg [31:0] ctrl;		// flash controller command;
	begin
		$display("test: %M: dev %d", dev);
		ctrl[31] = 1;
		ctrl[30] = 0;			// no intr;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 0;			// no read data phase;
		ctrl[27:24] = 4'd0;		// no address phases;
		ctrl[23:16] = 8'hff;	// reset command;
		ctrl[15] = 1;			// wait for ready;
		ctrl[14] = $random;		// don't care about buffer;
		ctrl[13:12] = dev;
		ctrl[11] = 0;			// no ecc;
		ctrl[10] = 0;			// single command;
		ctrl[9:0] = $random;	// don't care;
		pi_flash_cmd(0, ctrl, `FL_RDY_RESET, 0);
	end
endtask

// setup pi buffer for flash read test;
// patterns contains address and page index;
// store lower address bits in each byte of the 32-bit word;

task pi_flash_buf_setup;
	reg [31:0] addr;		// pi buffer address;
	reg [31:0] wdata;		// write data;
	integer n;
	begin
		$display("%t: %M", $time);
		addr = `PI_BUF;
		for(n = 0; n < 128; n = n + 1) begin
			wdata[7:0] = n;
			wdata[15:8] = ~n;
			wdata[23:16] = n;
			wdata[31:24] = 8'd0;
			swrite(addr | `PI_BUF0, `CPU_SIZE_4, wdata);
			wdata[31:24] = 8'd1;
			swrite(addr | `PI_BUF1, `CPU_SIZE_4, wdata);
			addr = addr + 4;
		end
		addr = `PI_BUF;
		for(n = 128; n < 132; n = n + 1) begin
			wdata[7:0] = n;
			wdata[15:8] = ~n;
			wdata[23:16] = n;
			wdata[31:24] = 8'd0;
			swrite(addr | `PI_SP0, `CPU_SIZE_4, wdata);
			wdata[31:24] = 8'd1;
			swrite(addr | `PI_SP1, `CPU_SIZE_4, wdata);
			addr = addr + 4;
		end
	end
endtask

// check pi buffer after flash read;

task pi_flash_read_check;
	input bufid;			// buffer id;
	input [31:0] daddr;		// device address;
	input [9:0] nbytes;		// # of bytes;
	input chkob;			// check other buffer;
	input [2:0] pbidx;		// page buffer index;
	reg [31:0] addr;		// pi buffer address;
	reg [31:0] rdata;		// read data;
	reg [31:0] eaddr;		// end address of current page;
	reg [31:0] laddr;		// last byte address;
	reg [31:0] mask;		// byte mask;
	reg [31:0] lmask;		// last byte mask;
	reg [31:0] pat;			// flash pattern;
	integer paddr;			// pattern address;
	integer n;
	reg addr_out;			// address outside read area;
	begin
		// check that the other buffer is untouched;

		if(chkob) begin
			$display("%t: %M: checking other buf %b", $time, ~bufid);
			addr = `PI_BUF;
			addr[9] = ~bufid;
			for(n = 0; n < (128 + 4); n = n + 1) begin
				sread(addr, `CPU_SIZE_4, rdata);
				pat[7:0] = n;
				pat[15:8] = ~n;
				pat[23:16] = n;
				pat[31:24] = { 7'd0, ~bufid };
				$display("%t: n=%d pat=0x%h", $time, n, pat);
				rd_check(0, pat, 32'hffffffff, 0);
				if(addr[8:2] == 7'd127) begin
					addr = `PI_BUF + 1024;
					addr[4] = ~bufid;
				end else
					addr = addr + 4;
			end
		end

		// check the read target buffer;
		// the partial data starts within the first 512 bytes,
		// but can span into the spare area;

		$display("%t: %M: checking buf %b, off %0d, len %0d",
			$time, bufid, daddr[8:0], nbytes);
		addr = `PI_BUF;
		addr[9] = bufid;
		addr[8:2] = daddr[8:2];
		mask = 32'hffff_ffff >> (8 * daddr[1:0]);
		laddr = daddr + nbytes - 1;
		eaddr = { daddr[31:9], 9'd0 } + 527;
		if(laddr > eaddr)
			laddr = eaddr;
		lmask = 32'hffff_ffff << (8 * (3 - laddr[1:0]));
		n = laddr[31:2] - daddr[31:2];
		paddr = (pbidx * 528) + addr[8:0];
		while(n >= 0) begin
			sread(addr, `CPU_SIZE_4, rdata);
			pat[31:24] = flash_pat[paddr + 0];
			pat[23:16] = flash_pat[paddr + 1];
			pat[15:8] = flash_pat[paddr + 2];
			pat[7:0] = flash_pat[paddr + 3];
			paddr = paddr + 4;
			if(n == 0)
				mask = mask & lmask;
			rd_check(0, pat, mask, 0);
			mask = 32'hffff_ffff;
			if(addr[8:2] == 7'd127) begin
				addr = `PI_BUF + 1024;
				addr[4] = bufid;
			end else
				addr = addr + 4;
			n = n - 1;
		end
	end
endtask

// check spare data read into pi buffer;

task pi_flash_spare_check;
	input bufid;			// buffer id;
	input [31:0] daddr;		// device address;
	input [1:0] pbidx;		// page buffer index;
	reg [31:0] addr;		// pi buffer address;
	reg [31:0] rdata;		// read data;
	reg [31:0] pat;			// flash pattern;
	integer paddr;			// pattern address;
	integer n;
	begin
		$display("%t: %M: checking spare data buf %b, off %0d",
			$time, bufid, daddr[8:0]);
		addr = `PI_BUF;
		addr[9] = bufid;
		addr[8:2] = daddr[8:2];
		paddr = pbidx * 528 + 512;
		for(n = 0; n < 4; n = n + 1) begin
			sread(addr, `CPU_SIZE_4, rdata);
			pat[31:24] = flash_pat[paddr + 0];
			pat[23:16] = flash_pat[paddr + 1];
			pat[15:8] = flash_pat[paddr + 2];
			pat[7:0] = flash_pat[paddr + 3];
			paddr = paddr + 4;
			rd_check(0, pat, 32'hffff_ffff, 0);
			addr = addr + 4;
		end
	end
endtask

// check erased page in pi buffer;

task pi_flash_erase_check;
	input bufid;			// buffer id;
	reg [31:0] addr;		// pi buffer address;
	reg [31:0] rdata;		// read data;
	integer n;
	begin
		// check that the other buffer is untouched;

		$display("%t: %M: checking buf %b", $time, bufid);
		addr = `PI_BUF;
		addr[9] = bufid;
		for(n = 0; n < (128 + 4); n = n + 1) begin
			sread(addr, `CPU_SIZE_4, rdata);
			rd_check(0, 32'hffff_ffff, 32'hffff_ffff, 0);
			if(addr[8:2] == 7'd127) begin
				addr = `PI_BUF + 1024;
				addr[4] = bufid;
			end else
				addr = addr + 4;
		end
	end
endtask

// spin on device readies;
// use read status command to read per device ready;

task pi_flash_wait_ready;
	input [31:0] to;		// timeout in ns;
	inout [3:0] devrdy;		// device ready bits;
	reg [7:0] status;		// flash status byte;
	integer dev;			// flash device;
	integer n;
	begin
		$display("%t: %M", $time);
		to = to / (32000 * vsim.sysclk_period);
		for(n = 32; n > 0; n = n - 1) begin
			repeat(to) @(posedge sysclk);
			for(dev = 0; dev < 4; dev = dev + 1) begin
				if(flash_present[dev]) begin
					pi_flash_status(dev, dev[0], status);
					if(status[6])
						devrdy[dev] = 1;
				end
			end
			if(devrdy === 4'b1111)
				n = 0;
			$display("%t: %M: device ready %b ", $time, devrdy);
		end
	end
endtask

// query flash devices;

task pi_flash_detect;
	input wp;				// flash is write-protected;
	integer dev;			// device id;
	reg [7:0] status;		// flash status;
	begin
		// read the device ids of all flash ports;
		// PI_FLASH_CONF is still the reset default;
		// status must be ready and write-protected;

		$display("test: %M: device detection");
		for(dev = 0; dev < 4; dev = dev + 1) begin
			pi_flash_read_id(dev, dev[0]);
			if(vsim.mm.fl_comp[dev] & ~flash_present[dev])
				$display("ERROR: %t: %M: dev %0d compiled in, but not detected", $time, dev);
			if(flash_present[dev] === 1) begin
				pi_flash_status(dev, dev[0], status);
				if(status !== { 1'b0, wp, 6'd0 })
					$display("ERROR: %t: %M: status 0x%h exp 0x40", $time, status);
			end
		end
	end
endtask

// setup data for page programming;

task pi_flash_program_data;
	input bufid;			// pi buffer to use;
	input [2:0] pbidx;		// page buffer index;
	reg [31:0] addr;		// pi buffer address;
	reg [31:0] pat;			// flash pattern;
	integer paddr;			// pattern address;
	integer n;
	begin
		$display("%t: %M: page pattern %d", $time, pbidx);
		addr = `PI_BUF;
		addr[9] = bufid;
		paddr = pbidx * 528;
		for(n = 0; n < (128 + 4); n = n + 1) begin
			pat[31:24] = flash_pat[paddr + 0];
			pat[23:16] = flash_pat[paddr + 1];
			pat[15:8] = flash_pat[paddr + 2];
			pat[7:0] = flash_pat[paddr + 3];
			paddr = paddr + 4;
			swrite(addr, `CPU_SIZE_4, pat);
			$display("%t: n=%d pat=0x%h", $time, n, pat);
			if(addr[8:2] == 7'd127) begin
				addr = `PI_BUF + 1024;
				addr[4] = bufid;
			end else
				addr = addr + 4;
		end
	end
endtask

// flash read tests;
// all flash devices are preloaded from the same file ./External_File.txt;
// cannot be changed for samsung models because they are protected .v;
// devices 0..3 read blocks 0..3 from the flash;
// each block contains 528 random bytes, ecc is not valid;

task pi_flash_read_tests;
	integer dev;			// flash device;
	reg [31:0] daddr;		// device address;
	reg [9:0] size;			// data size;
	reg bufid;				// pi buffer to use;
	integer n;
	begin
		// test that complete block read works;
		// read starts at begin of page and reads 528 bytes;
		// lowest device bit determines which pi buffer is used;
		// don't use ecc to test all bytes;

		$readmemh("./External_File.txt", flash_pat);
		$display("test: %M: full page reads");
		daddr[31:11] = 0;
		daddr[8:0] = 0;
		size = 528;
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev] === 1) begin
				daddr[10:9] = dev;
				bufid = dev[0];
				pi_flash_buf_setup;
				pi_flash_read_page(dev, bufid, daddr, size, flash_adph[dev], 0, $random, 2'b00);
				pi_flash_read_check(bufid, daddr, size, 1, dev);
			end
		end

		// run a number of partial read tests;
		// pick random pi buffer to use;
		// pick random page offset and read length;
		// ecc cannot be used;

		daddr[31:11] = 0;
		for(n = 0; n < `N_PI_FLASH_PARTIAL; n = n + 1) begin
			$display("test: %M: partial page reads, round %0d", n);
			for(dev = 0; dev < 4; dev = dev + 1) begin
				if(flash_present[dev] === 1) begin
					daddr[10:9] = dev;
					daddr[8:0] = $random;
					size = 1 + $random;
					bufid = $random;
					pi_flash_buf_setup;
					pi_flash_read_page(dev, bufid, daddr, size, flash_adph[dev], 0, $random, 2'b00);
					pi_flash_read_check(bufid, daddr, size, 1, dev);
				end
			end
		end

		// test read of spare area;
		// pick random pi buffer to use;
		// device 0..3 read into buffer offsets 0,80,160,320;
		// do not check the other pi buffer for speed reasons;
		// ecc cannot be used;

		$display("test: %M: spare data read");
		daddr[31:11] = 0;
		daddr[8] = 0;
		daddr[3:0] = 0;
		size = 16;
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev] === 1) begin
				daddr[10:9] = dev;
				daddr[7:6] = dev;
				daddr[5:4] = dev;
				bufid = $random;
				pi_flash_read_spare(dev, bufid, daddr, size, flash_adph[dev], $random);
				pi_flash_spare_check(bufid, daddr, dev);
			end
		end
	end
endtask

// test flash block erasure and programming;

task pi_flash_ep_tests;
	integer dev;			// flash device;
	reg [31:0] daddr;		// device address;
	reg [9:0] size;			// data size;
	reg [31:0] baddr [0:3];	// unique block addresses;
	reg [3:0] devrdy;		// device done;
	reg bufid;				// pi buffer to use;
	begin
		// smallest device is 8MB;
		// pick block addresses so that all address bits toggle;

		baddr[0] = 32'b0000000_0010101001010101_0xxxxxxxx;
		baddr[1] = 32'b0000000_0111101111011110_0xxxxxxxx;
		baddr[2] = 32'b0000000_1100110001110001_0xxxxxxxx;
		baddr[3] = 32'b0000000_0001010110101010_0xxxxxxxx;

		// issue block erase to all devices in parallel, because
		// `FL_RDY_ERASE takes a long time in the simulator;
		// pi_flash_erase does not wait for ready;

		$display("test: %M: block erase");
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev])
				pi_flash_erase(dev, baddr[dev], 4'b1110, 0, `FL_EP_SERIAL);
			devrdy[dev] = ~flash_present[dev];
		end

		// wait for all devices to signal ready;
		// use read status command to check ready per device;
		// time out after FL_RDY_ERASE;

		pi_flash_wait_ready(`FL_RDY_ERASE, devrdy);
		if(devrdy !== 4'b1111)
			$display("ERROR: %t: %M: flash not ready after erase %b", $time, devrdy);

		// verify that a page of erased block is all 1s;
		// page checked is the device index from the start of the block;
		// read starts at begin of page and reads 528 bytes;
		// lowest device bit determines which pi buffer is used;
		// don't use ecc to test all bytes;
		// smallest device has 8kbyte blocks;

		$display("test: %M: check erased block all 1s");
		size = 528;
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev] === 1) begin
				daddr = baddr[dev];
				daddr[12:11] = 2'd0;
				daddr[10:9] = dev;
				daddr[8:0] = 9'd0;
				bufid = $random;
				pi_flash_read_page(dev, bufid, daddr, size, flash_adph[dev], 0, $random, 2'b00);
				pi_flash_erase_check(bufid);
			end
		end

		// test flash block program;
		// program device 0..3 with read pages 3..0;
		// use same page address of erase test;
		// pick random pi buffer to use;
		// issue page program to all devices in parallel, because
		// `FL_RDY_PROG takes a long time in the simulator;

		$display("test: %M: page program");
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev]) begin
				daddr = baddr[dev];
				daddr[12:11] = 2'd0;
				daddr[10:9] = dev;
				daddr[8:0] = 9'd0;
				bufid = $random;
				pi_flash_program_data(bufid, 3 - dev);
				pi_flash_program(dev, bufid, daddr, 528, flash_adph[dev], 0, `FL_EP_SERIAL, 0);
			end
			devrdy[dev] = ~flash_present[dev];
		end

		// wait for all devices to signal ready;
		// use read status command to check ready per device;
		// time out after FL_RDY_PROG;

		pi_flash_wait_ready(`FL_RDY_PROG, devrdy);
		if(devrdy !== 4'b1111)
			$display("ERROR: %t: %M: flash not ready after program %b", $time, devrdy);

		// read back programmed data and compare;
		// read starts at begin of page and reads 528 bytes;
		// pick random pi buffer to use;
		// don't use ecc to test all bytes;

		$display("test: %M: page verify after program");
		size = 528;
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev] === 1) begin
				daddr = baddr[dev];
				daddr[12:11] = 2'd0;
				daddr[10:9] = dev;
				daddr[8:0] = 9'd0;
				bufid = $random;
				pi_flash_read_page(dev, bufid, daddr, size, flash_adph[dev], 0, $random, 2'b00);
				pi_flash_read_check(bufid, daddr, size, 0, 3 - dev);
			end
		end
	end
endtask

// calculate ecc over 256 byte block in flash_pat[];

task pi_flash_ecc_gen;
	input [2:0] pbidx;		// page index;
	input buf01;			// first or second 256-byte block;
	output [23:0] ecc;		// calculated ecc bytes;
	integer n;
	reg [7:0] b;			// input byte;
	reg bp;					// byte parity;
	reg [10:0] ph, pl;		// upper/lower row/col parity;
	integer paddr;			// pattern address;
	begin
		ph = 0;
		pl = 0;
		paddr = 528 * pbidx;
		if(buf01)
			paddr = paddr + 256;
		for(n = 0; n < 256; n = n + 1) begin
			b = flash_pat[n + paddr];
			bp = ^b;
			ph[2] = ph[2] ^ b[7] ^ b[6] ^ b[5] ^ b[4];
			pl[2] = pl[2] ^ b[3] ^ b[2] ^ b[1] ^ b[0];
			ph[1] = ph[1] ^ b[7] ^ b[6] ^ b[3] ^ b[2];
			pl[1] = pl[1] ^ b[5] ^ b[4] ^ b[1] ^ b[0];
			ph[0] = ph[0] ^ b[7] ^ b[5] ^ b[3] ^ b[1];
			pl[0] = pl[0] ^ b[6] ^ b[4] ^ b[2] ^ b[0];
			if( ~n[0])
				pl[3] = pl[3] ^ bp;
			if( n[0])
				ph[3] = ph[3] ^ bp;
			if( ~n[1])
				pl[4] = pl[4] ^ bp;
			if( n[1])
				ph[4] = ph[4] ^ bp;
			if( ~n[2])
				pl[5] = pl[5] ^ bp;
			if( n[2])
				ph[5] = ph[5] ^ bp;
			if( ~n[3])
				pl[6] = pl[6] ^ bp;
			if( n[3])
				ph[6] = ph[6] ^ bp;
			if( ~n[4])
				pl[7] = pl[7] ^ bp;
			if( n[4])
				ph[7] = ph[7] ^ bp;
			if( ~n[5])
				pl[8] = pl[8] ^ bp;
			if( n[5])
				ph[8] = ph[8] ^ bp;
			if( ~n[6])
				pl[9] = pl[9] ^ bp;
			if( n[6])
				ph[9] = ph[9] ^ bp;
			if( ~n[7])
				pl[10] = pl[10] ^ bp;
			if( n[7])
				ph[10] = ph[10] ^ bp;
		end
		ecc = ~{ ph[6], pl[6], ph[5], pl[5], ph[4], pl[4], ph[3], pl[3],
			ph[10], pl[10], ph[9], pl[9], ph[8], pl[8], ph[7], pl[7],
			ph[2], pl[2], ph[1], pl[1], ph[0], pl[0], 2'b00 };
		$display("%t: %M: buf%0d ph 0x%h pl 0x%h ecc 0x%h",
			$time, buf01, ph, pl, ecc);
	end
endtask

// store calculated ecc into buffer;

task pi_flash_ecc_store;
	input [2:0] pbidx;		// page buffer index;
	input [9:0] off;		// byte offset in buffer;
	input [23:0] ecc;		// ecc bytes;
	integer idx;
	begin
		idx = off + (528 * pbidx);
		flash_pat[idx + 0] = ecc[23:16];
		flash_pat[idx + 1] = ecc[15:8];
		flash_pat[idx + 2] = ecc[7:0];
	end
endtask

// flip a data or ecc bit in one half;
// data region had 256 bits;
// ecc is 22 bits;
// map bits to msg first;

task pi_flash_flip_bits;
	input [2:0] pbidx;		// page buffer index;
	input buf01;			// which half to modify;
	input [1:0] nerr;		// # of bits to flip;
	input dex;				// flip data=0 or ecc=1 bits;
	integer addr;			// byte address;
	reg [10:0] bit;			// byte and bit to modify;
	integer off;
	integer paddr;			// page buffer address;
	reg [11:0] flipped;		// bits already flipped;
	begin
		case({ buf01, dex })
			2'b00: off = 0;
			2'b10: off = 256;
			2'b01: off = 525;
			2'b11: off = 520;
		endcase
		flipped = { 1'b1, 11'd0 };
		while(nerr > 0) begin
			bit = $random;
			while(bit == flipped)
				bit = $random;
			while(dex & (bit >= 22))
				bit = $random & 'h1f;
			bit[2:0] = ~bit[2:0];
			flipped = bit;
			addr = off + bit[10:3];
			paddr = (528 * pbidx) + addr;
			flash_pat[paddr] = flash_pat[paddr] ^ (1 << bit[2:0]);
			$display("%t: %M: buf %0d, half %b, %s, byte %0d, bit %0d",
				$time, pbidx, buf01, dex? "ecc" : "data", addr, bit[2:0]);
			nerr = nerr - 1;
		end
	end
endtask

// modify data or ecc bits in both halves;
// mode 0, no modification;
// mode 1, force single-bit errors, data, ecc;
// mode 2, force double-bit errors, data/data, ecc/ecc;
// mode 3, force double-bit errors, data/ecc, data/ecc;

task pi_flash_force_error;
	input [2:0] pbidx;		// page buffer index;
	input [1:0] mode;		// type of modification;
	begin
		case(mode)
			2'd0: ;
			2'd1: begin
				pi_flash_flip_bits(pbidx, 0, 1, 0);
				pi_flash_flip_bits(pbidx, 1, 1, 1);
			end
			2'd2: begin
				pi_flash_flip_bits(pbidx, 0, 2, 0);
				pi_flash_flip_bits(pbidx, 1, 2, 1);
			end
			2'd3: begin
				pi_flash_flip_bits(pbidx, 0, 1, 0);
				pi_flash_flip_bits(pbidx, 0, 1, 1);
				pi_flash_flip_bits(pbidx, 1, 1, 0);
				pi_flash_flip_bits(pbidx, 1, 1, 1);
			end
		endcase
	end
endtask

// ecc tests;
// must use erase, program, and read sequence,
// because flash models do not have a backdoor;

task pi_flash_ecc_tests_recover;
	integer dev;			// flash device;
	reg [31:0] daddr;		// device address;
	reg [9:0] size;			// data size;
	reg bufid;				// pi buffer to use;
	reg [3:0] devrdy;		// device done;
	reg [23:0] ecc;			// computed ecc;
	reg hwecc;				// let hardware compute ecc;
	reg [11:10] eccsts;		// ecc status;
	reg [1:0] ecctype;		// ecc test type;
	reg [2:0] pbidx;		// page buffer index;
	integer cmp_len;		// read compare length;
	integer n;
	begin
		$display("test: %M: ecc tests recover");

		// erase first block of all flash devices;
		// issue block erase to all devices in parallel, because
		// `FL_RDY_ERASE takes a long time in the simulator;
		// pi_flash_erase does not wait for ready;
		// do not test for erased bits all 1, takes too long;

		$display("test: %M: ecc block erase");
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev])
				pi_flash_erase(dev, 0, 4'b1110, 0, `FL_EP_SERIAL);
			devrdy[dev] = ~flash_present[dev];
		end

		// wait for all devices to signal ready;
		// use read status command to check ready per device;
		// time out after FL_RDY_ERASE;

		pi_flash_wait_ready(`FL_RDY_ERASE, devrdy);
		if(devrdy !== 4'b1111)
			$display("ERROR: %t: %M: flash not ready after erase %b", $time, devrdy);

		// program first few pages of all devices;
		// fill flash_pat[dev] with random data;
		// flash_pat[dev] is modified and sent out during program;
		// flash_pat[dev+4] is used for data check after read back;
		// page mod 0 has no ecc errors and hardware computed ecc;
		// page mod 1 has sbe in data, and sbe in ecc;
		// page mod 2 has dbe in data/data, and dbe in ecc/ecc;
		// page mod 3 has dbe in data/ecc, and data/ecc;

		for(n = 0; n < `N_PI_ECC_PAGES; n = n + 1) begin
			daddr = 512 * n;
			ecctype = n[1:0];
			ecctype = n[1:0];
			hwecc = (ecctype == 0);
			eccsts[11] = (ecctype == 1);
			eccsts[10] = (ecctype == 2) | (ecctype == 3);

			// program a page waiting for flash ready;
			// issue page program to all devices in parallel, because
			// `FL_RDY_PROG takes a long time in the simulator;
			// pi_flash_program does not wait for ready;

			for(dev = 0; dev < 4; dev = dev + 1) begin
				if(flash_present[dev]) begin
					$display("test: %M: dev %0d, ecc page %0d program", dev, n);
					pi_flash_buf_rand(dev);
					pi_flash_ecc_gen(dev, 0, ecc);
					pi_flash_ecc_store(dev, 525, ecc);
					pi_flash_ecc_gen(dev, 1, ecc);
					pi_flash_ecc_store(dev, 520, ecc);
					pi_flash_copy_pb(dev, dev + 4);
					bufid = $random;
					pi_flash_program_data(bufid, dev);
					pi_flash_program(dev, bufid, daddr, 528, flash_adph[dev], 0, `FL_EP_SERIAL, hwecc);
				end
			end

			// wait for all devices to signal ready;
			// use read status command to check ready per device;
			// time out after FL_RDY_PROG;

			pi_flash_wait_ready(`FL_RDY_PROG, devrdy);
			if(devrdy !== 4'b1111)
				$display("ERROR: %t: %M: flash not ready after program %b", $time, devrdy);
		end
	end
endtask

task pi_flash_ecc_tests;
	integer dev;			// flash device;
	reg [31:0] daddr;		// device address;
	reg [9:0] size;			// data size;
	reg bufid;				// pi buffer to use;
	reg [3:0] devrdy;		// device done;
	reg [23:0] ecc;			// computed ecc;
	reg hwecc;				// let hardware compute ecc;
	reg [11:10] eccsts;		// ecc status;
	reg [1:0] ecctype;		// ecc test type;
	reg [2:0] pbidx;		// page buffer index;
	integer cmp_len;		// read compare length;
	integer n;
	begin
		$display("test: %M: ecc tests");

		// erase first block of all flash devices;
		// issue block erase to all devices in parallel, because
		// `FL_RDY_ERASE takes a long time in the simulator;
		// pi_flash_erase does not wait for ready;
		// do not test for erased bits all 1, takes too long;

		$display("test: %M: ecc block erase");
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev])
				pi_flash_erase(dev, 0, 4'b1110, 0, `FL_EP_SERIAL);
			devrdy[dev] = ~flash_present[dev];
		end

		// wait for all devices to signal ready;
		// use read status command to check ready per device;
		// time out after FL_RDY_ERASE;

		pi_flash_wait_ready(`FL_RDY_ERASE, devrdy);
		if(devrdy !== 4'b1111)
			$display("ERROR: %t: %M: flash not ready after erase %b", $time, devrdy);

		// program first few pages of all devices;
		// fill flash_pat[dev] with random data;
		// flash_pat[dev] is modified and sent out during program;
		// flash_pat[dev+4] is used for data check after read back;
		// page mod 0 has no ecc errors and hardware computed ecc;
		// page mod 1 has sbe in data, and sbe in ecc;
		// page mod 2 has dbe in data/data, and dbe in ecc/ecc;
		// page mod 3 has dbe in data/ecc, and data/ecc;

		for(n = 0; n < `N_PI_ECC_PAGES; n = n + 1) begin
			daddr = 512 * n;
			ecctype = n[1:0];
			ecctype = n[1:0];
			hwecc = (ecctype == 0);
			eccsts[11] = (ecctype == 1);
			eccsts[10] = (ecctype == 2) | (ecctype == 3);

			// program a page waiting for flash ready;
			// issue page program to all devices in parallel, because
			// `FL_RDY_PROG takes a long time in the simulator;
			// pi_flash_program does not wait for ready;

			for(dev = 0; dev < 4; dev = dev + 1) begin
				if(flash_present[dev]) begin
					$display("test: %M: dev %0d, ecc page %0d program", dev, n);
					pi_flash_buf_rand(dev);
					pi_flash_ecc_gen(dev, 0, ecc);
					pi_flash_ecc_store(dev, 525, ecc);
					pi_flash_ecc_gen(dev, 1, ecc);
					pi_flash_ecc_store(dev, 520, ecc);
					pi_flash_copy_pb(dev, dev + 4);
					pi_flash_force_error(dev, ecctype);
					bufid = $random;
					pi_flash_program_data(bufid, dev);
					pi_flash_program(dev, bufid, daddr, 528, flash_adph[dev], 0, `FL_EP_SERIAL, hwecc);
				end
			end

			// wait for all devices to signal ready;
			// use read status command to check ready per device;
			// time out after FL_RDY_PROG;

			pi_flash_wait_ready(`FL_RDY_PROG, devrdy);
			if(devrdy !== 4'b1111)
				$display("ERROR: %t: %M: flash not ready after program %b", $time, devrdy);

			// read back ecc test pages;
			// test single-bit ecc detection and correction;
			// test recording of correctable single-bit errors;
			// test double-bit ecc detection and error handling;
			// use size of all 1s for full-page read;
			// for correctable errors, compare with original data;
			// for uncorrectable errors, compare data sent to flash;

			for(dev = 0; dev < 4; dev = dev + 1) begin
				if(flash_present[dev]) begin
					cmp_len = eccsts[11]? 512 : 528;
					$display("test: %M: dev %0d, ecc page %0d read, cmp %0d", dev, n, cmp_len);
					bufid = $random;
					pi_flash_read_page(dev, bufid, daddr, 'h3ff, flash_adph[dev], 1, $random, eccsts);
					pbidx = dev + (eccsts[10]? 0 : 4);
					pi_flash_read_check(bufid, daddr, cmp_len, 0, pbidx);
				end
			end
		end
	end
endtask

// test flash operations initiated by cpu;

task pi_flash_cpu;
	integer dev;			// flash device;
	reg [7:0] status;		// flash status byte;
	reg [9:0] size;			// data size;
	reg [31:0] wdata;		// write data;
	reg [31:0] rdata;		// read data;
	reg bufid;				// pi buffer to use;
	begin
		// configure nflash models;

		pi_nflash_conf(3, 16, 3, 2);

		// read the device ids of all flash ports;
		// PI_FLASH_CONF is still the reset default;
		// status must be ready and write-protected;
		// setup fastest timing config;

		pi_flash_detect(1);
		pi_flash_config(1);

		// test flash reads;
		// flash content is initialized from file;

		pi_flash_read_tests;

		// disable write-protect;

		$display("%t: %M: disabling write-protection", $time);
		sread(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);
		rdata[31] = 0;
		swrite(`PI_FLASH_CONF, `CPU_SIZE_4, rdata);

		// test flash block erasure and programming;

		pi_flash_ep_tests;

		// test ecc calculation, detection and correction;
`ifdef PI_ECC_TEST
		pi_flash_ecc_tests;       
		pi_flash_ecc_tests_recover;       
`endif
		// test multiple programs to same pages; // XXX

		// test stop of flash controller; // XXX

		// test abort of program with WP; // XXX

		// test flash reset command;
		// start device command without waiting for ready;
		// then kill it by sending the reset command;

		$display("test: %M: reset during page read");
		size = 528;
		for(dev = 0; dev < 4; dev = dev + 1) begin
			if(flash_present[dev] === 1) begin
				bufid = $random;
				pi_flash_start_cmd(dev, flash_adph[dev], 8'h00);
				pi_flash_reset(dev);
			end
		end
	end
endtask

// load aes init vector to pi buffer;

task pi_aes_load_iv;
	reg [31:0] addr;		// address;
	integer n;
	begin
		$display("%t: %M", $time);
		addr = `PI_AES_INIT;
		for(n = 0; n < 4; n = n + 1)
			swrite(addr + 4*n, `CPU_SIZE_4, aes_init[n]);
	end
endtask

// load expanded key to pi buffer;

task pi_aes_load_ekey;
	reg [31:0] addr;		// address;
	integer n;
	begin
		$display("%t: %M", $time);
		addr = `PI_AES_EKEY;
		for(n = 0; n < 44; n = n + 1)
			swrite(addr + 4*n, `CPU_SIZE_4, aes_ekey[n]);
	end
endtask
		
// load cypher text data to pi buffer;

task pi_aes_load_ctext;
	input [9:0] nw;			// # of 32-bit words;
	reg [31:0] addr;		// address;
	integer n;
	begin
		$display("%t: %M", $time);
		addr = `PI_BUF;
		for(n = 0; n < nw; n = n + 1)
			swrite(addr + 4*n, `CPU_SIZE_4, aes_ctext[n]);
	end
endtask

// test aes initiated through aes control register;

task pi_aes_run;
	input [7:0] da;			// data address;
	input [9:0] nw;			// # of 32-bit words;
	input hc;				// hw chaining;
	input intr;				// test interrupt;
	reg [31:0] addr;		// address;
	reg [31:0] ctrl;		// write data;
	reg [31:0] rdata;		// read data;
	integer n;
	reg rreq;				// random read request;
	begin
		// aes core should not be busy;

		$display("test: %M: da %0d, nw %0d, hc %b", da, nw, hc);
		sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 0)
			$display("ERROR: %t: %M: aes not idle %b", $time, rdata[31]);

		// start aes decryption;

		$display("test: %M: starting aes");
		ctrl[31] = 1;					// start aes operation;
		ctrl[30] = intr;
		ctrl[29:22] = 'd0;
		ctrl[21:16] = (nw >> 2) - 1;	// 128-bit words;
		ctrl[15:8] = da;				// pi buffer address;
		ctrl[7:0] = 154;				// pi init vector;
		ctrl[0] = hc;
		swrite(`PI_AES_CTRL, `CPU_SIZE_4, ctrl);

		// read back status register;
		// aes core should be busy;

		sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 1)
			$display("ERROR: %t: %M: aes not busy %b", $time, rdata[31]);

		// spin on aes busy status;
		// issue random intervening pi buffer operations;
		// scratch into atb buffer;
		// 16 bytes (128 bits) take up to 60 clocks;
		// cpu register reads/write average to about 10 clocks;

		n = ((nw / 4) * 60) / 10;
		while((n > 0) & (rdata[31] === 1)) begin
			rreq = $random;
			if(rreq)
				sread(`PI_BUF_ATB, `CPU_SIZE_4, rdata);
			else
				swrite(`PI_BUF_ATB, `CPU_SIZE_4, rdata);
			req_spacing($random);
			sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
			n = n - 1;
		end
		if(n <= 0)
			$display("ERROR: %t: %M: aes busy timeout %b", $time, rdata[31]);

		// check decrypted data in pi buffer;

		$display("test: %M: checking plain text");
		addr = `PI_BUF + (da << 3);
		for(n = 0; n < nw; n = n + 1) begin
			sread(addr + 4*n, `CPU_SIZE_4, rdata);
			rd_check(0, aes_ptext[n + da*2], 32'hffffffff, 0);
		end

		// check that interrupt is as expected;

		pi_intr_check(`MI_INTR_AES, intr);
		sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[30] !== intr)
			$display("ERROR: %t: %M: intr %b exp %b", $time, rdata[30], intr);

		// stop aes controller;
		// also clears interrupt;

		ctrl[31] = 0;
		ctrl[30] = 0;
		swrite(`PI_AES_CTRL, `CPU_SIZE_4, ctrl);

		// check that interrupt is cleared;

		pi_intr_check(`MI_INTR_AES, 0);
		sread(`PI_AES_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[31] !== 0)
			$display("ERROR: %t: %M: unexpected busy %b", $time, rdata[31]);
		if(rdata[30] !== 0)
			$display("ERROR: %t: %M: unexpected intr %b", $time, rdata[30]);
	end
endtask

// test aes decryption initiated by cpu;

task pi_aes_cpu;
	begin
		// test cast pattern with interrupt disabled;

		$display("test: %M: cast test bench pattern");
		aes_init[0] = 32'h00010203;
		aes_init[1] = 32'h04050607;
		aes_init[2] = 32'h08090a0b;
		aes_init[3] = 32'h0c0d0e0f;
		aes_ekey[0] = 32'hd014f9a8;
		aes_ekey[1] = 32'hc9ee2589;
		aes_ekey[2] = 32'he13f0cc8;
		aes_ekey[3] = 32'hb6630ca6;
		aes_ekey[4] = 32'h0c7b5a63;
		aes_ekey[5] = 32'h1319eafe;
		aes_ekey[6] = 32'hb0398890;
		aes_ekey[7] = 32'h664cfbb4;
		aes_ekey[8] = 32'hdf7d925a;
		aes_ekey[9] = 32'h1f62b09d;
		aes_ekey[10] = 32'ha320626e;
		aes_ekey[11] = 32'hd6757324;
		aes_ekey[12] = 32'h12c07647;
		aes_ekey[13] = 32'hc01f22c7;
		aes_ekey[14] = 32'hbc42d2f3;
		aes_ekey[15] = 32'h7555114a;
		aes_ekey[16] = 32'h6efcd876;
		aes_ekey[17] = 32'hd2df5480;
		aes_ekey[18] = 32'h7c5df034;
		aes_ekey[19] = 32'hc917c3b9;
		aes_ekey[20] = 32'h6ea30afc;
		aes_ekey[21] = 32'hbc238cf6;
		aes_ekey[22] = 32'hae82a4b4;
		aes_ekey[23] = 32'hb54a338d;
		aes_ekey[24] = 32'h90884413;
		aes_ekey[25] = 32'hd280860a;
		aes_ekey[26] = 32'h12a12842;
		aes_ekey[27] = 32'h1bc89739;
		aes_ekey[28] = 32'h7c1f13f7;
		aes_ekey[29] = 32'h4208c219;
		aes_ekey[30] = 32'hc021ae48;
		aes_ekey[31] = 32'h0969bf7b;
		aes_ekey[32] = 32'hcc7505eb;
		aes_ekey[33] = 32'h3e17d1ee;
		aes_ekey[34] = 32'h82296c51;
		aes_ekey[35] = 32'hc9481133;
		aes_ekey[36] = 32'h2b3708a7;
		aes_ekey[37] = 32'hf262d405;
		aes_ekey[38] = 32'hbc3ebdbf;
		aes_ekey[39] = 32'h4b617d62;
		aes_ekey[40] = 32'h2b7e1516;
		aes_ekey[41] = 32'h28aed2a6;
		aes_ekey[42] = 32'habf71588;
		aes_ekey[43] = 32'h09cf4f3c;
		aes_ctext[0] = 32'h7649abac;
		aes_ctext[1] = 32'h8119b246;
		aes_ctext[2] = 32'hcee98e9b;
		aes_ctext[3] = 32'h12e9197d;
		aes_ctext[4] = 32'h5086cb9b;
		aes_ctext[5] = 32'h507219ee;
		aes_ctext[6] = 32'h95db113a;
		aes_ctext[7] = 32'h917678b2;
		aes_ctext[8] = 32'h73bed6b8;
		aes_ctext[9] = 32'he3c1743b;
		aes_ctext[10] = 32'h7116e69e;
		aes_ctext[11] = 32'h22229516;
		aes_ctext[12] = 32'h3ff1caa1;
		aes_ctext[13] = 32'h681fac09;
		aes_ctext[14] = 32'h120eca30;
		aes_ctext[15] = 32'h7586e1a7;
		aes_ptext[0] = 32'h6bc1bee2;
		aes_ptext[1] = 32'h2e409f96;
		aes_ptext[2] = 32'he93d7e11;
		aes_ptext[3] = 32'h7393172a;
		aes_ptext[4] = 32'hae2d8a57;
		aes_ptext[5] = 32'h1e03ac9c;
		aes_ptext[6] = 32'h9eb76fac;
		aes_ptext[7] = 32'h45af8e51;
		aes_ptext[8] = 32'h30c81c46;
		aes_ptext[9] = 32'ha35ce411;
		aes_ptext[10] = 32'he5fbc119;
		aes_ptext[11] = 32'h1a0a52ef;
		aes_ptext[12] = 32'hf69f2445;
		aes_ptext[13] = 32'hdf4f9b17;
		aes_ptext[14] = 32'had2b417b;
		aes_ptext[15] = 32'he66c3710;
		pi_aes_load_iv;
		pi_aes_load_ekey;
		pi_aes_load_ctext(16);
		pi_aes_run(0, 16, 0, 0);

		// test broadon pattern with interrupt enabled;
		// read init vector, expanded key and data from files;

		$display("test: %M: random test pattern");
		$readmemh("tests/pi_init.dat", aes_init);
		$readmemh("tests/pi_ekey.dat", aes_ekey);
		$readmemh("tests/pi_ctext.dat", aes_ctext);
		$readmemh("tests/pi_ptext.dat", aes_ptext);
		pi_aes_load_iv;
		pi_aes_load_ekey;

		// decrypt 512 byte block without hw chaining;

		pi_aes_load_ctext(128);
		pi_aes_run(0, 128, 0, 1);

		// decrypt 1k block with two requests and hw chaining;

		pi_aes_load_ctext(256);
		pi_aes_run(0, 128, 0, 1);
		pi_aes_run(64, 128, 1, 1);
	end
endtask

// monitor atb signals;

reg atb_done;		// done flag;
integer atb_nlu;	// # of lookups;

always @(posedge vsim.bb.bcp.pi.atb_done)
	atb_done = 1;
always @(posedge vsim.bb.bcp.pi.atb_req)
	atb_nlu = atb_nlu + 1;

// run a single atb lookup;

task pi_atb_exec;
	input map;				// map v->p address;
	input [15:0] vpage;		// virtual page to lookup;
	input [15:0] ppage;		// physical page for pass-through;
	input [1:0] pdev;		// physical device;
	input experr;			// expected error;
	input [3:0] nlu;		// # of expected lookups;
	reg err;				// error;
	reg [13:0] poff;		// page offset;
	reg [15:0] page;		// page address;
	reg [1:0] dev;			// device;
	reg [31:0] rdata;		// read data;
	integer n;
	begin
`ifdef	SIMGATE
		$display("test: %M: Warning: not done on gate-level");
`else	// SIMGATE
		$display("test: %M: vpage 0x%h", vpage);
		atb_done = 0;
		atb_nlu = 0;
		poff = $random;
`ifdef	ATB_NOMAP
		vsim.bb.bcp.pi.atb_map = map;
`endif	// ATB_NOMAP
		vsim.bb.bcp.pi.atb_vaddr = { 2'b00, vpage, poff };
		@(posedge sysclk);
		vsim.bb.bcp.pi.atb_start <= 1;
		@(posedge sysclk);
		vsim.bb.bcp.pi.atb_start <= 0;

		// wait for atb_done;
		// issue intervening pio cycles to pi buffer;

		for(n = 0; n < 8; n = n + 1) begin
			sread(`PI_BUF_ATB, `CPU_SIZE_4, rdata);
			if(atb_done)
				n = 10;
		end
		if(n == 8)
			$display("ERROR: %t: %M: atb timeout", $time);
		if(atb_nlu > 7)
			$display("ERROR: %t: %M: atb_nlu %0d too big", $time, atb_nlu);
		if( ~nlu[3] & (atb_nlu !== nlu[2:0]))
			$display("ERROR: %t: %M: atb cache problem, atb_nlu %0d", $time, atb_nlu);

		// check lookup result;

		err = vsim.bb.bcp.pi.atb_err;
		if(err !== experr)
			$display("ERROR: %t: %M: atb error %b exp %b", $time, err, experr);
		if( !experr) begin
			page = vsim.bb.bcp.pi.atb_paddr[29:14];
			if(page !== ppage)
				$display("ERROR: %t: %M: atb ppage 0x%h exp 0x%h", $time, page, ppage);
			dev = vsim.bb.bcp.pi.atb_pdev;
			if(dev !== pdev)
				$display("ERROR: %t: %M: atb pdev %b exp %b", $time, dev, pdev);
		end
`endif	// SIMGATE
	end
endtask

// directed atb tests;
// atb does not have a direct cpu interface;
// test it by overwriting verilog signals;

task pi_atb_tests;
	reg [8:0] atbu;			// upper atb bits;
	reg [15:0] vpage;		// virtual page address;
	reg [15:0] ppage;		// physical page address;
	reg [31:0] addr;		// cpu address;
	integer n;
	reg [7:0] idx;			// pattern index;
	begin
		// load atb with increasing pattern;
		// r/w permission, block size 16k;
		// device bits in atb entry will be set to index;
		// leave lower and upper vpage addresses free for miss test;

		$display("test: %M: loading atb for hit/miss tests");
		addr = `PI_BUF_ATB;
		atbu = { 1'b0, 2'b00, 2'b11, 4'b0000 };
		n = 0;
		while(n < `PI_N_ATB) begin
			atbu[7:6] = n[1:0];
			swrite(`PI_ATBU, `CPU_SIZE_4, atbu);
			ppage = 256 + n;
			n = n + 1;
			vpage[15:8] = n;
			vpage[7:0] = n;
			swrite(addr, `CPU_SIZE_4, { ppage, vpage });
			addr = addr + 4;
		end

		// lookup pages outside of atb area;
		// must fail at either end of atb area;
		// lookup twice to check that cache misses;

		$display("test: %M: miss tests");
		pi_atb_exec(1, 16'h0000, 16'bx, 2'bx, 1, 2);
		pi_atb_exec(1, 16'h0000, 16'bx, 2'bx, 1, 2);
		pi_atb_exec(1, 16'hffff, 16'bx, 2'bx, 1, 7);
		pi_atb_exec(1, 16'hffff, 16'bx, 2'bx, 1, 7);

		// lookup first and last atb entry;
		// must hit without error at either end of atb area;
		// lookup twice to check cache hit;

		$display("test: %M: hit tests");
		pi_atb_exec(1, 16'h0101, 16'h0100, 2'd0, 0, 2);
		pi_atb_exec(1, 16'h0101, 16'h0100, 2'd0, 0, 0);
		pi_atb_exec(1, 16'hc0c0, 16'h01bf, 2'd3, 0, 7);
		pi_atb_exec(1, 16'hc0c0, 16'h01bf, 2'd3, 0, 0);

		// check that unmapped request invalidates cache;

`ifdef	ATB_NOMAP
		$display("test: %M: unmapped invalidates");
		pi_atb_exec(1, 16'h0202, 16'h0101, 2'd1, 0, 2);
		vpage = $random;
		pi_atb_exec(0, vpage, vpage, 2'd3, 0, 0);
		pi_atb_exec(1, 16'h0202, 16'h0101, 2'd1, 0, 2);
`endif	// ATB_NOMAP

		// test a number of random entries;

		$display("test: %M: random hit tests");
		for(n = 0; n < `N_PI_ATB_RAND; n = n + 1) begin
			idx = $random;
			while(idx >= `PI_N_ATB)
				idx = $random;
			vpage[15:8] = idx + 1;
			vpage[7:0] = idx + 1;
			ppage = 256 + idx;
			pi_atb_exec(1, vpage, ppage, idx[1:0], 0, 8);
		end

		// initialize atb for size test;
		// setup vpage from biggest to smallest;
		// ppage is mapped to opposite region;

		$display("test: %M: loading atb for size tests");
		addr = `PI_BUF_ATB;
		atbu[8] = 0;
		atbu[5:4] = 2'b11;
		for(n = 0; n < `PI_N_ATB; n = n + 1) begin
			atbu[7:6] = n[1:0];
			if(n < 16) begin
				atbu[3:0] = 15 - n;		
				vpage = (16'hfffe << (15 - n));
				ppage = (1 << (15 - n));
			end else begin
				atbu[3:0] = 0;
				vpage = 16'hffff;
				ppage = 16'h0000;
			end
			swrite(`PI_ATBU, `CPU_SIZE_4, atbu);
			swrite(addr, `CPU_SIZE_4, { ppage, vpage });
			addr = addr + 4;
		end

		// test atb lookups per size;

		for(n = 0; n < 16; n = n + 1) begin
			$display("test: %M: atb size %0d", 15 - n);
			vpage = (16'hfffe << (15 - n));
			ppage = (1 << (15 - n));
			pi_atb_exec(1, vpage, ppage, n[1:0], 0, 8);
		end
	end
endtask

// access test for single word;
// can be used for registers and memory;

task pi_acc_word;
	input [7:0] acc;		// access rights;
	input [31:0] addr;		// register address;
	input mem;				// is memory;
	reg [31:0] orig;		// original data;
	reg [31:0] rdata;		// read data;
	begin
		// if memory, setup pattern;

		$display("test: %M: reg 0x%h", addr);
		pi_access(acc);
		if(mem) begin
			orig = $random;
			swrite(addr, `CPU_SIZE_4, orig);
		end

		// read original value;
		// disable access;
		// should still succeed because we are in secure mode;

		sread(addr, `CPU_SIZE_4, orig);
		pi_access(8'h00);
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, orig, 32'hffff_ffff, 0);

		// setup access rights for non-secure mode;
		// leave secure mode;

		pi_access(acc);
		mi_sec_mode_leave;

		// read with access enabled;
		// write new pattern;

		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, orig, 32'hffff_ffff, 0);
		if(mem) begin
			orig = $random;
			swrite(addr, `CPU_SIZE_4, orig);
			sread(addr, `CPU_SIZE_4, rdata);
			rd_check(0, orig, 32'hffff_ffff, 0);
		end

		// turn off access right;
		// writes should be ignored;
		// reads should return 0;

		pi_access(8'h00);
		swrite(addr, `CPU_SIZE_4, $random);
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, 32'd0, 32'hffff_ffff, 0);

		// re-enter secure mode;
		// check that orignal value is there;
		// access disabled should not matter in secure mode;

		mi_sec_mode_kick(1);
		mi_sec_mode_enter(0);
		sread(addr, `CPU_SIZE_4, rdata);
		rd_check(0, orig, 32'hffff_ffff, 0);
	end
endtask

// test access control;

task pi_acc_tests;
	begin
		// test access to data buffers and spare buffers;

		$display("test: %M: data buffers");
		pi_acc_word(8'h01, `PI_BUF0, 1);
		pi_acc_word(8'h01, `PI_BUF1, 1);
		pi_acc_word(8'h01, `PI_SP0, 1);
		pi_acc_word(8'h01, `PI_SP1, 1);

		// test access to flash controller;

		$display("test: %M: flash");
		pi_acc_word(8'h02, `PI_FLASH_CONF, 0);
		pi_acc_word(8'h02, `PI_FLASH_CTRL, 0);

		// test access to atb hardware;

		$display("test: %M: atb");
		pi_acc_word(8'h04, `PI_ATBU, 0);
		pi_acc_word(8'h04, `PI_BUF_ATB, 1);
		pi_acc_word(8'h04, `PI_BUF_ATBU, 0);

		// test access to aes hardware;

		$display("test: %M: aes");
		pi_acc_word(8'h08, `PI_AES_CTRL, 0);
		pi_acc_word(8'h08, `PI_AES_INIT, 1);
		pi_acc_word(8'h08, `PI_AES_EKEY, 1);

		// test access to buffer dma registers;

		$display("test: %M: buffer dma");
		pi_acc_word(8'h10, `PI_DMA_BREAD, 0);
		pi_acc_word(8'h10, `PI_DMA_BWRITE, 0);

		// test access to gpio register;

		$display("test: %M: gpio");
		pi_acc_word(8'h20, `PI_GPIO, 0);

		// test access to ide hardware;

		$display("test: %M: ide"); // XXX

		// test access to error registers;

		$display("test: %M: error register");
		pi_acc_word(8'h80, `PI_ERROR, 0);
	end
endtask

// test pi dma;

task pi_dma;
	input [31:0] mem_addr;	// memory address;
	input [31:0] dev_addr;	// device address;
	input [31:0] dma_reg;	// read/write dma register to use;
	input [31:0] size;		// dma size;
	input [31:0] to;		// dma timeout in usec;
	reg [31:0] status;		// dma status;
	reg [31:0] pierr;		// pi error register;
	reg trap;				// expect dma trap;
	reg [63:0] t0, t;		// timeouts;
	reg [31:0] mi_addr;		// mi address;
	reg [1:0] mi_size;		// mi request size;
	reg [31:0] mi_mem;		// available memory;
	reg [31:0] mi_space;	// mi request space;
	integer nclks;			// sysclks per usec;
	begin
		// check that status register is as expected;

		$display("test: %M: mem 0x%h, dev 0x%h, reg 0x%h, size %0d, to %0dus",
			mem_addr, dev_addr, dma_reg, size, to);
		sread(`PI_STATUS, `CPU_SIZE_4, status);
		if(status[0] !== 1'b0)
			$display("ERROR: %t: %M: dma %b not idle", $time, status[0]);
		if(status[1] !== 1'b0)
			$display("ERROR: %t: %M: io %b not idle", $time, status[1]);
		if(status[2] !== 1'b0)
			$display("ERROR: %t: %M: err %b not cleared", $time, status[2]);
		if(status[3] !== 0)
			$display("ERROR: %t: %M: intr %b before dma", $time, status[3]);

		// make sure error register is clean;

		swrite(`PI_ERROR, `CPU_SIZE_4, 32'd0);

		// start dma;

		swrite(`PI_DRAM_ADDR, `CPU_SIZE_4, mem_addr);
		swrite(`PI_DEV_ADDR, `CPU_SIZE_4, dev_addr);
		swrite(dma_reg, `CPU_SIZE_4, size - 1);

		// XXX conflict;

		// check that dma is busy;
		// zero size dma completes immediatedly with 4'b1000;

		sread(`PI_STATUS, `CPU_SIZE_4, status);
		if((size === 0) & (status[3] === 1'b1) & (status[0] === 1'b0))
			$display("%t: %M: zero size dma complete", $time);
		else if((to !== 0) & (status[0] !== 1))
			$display("ERROR: %t: %M: dma not started", $time);

		// for PI_DMA_READ, the dma trap error should be set;
		// handle trap by reseting dma;
		// completion interrupt is triggered by 0-size dma;

		sread(`PI_ERROR, `CPU_SIZE_4, pierr);
		trap = (dma_reg == `PI_DMA_READ);
		if(trap !== pierr[4])
			$display("ERROR: %t: %M: dma trap %b exp %b", $time, pierr[4], trap);
		if(trap) begin
			$display("%t: %M: handling dma write trap", $time);
			pierr[4] = 0;
			swrite(`PI_ERROR, `CPU_SIZE_4, pierr);
			swrite(`PI_STATUS, `CPU_SIZE_4, 1);
			swrite(`PI_DMA_WRITE, `CPU_SIZE_4, 32'hffff_ffff);
			sread(`PI_STATUS, `CPU_SIZE_4, status);
		end

		// spin until done or timeout;
		// issue mi block reads to stress ri and mi;

		t0 = $time;
		t = 0;
		to = to * 1000;
		while( !trap & (t < to) & (status[0] !== 0)) begin
			mi_addr = $random;
			mi_size = mi_addr[31]? `CPU_SIZE_16 : `CPU_SIZE_32;
			case(mi_addr[1:0])
				2'b00: { mi_mem, mi_space } = { vsim.MEM_SIZE, `BASE_DRAM64L };
				2'b01: { mi_mem, mi_space } = { vsim.MEM_SIZE, `BASE_DRAM64H };
				default: { mi_mem, mi_space } = { vsim.MEM_SIZE / 2, `BASE_DRAM36 };
			endcase
			mi_addr = mi_space + (mi_addr & (mi_mem - 1));
			mi_addr[1:0] = 2'd0;
			bread(mi_addr, mi_size);

			sread(`PI_STATUS, `CPU_SIZE_4, status);
			t = $time - t0;
		end
		if(status[0] !== 0)
			$display("ERROR: %t: %M: dma not done: 0x%h", $time, status);

		// check that dma interrupt is set;

		if(status[3] !== 1)
			$display("ERROR: %t: %M: status intr %b, not 1", $time, status[3]);
		if(vsim.bb.bcp.pi_intr !== 1)
			$display("ERROR: %t: %M: intr %b, not 1", $time, vsim.bb.bcp.pi_intr);

		// check for fatal dma errors;

		sread(`PI_ERROR, `CPU_SIZE_4, pierr);
		if(pierr[5] !== 0)
			$display("ERROR: %t: %M: unexpecetd module removal, %b", $time, pierr[5]);
		if(pierr[4] !== 0)
			$display("ERROR: %t: %M: unexpecetd trap, %b", $time, pierr[4]);
		if(pierr[2] !== 0)
			$display("ERROR: %t: %M: unexpected dbe ecc error, %b", $time, pierr[2]);
		if(pierr[1:0] !== 2'b00)
			$display("ERROR: %t: %M: unexpected atb errors, %b", $time, pierr[1:0]);

		// test clearing of pi interrupt;

		swrite(`PI_STATUS, `CPU_SIZE_4, 32'h2);
		sread(`PI_STATUS, `CPU_SIZE_4, status);
		if(status[3] !== 0)
			$display("ERROR: %t: %M: status intr %b, not 0", $time, status[3]);
		if(vsim.bb.bcp.pi_intr !== 0)
			$display("ERROR: %t: %M: intr %b, not 0", $time, vsim.bb.bcp.pi_intr);

		// kill any dma still in progress;
		// test clearing of dma error bit;

		swrite(`PI_STATUS, `CPU_SIZE_4, 32'h1);
		sread(`PI_STATUS, `CPU_SIZE_4, status);
		if(status[0] !== 0)
			$display("ERROR: %t: %M: dma busy %b after kill", $time, status[0]);
		if(status[2] !== 0)
			$display("ERROR: %t: %M: dma err %b after kill", $time, status[2]);
	end
endtask

// atb setup for dma tests;
// dma tests require a special flash init file;
// atb is setup the following way;
// the flash file is filled with 32-bit words;
// bits[31:25] are random;
// bits[24:2] is the byte address;
// bits[1:0] are random;
// call pi_make_dma_atb_file to generate the atb setup file;
//
//	19	size 16k,  dev 1, off     8M+4M+2M+1M+512k+256k+128k+64k+32k;
//	18	size 16k,  dev 2, off 16M+8M+4M+2M+1M+512k+256k+128k+64k+32k;
//	17	size 32k,  dev 1, off     8M+4M+2M+1M+512k+256k+128k+64k;
//	16	size 32k,  dev 2, off 16M+8M+4M+2M+1M+512k+256k+128k+64k;
//	15	size 64k,  dev 1, off     8M+4M+2M+1M+512k+256k+128k;
//	14	size 64k,  dev 2, off 16M+8M+4M+2M+1M+512k+256k+128k;
//	13	size 128k, dev 1, off     8M+4M+2M+1M+512k+256k;
//	12	size 128k, dev 2, off 16M+8M+4M+2M+1M+512k+256k;
//	11	size 256k, dev 1, off     8M+4M+2M+1M+512k;
//	10	size 256k, dev 2, off 16M+8M+4M+2M+1M+512k;
//	9	size 512k, dev 1, off     8M+4M+2M+1M;
//	8	size 512k, dev 2, off 16M+8M+4M+2M+1M;
//	7	size 1M,   dev 1, off     8M+4M+2M;
//	6	size 1M,   dev 2, off 16M+8M+4M+2M;
//	5	size 2M,   dev 1, off     8M+4M;
//	4	size 2M,   dev 2, off 16M+8M+4M;
//	3	size 4M,   dev 1, off     8M;
//	2	size 4M,   dev 2, off 16M+8M;
//	1	size 8M,   dev 1, off 0;
//	0	size 8M,   dev 2, off 16M;

reg [40:0] pi_dma_atb [0:191];		// dma atb;

task pi_make_dma_atb_file;
	reg [31:0] vaddr;		// virtual address;
	reg [31:0] p1addr;		// dev 1 physical address;
	reg [31:0] p2addr;		// dev 2 physical address;
	reg [3:0] bsize;		// size of block;
	reg [40:0] atb;			// atb bits;
	integer size;			// virtual size;
	integer n;
	begin
		// setup 20 atb entries to match file;

		$display("%t: %M", $time);
		vaddr = 0;
		p1addr = 0;
		p2addr = 16 << 20;
		bsize = 9;
		atb[40:36] = { 1'b1, 2'b00, 2'b01 };
		for(n = 0; n < 20; n = n + 2) begin
			atb[35:32] = bsize;
			size = (16 * 1024) << bsize;
			atb[39:38] = 2;					// dev 2 entry;
			atb[31:16] = p2addr[29:14];
			atb[15:0] = vaddr[29:14];
			pi_dma_atb[n + 0] = atb;
			vaddr = vaddr + size;
			p2addr = p2addr + size;
			atb[39:38] = 1;					// dev 1 entry;
			atb[31:16] = p1addr[29:14];
			atb[15:0] = vaddr[29:14];
			vaddr = vaddr + size;
			p1addr = p1addr + size;
			pi_dma_atb[n + 1] = atb;
			bsize = bsize - 1;
		end

		// fill remaining atb entries;
		// write out file;

		atb[40:32] = { 1'b0, 2'b00, 2'b00, 4'b0000 };
		while(n < `PI_N_ATB) begin
			atb[31:16] = 0;
			atb[15:0] = vaddr[29:14];
			pi_dma_atb[n] = atb;
			n = n + 1;
		end
		$writememb("tests/pi_atb.dat", pi_dma_atb);
	end
endtask

// setup atb and aes for dma tests;

task pi_dma_setup;
	input [7:0] off;		// virtual address offset;
	reg [31:0] addr;		// atb buffer address;
	reg [31:0] ctrl;		// controller state;
	reg [40:0] atb;			// atb bits;
	integer n;
	begin
		// read atb from file;
		// setup iv entry, first or last depending on off;

		$display("%t: %M offset 0x%h", $time, off);
		$readmemb("tests/pi_atb.dat", pi_dma_atb);
		atb = { 1'b1, 2'd0, 2'b11, 4'd0, 16'd0, 16'hffff };
		n = (off == 8'h00)? `PI_N_ATB - 1 : 0;
		pi_dma_atb[n] = atb;

		// write atb to pi buffer;

		addr = `PI_BUF_ATB;
		for(n = 0; n < `PI_N_ATB; n = n + 1) begin
			atb = pi_dma_atb[n];
			swrite(`PI_ATBU, `CPU_SIZE_4, atb[40:32]);
			atb[15:10] = atb[15:10] + off[5:0];
			swrite(addr, `CPU_SIZE_4, atb[31:0]);
			addr = addr + 4;
		end

		// load init vector from file to pi buffer;
		// load expanded key from file to pi buffer;

		$readmemh("tests/pi_init.dat", aes_init);
		$readmemh("tests/pi_ekey.dat", aes_ekey);
		pi_aes_load_iv;
		pi_aes_load_ekey;

		// setup flash controller state;

		ctrl[31] = 0;			// no start;
		ctrl[30] = 0;			// intr off;
		ctrl[29] = 0;			// no write data phase;
		ctrl[28] = 1;			// read data phase;
		ctrl[27:24] = 4'b1111;	// max # of address phases; XXX
		ctrl[23:16] = 8'h00;	// read command;
		ctrl[15] = 1;			// require ready;
		ctrl[14] = 0;			// buf 0;
		ctrl[13:12] = 2'd0;		// device 0;
		ctrl[11] = 1;			// use ecc;
		ctrl[10] = 0;			// not a multi-cycle command;
		ctrl[9:0] = {10{1'b1}};	// max size;
		swrite(`PI_FLASH_CTRL, `CPU_SIZE_4, ctrl);

		// setup aes controller state;
		// da, ia, hc and size do not matter;

		ctrl[31] = 0;			// no start;
		ctrl[30] = 0;			// intr off;
		ctrl[21:16] = $random;	// size;
		ctrl[15:9] = $random;	// da 0;
		ctrl[7:1] = $random;	// ia 0;
		ctrl[0] = $random;		// hc 0;
		swrite(`PI_AES_CTRL, `CPU_SIZE_4, ctrl);
	end
endtask

// fill dma pattern with randoms;

task pi_dma_pat_rand;
	integer n;
	begin
		$display("%t: %M", $time);
		for(n = 0; n < 256; n = n + 1)
			pi_dma_pat[n] = $random;
	end
endtask

// copy dma pattern to memory or pi buffer;
// addr is forced to 32-bit alignment;
// pattern will wrap in pi buffer;

task pi_dma_pat_fill;
	input [31:0] addr;		// memory/buffer address;
	input inv;				// invert pattern;
	reg in_pibuf;			// dst is pi buffer;
	reg [31:0] pat;			// pattern;
	integer n;
	begin
		$display("%t: %M: addr 0x%x, inv %b", $time, addr, inv);
		addr[1:0] = 0;
		in_pibuf = (addr[31:16] == (`PI_BUF >> 16));
		for(n = 0; n < 256; n = n + 1) begin
			pat = {32{inv}} ^ pi_dma_pat[n];
			if(in_pibuf) begin
				addr[15:10] = 6'd0;
				swrite(addr, `CPU_SIZE_4, pat);
			end else
				mem_swrite(addr, `CPU_SIZE_4, pat);
			addr = addr + 4;
		end
	end
endtask

// compare pattern in pi buffer or memory;
// comparison is done on 16-bit values;
// type[1:0]
//	00 check dma_pat;
//	01 check ~dma_pat;
//	1x check flash file pattern;

task pi_dma_pat_cmp;
	input [31:0] mem_addr;	// memory address;
	input [31:0] dev_addr;	// device address;
	input [9:0] first;		// first byte in dma block;
	input [9:0] last;		// last byte in dma block;
	input [1:0] type;		// compare type;
	reg in_pibuf;			// dst is pi buffer;
	reg [31:0] rdata;		// read data;
	reg [31:0] pmask;		// pattern mask;
	reg [31:0] exp;			// expected data;
	reg [31:0] pat;			// pattern data;
	reg [31:0] flpat;		// flash pattern;
	reg within;				// within dma boundaries;
	integer n;
	integer idx;
	begin
		$display("%t: %M: mem 0x%h, dev 0x%h, %0d...%0d, type %0d",
			$time, mem_addr, dev_addr, first, last, type);
		in_pibuf = (mem_addr[31:16] == (`PI_BUF >> 16));
		mem_addr[1:0] = 2'd0;
		if(first > last)
			$display("ERROR: %t: %M: first %0d, last %0d", $time, first, last);
		within = 0;
		for(n = 0; n < 256; n = n + 1) begin
			if(in_pibuf) begin
				mem_addr[15:10] = 6'd0;
				sread(mem_addr, `CPU_SIZE_4, rdata);
			end else
				mem_sread(mem_addr, `CPU_SIZE_4, rdata);
			pmask = {32{within}};
			if(n == first[9:2]) begin
				pmask = 32'hffff_ffff >> (8 * first[1:0]);
				within = 1;
			end
			flpat = dev_addr >> 2;
			idx = dev_addr[9:2];
			if(within)
				dev_addr = dev_addr + 4;
			if(n == last[9:2]) begin
				pmask = pmask & (32'hffff_ffff << (8 * (3 - last[1:0])));
				within = 0;
			end
			if(type == 0) begin
				exp = pi_dma_pat[n];
				pat = pi_dma_pat[idx];
			end else if(type == 1) begin
				exp = pi_dma_pat[n];
				pat = ~pi_dma_pat[idx];
			end else begin
				exp = pi_dma_pat[n];
				flpat[31:24] = flpat[23:16] + flpat[15:8] + flpat[7:0];
				if(dev_addr[1]) begin
					pat = dev_addr >> 2;
					pat[31:24] = pat[23:16] + pat[15:8] + pat[7:0];
					flpat[31:16] = flpat[15:0];
					flpat[15:0] = pat[31:16];
				end
				pat = flpat;
			end
			exp = (exp & ~pmask) | (pat & pmask);
			if(rdata !== exp) begin
				$display("ERROR: %t: %M: addr 0x%h, data 0x%h exp 0x%h",
					$time, mem_addr, rdata, exp);
			end
			mem_addr = mem_addr + 4;
		end
	end
endtask

// unaligned dma compare;

task pi_dma_una_cmp;
	input [31:0] mem_addr;	// memory address;
	input [2:0] mem;		// memory alignment;
	input [2:0] dev;		// device alignment;
	input [7:0] size;		// dma size;
	reg [0:127] pat;		// aligned device pattern;
	reg [31:0] rdata;		// read data;
	integer n;
	begin
		mem[0] = 0;
		dev[0] = 0;
		$display("%t: %M: unaligned cmp, mem %0d, dev %0d, size %0d",
			$time, mem, dev, size);
		pat[0:31] = pi_dma_pat[0];
		pat[32:63] = pi_dma_pat[1];
		pat[64:95] = pi_dma_pat[2];
		pat[96:127] = pi_dma_pat[3];
		n = mem - dev;
		if(n > 0)
			pat = pat >> (n * 8);
		else if(n < 0)
			pat = pat << (n * -8);
		pat = pat & ({128{1'b1}} >> (8 * mem));
		n = 16 - (mem + size);
		pat = pat & ({128{1'b1}} << (8 * n));

		for(n = 0; n < 4; n = n + 1) begin
			mem_sread(mem_addr, `CPU_SIZE_4, rdata);
			if(rdata !== pat[0:31]) begin
				$display("ERROR: %t: %M: addr 0x%h, data 0x%h exp 0x%h",
					$time, mem_addr, rdata, pat[0:31]);
			end
			mem_addr = mem_addr + 4;
			pat = pat << 32;
		end
	end
endtask

// test pi buffer dma;
// buffer dma and traditional dma use the same hardware;
// walk address bits with buffer dma, because it is faster;

task pi_bdma_tests;
	input [7:0] space;		// memory space;
	input [5:0] nabits;		// # of address bits;
	reg [31:0] mem_addr;	// memory address;
	reg [31:0] dev_addr;	// device address;
	reg [23:0] dma_size;	// dma size;
	reg [23:0] dma_nb;		// # of dma bytes;
	integer first;			// first byte offset;
	integer last;			// last byte offset;
	integer n, m;
	begin
		$display("test: %M: space 0x%h, nabits %0d", space, nabits);

		// test dma sizes of 0;
		// setup pattern in memory and inverted pattern in pi buffer;
		// dma to pi buffer should not modify pi buffer data;

		$display("test: %M: bread dma, size 0");
		dma_size = 0;
		pi_dma_pat_rand;
		pi_dma_pat_fill(`PI_BUF, 1);
		pi_dma($random, $random, `PI_DMA_BREAD, dma_size, 2);
		pi_dma_pat_cmp(`PI_BUF, 0, 0, 1023, 1);

		// dma to memory should not modify memory data;

		$display("test: %M: bwrite dma, size 0");
		mem_addr = 0;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, $random, `PI_DMA_BWRITE, dma_size, 2);
		pi_dma_pat_cmp(mem_addr, 0, 0, 1023, 0);

		// test dma from pi buffer to memory;
		// dma a total of 1kB, both data buffers;
		// dma to memory can be 2-byte aligned;

		$display("test: %M: bwrite dma, size 1024");
		mem_addr = 0;
		dev_addr = 0;
		dma_size = 1024;
		pi_dma(mem_addr, dev_addr, `PI_DMA_BWRITE, dma_size, 5);
		pi_dma_pat_cmp(mem_addr, dev_addr, 0, dma_size - 1, 1);

		// test dma from memory to pi buffer;
		// dma a total of 1kB, both data buffers;
		// dma to pi buffer must be 8-byte aligned;

		$display("test: %M: bread dma, size 1024");
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_BREAD, dma_size, 5);
		pi_dma_pat_cmp(`PI_BUF, dev_addr, 0, dma_size - 1, 0);

		// test partial dma mem->pibuf;
		// walk dma memory address bits;
		// randomize dma size within 1kB block;
		// mem->pibuf must be 8-byte aligned;

		$display("test: %M: bread dma, mem_addr walking 1");
		for(n = 3; n < nabits; n = n + 1) begin
			mem_addr = { space, 24'd0 } + (1 << n);
			dev_addr = (1 << n) & 'h3f8;
			dma_size = ($random & 'h3f8) + 8;
			while((dma_size + dev_addr) > 1024)
				dma_size = ($random & 'h3f8) + 8;
			pi_dma_pat_rand;
			pi_dma_pat_fill(`PI_BUF, 0);
			pi_dma_pat_fill(mem_addr & 32'hffff_fc00, 1);
			pi_dma(mem_addr, dev_addr, `PI_DMA_BREAD, dma_size, 5);
			first = dev_addr;
			last = first + dma_size - 1;
			pi_dma_pat_cmp(`PI_BUF, dev_addr, first, last, 1);
		end

		// test partial dma pibuf->mem;
		// walk dma size bits;
		// randomize dev address within 1kB block;

		$display("test: %M: bwrite dma, dma_size walking 1");
		for(n = 1; n <= 16; n = n + 1) begin
			dma_size = n;
			mem_addr = rand_mem_addr(space, 1024, 2);
			mem_addr[5] = 0;
			dev_addr = mem_addr;
			pi_dma_pat_rand;
			pi_dma_pat_fill(`PI_BUF, 1);
			pi_dma_pat_fill(mem_addr & 32'hffff_fc00, 0);
			pi_dma(mem_addr, dev_addr, `PI_DMA_BWRITE, dma_size, 5);
			first = mem_addr;
			last = first + dma_size - 1;
			pi_dma_pat_cmp(mem_addr & 32'hffff_fc00, dev_addr, first, last, 1);
		end

		// test 4 source x 4 dst x 8 size combinations;
		// zero memory before each test;

		$display("test: %M: bwrite dma, unaligned, sizes 1...8");
		for(dma_size = 1; dma_size <= 8; dma_size = dma_size + 1) begin
			for(m = 0; m < 8; m = m + 2) begin
				for(dev_addr = 0; dev_addr < 8; dev_addr = dev_addr + 2) begin
					mem_addr = rand_mem_addr(space, 16, 16);
					mem_swrite(mem_addr + 0, `CPU_SIZE_4, 32'd0);
					mem_swrite(mem_addr + 4, `CPU_SIZE_4, 32'd0);
					mem_swrite(mem_addr + 8, `CPU_SIZE_4, 32'd0);
					mem_swrite(mem_addr + 12, `CPU_SIZE_4, 32'd0);
					pi_dma_pat[0] = $random;
					pi_dma_pat[1] = $random;
					pi_dma_pat[2] = $random;
					pi_dma_pat[3] = $random;
					swrite(`PI_BUF + 0, `CPU_SIZE_4, pi_dma_pat[0]);
					swrite(`PI_BUF + 4, `CPU_SIZE_4, pi_dma_pat[1]);
					swrite(`PI_BUF + 8, `CPU_SIZE_4, pi_dma_pat[2]);
					swrite(`PI_BUF + 12, `CPU_SIZE_4, pi_dma_pat[3]);
					pi_dma(mem_addr + m, dev_addr, `PI_DMA_BWRITE, dma_size, 5);
					pi_dma_una_cmp(mem_addr, m, dev_addr, dma_size);
				end
			end
		end

		// test 8 source x 8 dst with size > dma burst of 128;
		// tests burst boundary crossing;

		$display("test: %M: bwrite dma, unaligned, > burst size");
		for(m = 0; m < 32; m = m + 4) begin
			for(dev_addr = 0; dev_addr < 32; dev_addr = dev_addr + 4) begin
				dma_size = 128 + ($random & 32'h00ff);
				mem_addr = rand_mem_addr(space, 512, 512); // 512/16
				pi_dma_pat_rand;
				pi_dma_pat_fill(`PI_BUF, 1);
				pi_dma_pat_fill(mem_addr & 32'hffff_fc00, 0);
				pi_dma(mem_addr + m, dev_addr, `PI_DMA_BWRITE, dma_size, 5);
				first = mem_addr + m;
				last = first + dma_size - 1;
				pi_dma_pat_cmp(mem_addr & 32'hffff_fc00, dev_addr, first, last, 1);
			end
		end
	end
endtask

// test dma involving flash and atb;

task pi_dma_tests;
	input [7:0] space;		// memory space;
	input [5:0] nabits;		// # of address bits;
	reg [31:0] mem_addr;	// memory address;
	reg [31:0] dev_addr;	// device address;
	reg [23:0] dma_size;	// dma size;
	integer n;
	integer first;			// first byte offset;
	integer last;			// last byte offset;
	begin
		// setup fastest timing config;
		// setup atb for flash test file;

		$display("test: %M: space 0x%h, nabits %0d", space, nabits);
		pi_dma_setup(8'h00);

		// test dma sizes of 0;
		// setup pattern in memory;
		// dma of size 0 to memory should not modify data;

		$display("test: %M: write dma size 0");
		pi_dma_pat_rand;
		mem_addr = rand_mem_addr(space, 1024, 1024);
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, $random, `PI_DMA_WRITE, 0, 0);
		pi_dma_pat_cmp(mem_addr, 0, 0, 1023, 0);

		// test dma from dev_addr 0 for iv reference;
		// dma exactly one flash page;
		// exactly one flash page is read;

		$display("test: %M: write dma iv buf");
		mem_addr = 0;
		dev_addr = 0;
		dma_size = 512;
		pi_dma_pat_rand;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 80);
		pi_dma_pat_cmp(mem_addr, dev_addr, 0, 511, 2);

		// test dma where iv is last in flash page;
		// first page read should not trigger the aes;
		// exactly two flash pages are read;

		$display("test: %M: write dma iv last");
		mem_addr = 0;
		dev_addr = 512;
		dma_size = 512;
		pi_dma_pat_rand;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 2 * 80);
		pi_dma_pat_cmp(mem_addr, dev_addr, 0, 511, 2);

		// test dma length versus aes count;
		// end case of dma;

		$display("test: %M: write dma len/cnt");
		mem_addr = 'h40;
		dev_addr = 'hb4ae58;
		dma_size = 'd836;
		pi_dma_pat_rand;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 3 * 80);
		first = mem_addr[1:0];
		last = first + dma_size - 1;
		pi_dma_pat_cmp(mem_addr, dev_addr, first, last, 2);

		// test right shift dma;

		$display("test: %M: write dma shift right");
		mem_addr = 'h4;
		dev_addr = 'h9690a0;
		dma_size = 'd379;
		pi_dma_pat_rand;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 2 * 80);
		first = mem_addr[1:0];
		last = first + dma_size - 1;
		pi_dma_pat_cmp(mem_addr, dev_addr, first, last, 2);

		// test left shift dma;

		$display("test: %M: write dma shift left");
		mem_addr = 'h8;
		dev_addr = 'h9690a4;
		dma_size = 'd379;
		pi_dma_pat_rand;
		pi_dma_pat_fill(mem_addr, 0);
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 2 * 80);
		first = mem_addr[1:0];
		last = first + dma_size - 1;
		pi_dma_pat_cmp(mem_addr, dev_addr, first, last, 2);

		// walk dma memory address bits;
		// randomize dma size within 1kB block;
		// limit dev_addr and align to 16-bit words;
		// pick random dma sizes;
		// up to three flash pages are read;

		$display("test: %M: write dma walking dma address");
		for(n = 2; n < nabits; n = n + 1) begin
			mem_addr = { space, 24'd0 } + (1 << n);
			dev_addr = pi_dev_addr(1024, 4);
			dma_size = ($random & 'h3ff) + 1;
			pi_dma_pat_rand;
			pi_dma_pat_fill(mem_addr, 0);
			pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 3 * 80);
			first = mem_addr[1:0];
			last = first + dma_size - 1;
			pi_dma_pat_cmp(mem_addr, dev_addr, first, last, 2);
		end

		// test read dma trap;

		$display("test: %M: read dma trap");
		mem_addr = $random;
		dev_addr = pi_dev_addr(1024, 2);
		dma_size = $random;
		pi_dma(mem_addr, dev_addr, `PI_DMA_READ, dma_size, 0);
	end
endtask

// test pi dma bandwidth;

task pi_dma_bw;
	input [7:0] space;		// memory space;
	input [5:0] nabits;		// # of address bits;
	reg [31:0] mem_addr;	// memory address;
	reg [31:0] dev_addr;	// device address;
	reg [23:0] dma_size;	// dma size;
	reg [63:0] t0, t;		// times;
	integer kbps;			// kB/sec;
	begin
		// aligned test forces one more page to be read for iv;

		$display("test: %M: 16x512, aligned");
		dma_size = 16*512;
		mem_addr = rand_mem_addr(space, dma_size, 512);
		dev_addr = pi_dev_addr(dma_size, 512);
		t0 = $time;
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 17 * 80);
		t = $time - t0;
		kbps = dma_size * 1000 / (t / 1000);
		$display("test: %M: space 0x%h, 16x512, aligned, %0dkB/s", space, kbps);

		// non-aligned test;

		$display("test: %M: 16x512, non-aligned");
		dma_size = 16*512 - 16;
		mem_addr = rand_mem_addr(space, dma_size, 512);
		dev_addr = pi_dev_addr(dma_size, 512) + 16;
		t0 = $time;
		pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 16 * 80);
		t = $time - t0;
		kbps = dma_size * 1000 / (t / 1000);
		$display("test: %M: space 0x%h, 16x512, non-aligned, %0dkB/s", space, kbps);
	end
endtask

// compute expected flash value;

function [31:0] pi_iodata;
	input [31:0] addr;
	begin
		pi_iodata[31:24] = addr[23:16] + addr[15:8] + addr[7:0];
		pi_iodata[23:0] = addr[23:0];
	end
endfunction

// execute single cartrige read;

task pi_io_read;
	input [31:0] iospc;		// io space;
	input [31:0] voff;		// virtual offset;
	input err;				// expect bus error;
	input chkerr;			// check error register;
	reg [31:0] addr;		// address;
	reg [31:0] rdata;		// read data;
	reg [31:0] exp;			// expected data;
	reg [31:0] mask;		// error reg compare mask;
	begin
		$display("test: %M: iospc 0x%h voff 0x%h", iospc, voff);
		addr = iospc + voff;
		sread(addr, `CPU_SIZE_4, rdata);
		if(err == 1'b0) begin
			exp = pi_iodata(voff / 4);
			rd_check(0, exp, 32'hffff_ffff, 0);
			mask = { 2'b11, {22{1'b0}}, 3'h7, 1'b1, 2'b10, 2'b11 };
		end else begin
			berr_check(1);
			mask = { 2'b11, {22{1'b1}}, 3'h7, 1'b1, 2'b10, 2'b11 };
		end

		// check error register;
		// clear recorded erorr;

		if(chkerr) begin
			addr[8:0] = 0;
			addr = addr - 16;
			sread(`PI_ERROR, `CPU_SIZE_4, rdata);
			exp = { 2'b00, addr[29:8], 3'd0, 1'b0, 2'b0x, 1'b0, err };
			rd_check(0, exp, mask, 0);
			if(rdata[4:0] != 0)
				swrite(`PI_ERROR, `CPU_SIZE_4, 32'd0);
		end
	end
endtask

// pi cartrige pio tests;

task pi_io_tests;
	input [31:0] iospc;			// io space;
	input [31:24] mask;			// size of address space;
	reg [31:0] voff;			// virtual offset;
	reg [31:0] ioaddr [0:2];	// unmapped regions;
	reg err;					// expect error;
	integer n, nrd;
	begin
		$display("test: %M: io space 0x%h, setup", iospc);
		pi_dma_setup(iospc[31:24]);
		swrite(`PI_ERROR, `CPU_SIZE_4, 32'd0);

		// read at start of atb region to test iv atb entry;
		// read at offset to test atb and aes chaining;
		// always check error register;

		$display("test: %M: io space 0x%h, reads", iospc);
		pi_io_read(iospc, 0, 0, 1);			// pi buffer 0;
		pi_io_read(iospc, 512, 0, 1);		// pi buffer 1;
		pi_io_read(iospc, 1024, 0, 1);		// back to buffer 0;
		pi_io_read(iospc, 16*1024, 0, 1);	// new atb;

		// pick random block and read all words;
		// the block is cached, ie. only one flash read;
		// check error reg only if error to not invalidate pio cache;

		voff[31:9] = $random;
		voff[31:24] = voff[31:24] & mask;
		voff[8:0] = 0;
		err = (voff[31:25] !== 0);
		nrd = err? 1 : 512;
		for(n = 0; n < nrd; n = n + 4)
			pi_io_read(iospc, voff + n, err, err);

		// test that other regions return error;

		$display("test: %M: io space 0x%h, errors", iospc);
		case(iospc)
			`BASE_IO05: begin
				ioaddr[0] = 0;				// can't test, atb maps 32MB;
				ioaddr[1] = `BASE_IO08;
				ioaddr[2] = `BASE_IO10;
			end
			`BASE_IO06: begin
				ioaddr[0] = `BASE_IO05;
				ioaddr[1] = `BASE_IO08;
				ioaddr[2] = `BASE_IO10;
			end
			`BASE_IO08: begin
				ioaddr[0] = `BASE_IO05;
				ioaddr[1] = `BASE_IO06;
				ioaddr[2] = `BASE_IO10;
			end
			`BASE_IO10: begin
				ioaddr[0] = `BASE_IO05;
				ioaddr[1] = `BASE_IO06;
				ioaddr[2] = `BASE_IO08;
			end
			default: begin
				ioaddr[0] = 0;
				ioaddr[1] = 0;
				ioaddr[2] = 0;
				$display("ERROR: %t: %M: bad iospc 0x%h", $time, iospc);
			end
		endcase
		for(n = 0; n < 3; n = n + 1) begin
			if(ioaddr[n]) begin
				voff[31:24] = 0;
				voff[23:9] = $random;
				pi_io_read(ioaddr[n], voff, 1, 1);
			end
		end
	end
endtask


// test pi error handling;

task pi_error_tests;
	begin
		$display("test: %M: XXX");
	end
endtask

// test ide controller;

task pi_ide_tests;
	reg [31:0] rdata;		// read data;
	begin
		$display("test: %M: XXX");

		sread(`PI_IDE_CONF, `CPU_SIZE_4, rdata);
		rdata[31] = 0;
		swrite(`PI_IDE_CONF, `CPU_SIZE_4, rdata);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		swrite(`PI_DUMP, `CPU_SIZE_2, 0);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_DUMP, `CPU_SIZE_2, 1);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		swrite(`PI_PRINTF, `CPU_SIZE_2, 32'h0040_xxxx);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		swrite(`PI_PRINTF, `CPU_SIZE_2, 32'h0041_xxxx);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		swrite(`PI_PRINTF, `CPU_SIZE_2, 32'h0042_xxxx);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		swrite(`PI_PRINTF, `CPU_SIZE_2, 32'h000a_xxxx);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);

		sread(`PI_PRINTF, `CPU_SIZE_4, rdata);
		sread(`PI_PRINTF + 0, `CPU_SIZE_2, rdata);
		sread(`PI_PRINTF + 2, `CPU_SIZE_2, rdata);

		// md sequencer;

		swrite(`PI_MD_PTR, `CPU_SIZE_4, 0);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_MD_VAL, `CPU_SIZE_4, { 1'b1, 15'd10 });
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_MD_VAL, `CPU_SIZE_4, { 1'b0, 15'd10 });
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_MD_VAL, `CPU_SIZE_4, { 1'b1, 15'd10 });
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_MD_VAL, `CPU_SIZE_4, { 1'b0, 15'd10 });
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		swrite(`PI_MD_TRIG, `CPU_SIZE_4, 0);
		sread(`PI_IDE_FC, `CPU_SIZE_4, rdata);
		sread(`PI_MD_TRIG, `CPU_SIZE_4, rdata);
	end
endtask

// extended dma test for bdma corruption bug;

task pi_dma_bug_test;
	reg [31:0] mem_addr;	// memory address;
	reg [31:0] dev_addr;	// device address;
	reg [23:0] dma_size;	// dma size;
	integer first;			// first byte offset;
	integer last;			// last byte offset;
	integer i;
	begin
		$display("test: %M: chip sim, atb setup");
		pi_dma_setup(8'h00);

		for(i = 0; i < 128; i = i + 1) begin
			$display("test: %M: chip sim, dma test %h", i & 'hff);
			mem_addr = { i[3:0], 4'd0 };
			dev_addr = { i[6:4], 1'b0 };
			dev_addr[23:4] = $random;
			dma_size = 128 + ($random & 'h1ff);
			pi_dma_pat_rand;
			pi_dma_pat_fill(mem_addr, 0);
			pi_dma(mem_addr, dev_addr, `PI_DMA_WRITE, dma_size, 2 * 80);
			first = mem_addr[1:0];
			last = first + dma_size - 1;
			pi_dma_pat_cmp(mem_addr, dev_addr, first, last, 2);
		end
	end
endtask

// run all pi tests sequentially;

task test_pi;
	reg [5:0] nabits;		// # of address bit of dram;
	reg flash_ok;			// required flash devices present;
	integer rspto;			// saved cpu response timeout;
	begin
		nabits = vsim.MEM_NADDR;
		ri_config_ddr($random, $random);
		pi_after_reset;				// test default state after reset;

		// test individual units;

		pi_regs;					// test pi registers;
		pi_buf_pio_tests;			// test pi buffer pio access;
		pi_acc_tests;				// pi reg/buffer access tests;
		pi_access(8'hff);			// full access;
		pi_atb_tests;				// directed atb tests, no cpu involvment;
		pi_aes_cpu;					// test aes operations initiated by cpu;
		pi_flash_cpu;				// test flash operations initiated by cpu;

		// test device processor;
		// requires individual units to work;
		// buffer dma tests do not need flash;

		pi_bdma_tests(8'h00, nabits - 1);	// test pi buffer dma, x36;
		pi_bdma_tests(8'h01, nabits);		// test pi buffer dma, x64;

		// flash dma tests require flash and special file;
		// check that minimum flash requirements are met;

		pi_flash_config(1);
		pi_flash_detect(1);
		flash_ok = (flash_present[2:1] === 2'b11);
		if(flash_present[1] !== 1)
			$display("ERROR: %t: %M: required flash 1 missing", $time);
		if(flash_present[2] !== 1)
			$display("ERROR: %t: %M: required flash 2 missing", $time);
		if(flash_size[1] < 16)
			$display("ERROR: %t: %M: flash 1 smaller than 16MB", $time);
		if(flash_size[2] < 32)
			$display("ERROR: %t: %M: flash 2 smaller than 32MB", $time);

		// only run dma/pio tests when flash is ok;
		// extend cpu response timeout for pio tests;

		if(flash_ok) begin
`ifdef PI_ECC_TEST
`else
			pi_dma_tests(8'h00, nabits - 1);	// test pi dma, x36;
			pi_dma_tests(8'h01, nabits);		// test pi dma, x64;
`endif
  			pi_dma_bug_test;					// test for rev 1 dma corruption;
			pi_dma_bw(8'h00, nabits);			// test pi dma bandwidth;

			rspto = vsim.bb.cpu.rsp_timeout;
			vsim.bb.cpu.rsp_timeout = 80000;
			pi_io_tests(`BASE_IO05, 8'h00);		// test io space 2, 16MB;
			pi_io_tests(`BASE_IO06, 8'h01);		// test io space 1, 32MB;
			pi_io_tests(`BASE_IO08, 8'h07);		// test io space 2, 128MB;
			pi_io_tests(`BASE_IO10, 8'h07);		// test io space 1, 1GB, lower 128MB;
			vsim.bb.cpu.rsp_timeout = rspto;
		end else
			$display("ERROR: %t: %M: dma tests not run", $time);

		pi_error_tests;			// test pi errors, ecc, atb, module presence;
		pi_ide_tests;			// test ide controller;
	end
endtask