// ri_test.v v1 Doug Solomon
// RI ddr initialization
// :set tabstop=4

// ddr memory configuration;
// below list contains specific configs for testing;
// id[3:2] is cas latency, 4, 3, 3, 2;
// id[1:0] configure memory parameters, 9/4/5, 9/4/4, 9/4/3, 9/4/2;

reg [31:0] ri_ddr_mode [0:15];
reg [31:0] ri_ddr_rfsh [0:15];
reg [31:0] ri_ddr_parm [0:15];

initial
begin : ddr_init
	integer n;

	// setup modes for configs;

	for(n = 0; n < 4; n = n + 1)
		ri_ddr_mode[n] = 32'h0000_014a;
	for(n = 4; n < 12; n = n + 1)
		ri_ddr_mode[n] = 32'h0000_013a;
	for(n = 12; n < 16; n = n + 1)
		ri_ddr_mode[n] = 32'h0000_012a;

	// setup refresh;

	for(n = 0; n < 16; n = n + 1)
		ri_ddr_rfsh[n] = 32'h0000_1080;

	// setup memory parameters;

	for(n = 0; n < 4; n = n + 1) begin
		ri_ddr_parm[n + 0] = 32'h0511_1180 - (n * 32'h0100_0000);
		ri_ddr_parm[n + 4] = 32'h0511_1180 - (n * 32'h0100_0000);
		ri_ddr_parm[n + 8] = 32'h0510_0080 - (n * 32'h0100_0000);
		ri_ddr_parm[n + 12] = 32'h0510_0080 - (n * 32'h0100_0000);
	end
end

// configure ddr memory based on configuration id;

task ri_config_ddr;
	input [3:0] id;
	input fast_rfsh;
	reg [31:0] mode;
	reg [31:0] parm;
	reg [31:0] ext;
	reg [31:0] rdata;
	begin
		$display("test: %M: id %0d", id);

		// 1st pre-charge all;

		swrite(`RI_MODE, `CPU_SIZE_4, 32'h8000_0000);
		sread(`RI_MODE, `CPU_SIZE_4, rdata);

		// extended mode register write, enable pll;

		swrite(`RI_MODE, `CPU_SIZE_4, 32'h0000_2002);
		sread(`RI_MODE, `CPU_SIZE_4, rdata);

		// write mode register;
`ifdef TOSHIBA_64MB
		mode = 32'h0000_013a;
`else
		mode = ri_ddr_mode[id];
		mode = 32'h0000_013a;
`endif
		swrite(`RI_MODE, `CPU_SIZE_4, mode);
		sread(`RI_MODE, `CPU_SIZE_4, rdata);

		// 2nd pre-charge all;

		swrite(`RI_MODE, `CPU_SIZE_4, 32'h8000_0000);
		sread(`RI_MODE, `CPU_SIZE_4, rdata);

		// Auto Refesh

		swrite(`RI_MODE, `CPU_SIZE_4, 32'h4000_0000);
		sread(`RI_MODE, `CPU_SIZE_4, rdata);

		// write Tref;
		// if fast_rfsh is on, then force highest rate of refresh;
		// this is supposed to increase bank act/close frequency;
		// XXX implement fast_rfsh;
`ifdef TOSHIBA_64MB
		swrite(`RI_RFSH, `CPU_SIZE_4, 32'h0000_11e0);
`else
		//swrite(`RI_RFSH, `CPU_SIZE_4, ri_ddr_rfsh[id]);
		swrite(`RI_RFSH, `CPU_SIZE_4, 32'h0000_11e0);
`endif

		sread(`RI_RFSH, `CPU_SIZE_4, rdata);

		// set memory parameters;

		parm = ri_ddr_parm[id];
		parm[3:0] = mode[7:4];
`ifdef TOSHIBA_64MB
		swrite(`RI_PARAM, `CPU_SIZE_4, 32'h0311_11e4);
`else
		// swrite(`RI_PARAM, `CPU_SIZE_4, parm);
		swrite(`RI_PARAM, `CPU_SIZE_4, 32'h0310_00c4);
`endif
		sread(`RI_PARAM, `CPU_SIZE_4, rdata);

		// Issue Tref Read

		sread(`RI_RFSH, `CPU_SIZE_4, rdata);
		sread(`RI_RFSH, `CPU_SIZE_4, rdata);

		// setup for x32 or x16 memories;

		ext = vsim.ddr_x16? 1 : 0;
		if (ext == 1) begin
			swrite(`RI_XMEMSET, `CPU_SIZE_4, ext);
		end else begin
			swrite(`RI_STROBE, `CPU_SIZE_4, 1);
			swrite(`RI_AUTO_PRC, `CPU_SIZE_4, 1);
		end

		// Wait at least 200xmemclk from DLL Reset

		repeat(20) @(posedge sysclk);
		$display("test: %M: mode 0x%h, rfsh 0x%h, parm 0x%h, ext 0x%h",
			mode, ri_ddr_rfsh[id], parm, ext);
	end
endtask

// initialize ddr;

task test_ri;
	integer i;
	begin
		// 1st Precharge-All

		swrite(32'h0470_0020, 2'b11, 32'h8000_0000);
		sread(32'h0470_0020, 2'b11, data[0]);

		// extended mode register write, enable pll;

		swrite(32'h0470_0020, 2'b11, 32'h0000_2002);
		sread(32'h0470_0020, 2'b11, data[0]);

		// Mode Register Write
		// Issue Mx Write Reset PLL
		// CAS Latency = 2
		// Interleaved
		// Burst Length = 4

		swrite(32'h0470_0020, 2'b11, 32'h0000_012a);
		sread(32'h0470_0020, 2'b11, data[0]);

		// 2st Precharge-All

		swrite(32'h0470_0020, 2'b11, 32'h8000_0000);
		sread(32'h0470_0020, 2'b11, data[0]);

		// Auto Refesh

		swrite(32'h0470_0020, 2'b11, 32'h4000_0000);
		sread(32'h0470_0020, 2'b11, data[0]);

		//Write Tref

		swrite(32'h0470_0030, 2'b11, 32'h0000_1080);
		sread(32'h0470_0030, 2'b11, data[0]);

		// Issue Tref Read

		sread(32'h0470_0030, 2'b11, data[0]);
		sread(32'h0470_0030, 2'b11, data[0]);

		// Wait at least 200xmemclk from DLL Reset
		repeat(20) @(posedge sysclk);

                for (i=0; i<64; i=i+1)
                    swrite(i<<2, 2'b11, 32'h87564300+(i<<2));

                sread(32'h0000_0020, 2'b11, data[0]);
                sread(32'h0000_0060, 2'b11, data[0]);
                sread(32'h0000_0064, 2'b11, data[0]);
                sread(32'h0000_0068, 2'b11, data[0]);
                sread(32'h0000_0070, 2'b11, data[0]);


	end
endtask