// si_test.v v1 Frank Berndt
// SI cpu initiated tests;
// :set tabstop=4

// state of local controller sticks;

integer si_lctrl_x, si_lctrl_y;

// joychannel data buffers;

reg [7:0] si_jbuf1 [0:35];
reg [7:0] si_jbuf2 [0:35];
reg [7:0] si_jbuf3 [0:35];

// per channel data crc;

reg [7:0] si_jcrc [1:3];
reg [31:0] si_jrsp [1:3];

// return a memory address for si dma;
// si can only issue x36 or x64 L dma addresses;
// XXX page crossing;

task si_mem_addr;
	output [31:0] addr;
	reg spc;
	begin
		addr[31:25] = 0;
		addr[24:0] = $random & (vsim.MEM_SIZE - 1);
		spc = addr[0];
		if(spc == 0)
			addr = addr >> 1;
		else
			addr[31:24] = addr[31:24] + 1;
	end
endtask

// configure button sampling;

task si_but_config;
	input ena;			// enable button sampling;
	input [6:0] rate;	// sampling interval;
	reg [31:0] conf;	// current configuration;
	begin
		$display("test: %M: ena %b, rate %0d", ena, rate);
		sread(`SI_CONFIG, `CPU_SIZE_4, conf);
		conf[22] = ena;
		conf[21:16] = rate;
		swrite(`SI_CONFIG, `CPU_SIZE_4, conf);
		sread(`SI_CONFIG, `CPU_SIZE_4, data[0]);
		rd_check(0, conf, 32'hffffffff, 0);
	end
endtask

// test SI registers after reset;

task si_after_reset;
	reg [31:0] rdata;
	reg [31:0] exp;
	begin
		// read SI_STATUS register;
		// check that the defined bits are correct;

		$display("test: %M: SI_STATUS");
		sread(`SI_STATUS, `CPU_SIZE_4, rdata);
		exp = 32'd0;
		rd_check(0, exp, 32'hffff_ffff, 0);

		// SI_CONFIG and SI_CTRL return the same data;

		exp = { 1'b0, 7'd31,
			1'b1, 1'b0, 6'd2,
			8'h00,
			5'd0, 1'b0, 1'b0, 1'b1 };

		// check SI_CONFIG;

		$display("test: %M: SI_CONFIG");
		sread(`SI_CONFIG, `CPU_SIZE_4, rdata);
		rd_check(0, exp, 32'hffff_ffff, 0);

		// check SI_CTRL register;

		$display("test: %M: SI_CTRL");
		sread(`SI_CTRL, `CPU_SIZE_4, rdata);
		rd_check(0, exp, 32'hffff_ffff, 0);
	end
endtask

// set local controller button bits;

task si_lctrl_xy0;
	inout [31:0] qrsp;
	begin
		if(qrsp[20] & qrsp[16] & qrsp[17]) begin
			qrsp[31] = 1;
			si_lctrl_x = 0;
			si_lctrl_y = 0;
			qrsp[15:8] = 0;
			qrsp[7:0] = 0;
		end
		qrsp[30] = 0;
	end
endtask

// set and test joy channel reset bit in SI_CTRL;

task si_jcrst;
	input jcrst;
	reg [31:0] ctrl;
	begin
		// apply the big hammer;

		$display("test: %M: jcrst %b", jcrst);
		ctrl = { 24'd0, 7'd0, jcrst };
		swrite(`SI_CTRL, `CPU_SIZE_4, ctrl);
		sread(`SI_CTRL, `CPU_SIZE_4, ctrl);
		if(ctrl[0] !== jcrst)
			$display("ERROR: %t: %M: JCRST %b exp %b", $time, ctrl[16], jcrst);

		// reset local controller model;

		vsim.lctrl.lctrl_reset;
		si_lctrl_x = 0;
		si_lctrl_y = 0;
	end
endtask

// setup controller mode;

task si_jctrl_mode;
	input [1:0] ctrl;		// controller;
	input [3:0] mode;		// mode of operation;
	input rsprand;			// response randomization;
	input rspecho;			// cmd echo;
	reg enabled;			// enable/disable controller;
	reg collide;			// test collide;
	reg framerr;			// test frame error;
	reg master;				// set master mode;
	reg [2:0] coll_rand;	// random collision state;
	reg [4:0] fram_rand;	// random frame state;

	// only joy channel controllers can do this;
	// only controller 1 can be master;

	begin
		enabled = mode[0];
		collide = mode[1];
		framerr = mode[2];
		master = mode[3];
		coll_rand = collide? $random() : 3'bxxx;
		fram_rand = framerr? $random() : 5'bxxxxx;

		if(ctrl == 1) begin
			vsim.jctrl1.enable = enabled;
			vsim.jctrl1.master = master;
			vsim.jctrl1.collide = {collide, coll_rand};
			vsim.jctrl1.framerr = {framerr, fram_rand};
			vsim.jctrl1.rsp_random = rsprand;
			vsim.jctrl1.rsp_echo = rspecho;
		end else if(ctrl == 2) begin
			vsim.jctrl2.enable = enabled;
			vsim.jctrl3.master = 0;
			vsim.jctrl2.collide = {collide, coll_rand};
			vsim.jctrl2.framerr = {framerr, fram_rand};
			vsim.jctrl2.rsp_random = rsprand;
			vsim.jctrl2.rsp_echo = rspecho;
		end else  if(ctrl == 3) begin
			vsim.jctrl3.enable = enabled;
			vsim.jctrl3.master = 0;
			vsim.jctrl3.collide = {collide, coll_rand};
			vsim.jctrl3.framerr = {framerr, fram_rand};
			vsim.jctrl3.rsp_random = rsprand;
			vsim.jctrl3.rsp_echo = rspecho;
		end else
			$display("ERROR: %t: %M: no such ctrl%1d", $time, ctrl);
	end
endtask

// compare data bytes;

task si_byte_cmp;
	input [1:0] ctrl;	// controller;
	input [1:0] n;		// byte index;
	input [7:0] a;		// real byte;
	input [7:0] b;		// expected byte;
	begin
		if(a !== b) begin
			$display("ERROR: %t: %M: ctrl %0d byte[%0d] %b exp %b",
				$time, ctrl, n, a, b);
		end
	end
endtask

// setup jchan buffer with expected rx data;

task si_jrx_setup;
	input [1:0] ctrl;		// controller id;
	input [7:0] tx_size;	// transmit size;
	input [7:0] cmd;		// controller command;
	input [31:0] data;		// data bytes;
	reg [31:0] rsp;			// read response;
	reg [7:0] crc;			// crc, really checksum;
	integer n;
	begin
		crc = data[15:8];
		for(n = 1; n < 32; n = n + 1)
			crc = crc + data[7:0];
		rsp = { data[15:8], data[7:0], data[7:0], crc };
		case(ctrl)
			1: begin
				si_jbuf1[0] = cmd;
				si_jbuf1[1] = data[31:24];
				si_jbuf1[2] = data[23:16];
				si_jbuf1[3] = data[15:8];
				for(n = 4; n < tx_size; n = n + 1)
					si_jbuf1[n] = data[7:0];
				si_jrsp[1] = rsp;
				si_jcrc[1] = crc;
			end
			2: begin
				si_jbuf2[0] = cmd;
				si_jbuf2[1] = data[31:24];
				si_jbuf2[2] = data[23:16];
				si_jbuf2[3] = data[15:8];
				for(n = 4; n < tx_size; n = n + 1)
					si_jbuf2[n] = data[7:0];
				si_jrsp[2] = rsp;
				si_jcrc[2] = crc;
			end
			3: begin
				si_jbuf3[0] = cmd;
				si_jbuf3[1] = data[31:24];
				si_jbuf3[2] = data[23:16];
				si_jbuf3[3] = data[15:8];
				for(n = 4; n < tx_size; n = n + 1)
					si_jbuf3[n] = data[7:0];
				si_jrsp[3] = rsp;
				si_jcrc[3] = crc;
			end
		endcase
	end
endtask

// setup jctrl response to read;

task si_jrsp_setup;
	begin
		si_jrsp[1] = { vsim.jctrl1.rdata[0], vsim.jctrl1.rdata[1],
			vsim.jctrl1.rdata[2], vsim.jctrl1.rdata[32] };
		si_jrsp[2] = { vsim.jctrl2.rdata[0], vsim.jctrl2.rdata[1],
			vsim.jctrl2.rdata[2], vsim.jctrl2.rdata[32] };
		si_jrsp[3] = { vsim.jctrl3.rdata[0], vsim.jctrl3.rdata[1],
			vsim.jctrl3.rdata[2], vsim.jctrl3.rdata[32] };
	end
endtask

// compare rx data in jctrl;

task si_jrx_cmp;
	input [1:0] ctrl;	// controller;
	input [5:0] nb;		// # of bytes to compare;
	integer n;
	begin
		$display("%t: %M: ctrl%0d %0d bytes", $time, ctrl, nb);
		case(ctrl)
			1: begin
				for(n = 0; n < nb; n = n + 1)
					si_byte_cmp(ctrl, n, si_jbuf1[n], vsim.jctrl1.rx_data[n]);
			end
			2: begin
				for(n = 0; n < nb; n = n + 1)
					si_byte_cmp(ctrl, n, si_jbuf2[n], vsim.jctrl2.rx_data[n]);
			end
			3: begin
				for(n = 0; n < nb; n = n + 1)
					si_byte_cmp(ctrl, n, si_jbuf3[n], vsim.jctrl3.rx_data[n]);
			end
		endcase
	end
endtask

// force controller and joychannel reset;

task si_ctrl_reset;
	integer nclks;
	begin
		// turn off controllers to avoid error messages;

		$display("test: %M: controller reset");
		si_jctrl_mode(1, `JCTRL_OFF, 0, 0);
		si_jctrl_mode(2, `JCTRL_OFF, 0, 0);
		si_jctrl_mode(3, `JCTRL_OFF, 0, 0);
		si_jcrst(1);

		// wait for reset active time;
		// reset time 100us minimum;

		nclks = 105000000 / vsim.sysclk_gen.period;
		repeat(nclks) @(posedge sysclk);
		si_jcrst(0);
	end
endtask

// check si dma address register;

task si_dma_addr;
	reg [25:0] addr;
	integer n;
	begin
		$display("test: %M");
		for(n = 0; n < 4; n = n + 1) begin
			addr[25:3] = $random;
			addr[2:0] = 'bx;
			swrite(`SI_DRAM_ADDR, `CPU_SIZE_4, addr);
			sread(`SI_DRAM_ADDR, `CPU_SIZE_4, data[0]);
			addr[2:0] = 'b0;
			rd_check(0, addr, 32'hffffffff, 0);
		end
	end
endtask

// check clearance of si dma interrupt;
// any write to status register should reset DMA_ERR and DMA_INT;

task si_clear_status;
	reg [31:0] status;
	begin
		// write to SI_STATUS register;
		// read and check it;

		swrite(`SI_STATUS, `CPU_SIZE_4, 32'hxxxx_xxxx);
		sread(`SI_STATUS, `CPU_SIZE_4, status);
		if((status !== 32'h0000_0000) || (vsim.bb.bcp.si_intr !== 0))
			$display("ERROR: %t: %M: SI_STATUS after clear: 0x%h", $time, status);
	end
endtask

// read and write dma tasks can force a conflict;
// the address of the conflict register is used;

// check read/write dma status;

task si_check_dma;
	input read;
	input [31:0] conflict;
	input rsprand;
	input ctrlrst;
	input mtx;

	reg [31:0] status;	// dma status;
	integer n;
	integer nclks;		// # of sysclks per joychannel byte;
	begin
		// check that dma is busy;

		sread(`SI_STATUS, `CPU_SIZE_4, status);
		if(status[0] !== 1)
			$display("ERROR: %t: %M: si dma not started", $time);

		// check conflict bit;

		if((conflict !== 32'd0) && (status[3] !== 1))
			$display("ERROR: %t: %M: si dma conflict not seen", $time);

		// optionally start master transmit;

		if(mtx)
			si_master_tx;

		// optionally reset controllers;
		// used to test recovery after brutal reset;

		if(ctrlrst)
			si_ctrl_reset;

		// si requests single dma burst;
		// write dma should be done very quickly;
		// read dma has to wait for controllers to finish;
		// minimum jbus time is 64us separator + 32us/byte,
		// however, with rsp_random one byte can take up to 128us;
		// the longest packet is 2 separator, 1 cmd, 35 data;
		// add two more byte times as safeguard;
		// poll dma status every 2usec;
		// spin until done or timeout;

		n = read? (2 + 1 + 35 + 2) : 1;
		if(rsprand)
			n = n * 4;
		n = n * 16;
		while((n >= 0) & (status[0] !== 0)) begin
			if(read) begin
				nclks = 2000000 / vsim.sysclk_gen.period;
				repeat(nclks) @(posedge sysclk);
			end
			sread(`SI_STATUS, `CPU_SIZE_4, status);
			n = n - 1;
		end
		if(status[0] !== 0)
			$display("ERROR: %t: %M: si dma not done: 0x%h", $time, status);

		// check dma completion interrupt;

		if((status[12] !== 1) || (vsim.bb.bcp.si_intr !== 1))
			$display("ERROR: %t: %M: si dma intr not set: 0x%h", $time, status);
	end
endtask

// setup controller command in memory;

task si_mem_setup;
	input [31:0] addr;		// memory base address;
	input [1:0] ctrl;		// controller id;
	input [7:0] tx_size;	// transmit size;
	input [7:0] rx_size;	// receive size;
	input [7:0] cmd;		// controller command;
	reg [31:0] maddr;
	reg [63:0] data;
	integer n;
	begin
		data[63:56] = 1 | $random();	// must not be 0;
		data[55:48] = tx_size;			// tx size;
		data[47:40] = rx_size;			// rx size;
		data[39:32] = cmd;				// command;
		data[31:0] = $random();			// random tx data;
		if(ctrl < 4) begin
			maddr = { addr[31:3], 3'b000 } + (ctrl * 8);
			vsim.mem_swrite(maddr + 0, `CPU_SIZE_4, data[63:32]);
			vsim.mem_swrite(maddr + 4, `CPU_SIZE_4, data[31:0]);
			si_jrx_setup(ctrl, tx_size, cmd, data[31:0]);
		end else
			$display("ERROR: %t: %M: no such ctrl%1d", $time, ctrl);
	end
endtask

// compare memory with controller bits;

task si_ctrl_cmp;
	input [31:0] addr;	// memory address;
	input [1:0] ctrl;	// controller;
	input [7:0] ecode;	// completion code;
	input [7:0] txsize;	// tx size;
	input [7:0] rxsize;	// rx size;
	input [7:0] cmd;	// command;
	input [31:0] exp;	// expected response;
	reg [31:0] maddr;	// memory address;
	reg [31:0] req;		// expected status;
	reg [31:0] status;	// status word;
	reg [31:0] rsp;		// controller response;
	reg [31:0] mask;	// data mask;
	reg [7:0] tmp;		// tmp for button byte swap;
	reg rsperr;			// response error;
	integer nsh;
	begin
		// expected controller status;

		maddr = { addr[31:3], 3'b000 } + (ctrl * 8);
		vsim.mem_sread(maddr + 0, `CPU_SIZE_4, status);
		vsim.mem_sread(maddr + 4, `CPU_SIZE_4, rsp);

		// check command and status;

		rsperr = |ecode[7:3];
		req = { 8'hff, txsize, ecode | rxsize, cmd };
		if(req !== status) begin
			$display("ERROR: %t: %M: ctrl%1d status 0x%h exp 0x%h",
				$time, ctrl, status, req);
		end

		// check controller response;
		// response is undefined for errors;
		// determine compare mask based on command;
		// compare echo response, cmd[1:0] encode response length;

		casex({rsperr,req[7:0]})
			{ 1, 8'hxx } : nsh = 4;
			{ 0, `JCTRL_STATUS }: nsh = 1;
			{ 0, `JCTRL_QUERY }: nsh = 0;
			{ 0, `JCTRL_READ }: nsh = 0;
			{ 0, `JCTRL_WRITE }: nsh = 3;
			{ 0, `JCTRL_RESET }: nsh = 1;
			default: nsh = 3 - req[1:0];
		endcase

		// swap button bytes for issued queries;

		if((txsize != 8'd0) & (req[7:0] == `JCTRL_QUERY)) begin
			tmp = exp[31:24];
			exp[31:24] = exp[23:16];
			exp[23:16] = tmp;
		end

		// compare values;

		mask = 32'hffffffff << (8 * nsh);
		if((rsp & mask) !== (exp & mask)) begin
			$display("ERROR: %t: %M: ctrl%1d response 0x%8h exp 0x%8h mask 0x%8h",
				$time, ctrl, rsp & mask, exp & mask, mask);
		end
	end
endtask

// setup controller buttons/sticks;
// wait until local controller has sampled or move is done;

task si_ctrl_setup;
	input [1:0] ctrl;		// controller;
	input [15:0] button;	// button status;
	input [7:0] x, y;		// stick counts;
	integer lx, ly;			// target locatiob;
	integer dx, dy;			// deltas;
	begin
		if(ctrl === 0) begin
			vsim.lctrl.button = button;
			lx = x - (x[7]? 256 : 0);
			ly = y - (y[7]? 256 : 0);
			dx = lx - si_lctrl_x;
			dy = ly - si_lctrl_y;
			if(dx | dy) begin
				vsim.lctrl.xmove = dx;
				vsim.lctrl.ymove = dy;
				si_lctrl_x = lx;
				si_lctrl_y = ly;
				@(negedge vsim.lctrl.inmotion);
				@(posedge sysclk);
			end
		end else if(ctrl === 1) begin
			vsim.jctrl1.button = button;
			vsim.jctrl1.x = x;
			vsim.jctrl1.y = y;
		end else if(ctrl === 2) begin
			vsim.jctrl2.button = button;
			vsim.jctrl2.x = x;
			vsim.jctrl2.y = y;
		end else  if(ctrl === 3) begin
			vsim.jctrl3.button = button;
			vsim.jctrl3.x = x;
			vsim.jctrl3.y = y;
		end else
			$display("ERROR: %t: %M: no such ctrl%1d", $time, ctrl);
	end
endtask

// setup controller type/status;

task si_ctrl_type;
	input [1:0] ctrl;		// controller;
	input [15:0] type;		// type bits;
	input [7:0] status;		// status bits;

	// only joy channel controllers can do this;

	begin
		if(ctrl == 1) begin
			vsim.jctrl1.type_l = type[15:8];
			vsim.jctrl1.type_h = type[7:0];
			vsim.jctrl1.status = status;
		end else if(ctrl == 2) begin
			vsim.jctrl2.type_l = type[15:8];
			vsim.jctrl2.type_h = type[7:0];
			vsim.jctrl2.status = status;
		end else  if(ctrl == 3) begin
			vsim.jctrl3.type_l = type[15:8];
			vsim.jctrl3.type_h = type[7:0];
			vsim.jctrl3.status = status;
		end else
			$display("ERROR: %t: %M: no such ctrl%1d", $time, ctrl);
	end
endtask

// return a random unsupported controller command;

task si_ctrl_uncmd;
	output [7:0] cmd;
	begin
		cmd = `JCTRL_STATUS;
		while(cmd == `JCTRL_STATUS) begin
			cmd = $random;
			case(cmd)
				`JCTRL_STATUS,
				`JCTRL_QUERY,
				`JCTRL_READ,
				`JCTRL_WRITE,
				`JCTRL_RESET: cmd = `JCTRL_STATUS;
			endcase
		end
	end
endtask

// setup jctrl master transmit;

task si_master_setup;
	input [7:0] tx_size;		// transmit size;
	input [7:0] cmd;			// command;
	input [31:0] tx_data;		// data;
	input [7:0] rsp_size;		// response size;
	integer n;
	begin
		$display("%t: %M: size %0d, cmd 0x%h, data 0x%h",
			$time, tx_size, cmd, tx_data);
		vsim.jctrl1.tx_size = tx_size;
		vsim.jctrl1.tx_data[0] = cmd;
		vsim.jctrl1.tx_data[1] = tx_data[31:24];
		vsim.jctrl1.tx_data[2] = tx_data[23:16];
		vsim.jctrl1.tx_data[3] = tx_data[15:8];
		for(n = 4; n < 35; n = n + 1)
			vsim.jctrl1.tx_data[n] = tx_data[7:0];
		vsim.jctrl1.rx_last = rsp_size;
	end
endtask

// start jctrl master transmit;

task si_master_tx;
	begin
		vsim.jctrl1.tx_on = 1;
	end
endtask

// check received slave command;

task si_slcmd_cmp;
	input [31:0] addr;		// memory address;
	input [7:0] txsize;		// transmit size;
	input [7:0] rxsize;		// receive size;
	input [7:0] cmd;		// command;
	input [31:0] exp;		// data bytes;
	input [7:0] ecode;		// completion code;
	reg [31:0] status;		// status word;
	reg [31:0] rsp;			// controller response;
	reg [31:0] req;			// expected request;
	reg [31:0] mask;		// compare mask;
	reg cmderr;				// error in command;
	begin
		$display("%t: %M: addr 0x%h", $time, addr);
		addr[2:0] = 3'd0;
		vsim.mem_sread(addr + 8, `CPU_SIZE_4, status);
		vsim.mem_sread(addr + 12, `CPU_SIZE_4, rsp);

		// compare cmd/status;

		req = { 8'hff, txsize, ecode | rxsize[2:0], cmd };
		if(req !== status)
			$display("ERROR: %t: %M: status 0x%h exp 0x%h", $time, status, req);

		// compare data;

		cmderr = |ecode;
		if(cmderr)
			rxsize = 0;
		mask = 32'hffffffff;
		if(rxsize < 5)
			mask = mask << (8 * (5 - rxsize));
		if((rsp & mask) !== (exp & mask)) begin
			$display("ERROR: %t: %M: data 0x%8h exp 0x%8h mask 0x%8h",
				$time, rsp & mask, exp & mask, mask);
		end
	end
endtask

// check response in master model;

task si_slrsp_cmp;
	input [7:0] rspsize;	// expected # of bytes;
	input [31:0] exp;		// data bytes;
	reg [7:0] rxsize;		// rx size;
	reg [31:0] rsp;			// controller response;
	reg [31:0] mask;		// compare mask;
	begin
		$display("%t: %M: size %0d", $time, rspsize);
		rxsize = vsim.jctrl1.rx_size - 1;
		if(rspsize != rxsize) begin
			$display("ERROR: %t: %M: response size %0d exp %0d bytes",
				$time, rxsize, rspsize);
		end

		rsp[31:24] = vsim.jctrl1.rx_data[1];
		rsp[23:16] = vsim.jctrl1.rx_data[2];
		rsp[15:8] = vsim.jctrl1.rx_data[3];
		rsp[7:0] = vsim.jctrl1.rx_data[4];
		mask = 32'hffffffff << (8 * (4 - rspsize));
		if((rsp & mask) !== (exp & mask)) begin
			$display("ERROR: %t: %M: data 0x%8h exp 0x%8h mask 0x%8h",
				$time, rsp & mask, exp & mask, mask);
		end
	end
endtask

// test si write dma;
// 32-byte dma dram -> si structures;

task si_write_dma;
	input [31:0] mem_addr;
	input [31:0] conflict;
	begin
		// dram address is random within memory size;
		// si must force 8-byte alignment;
		// optionally, force dma conflict;

		$display("test: %M: conflict 0x%h", conflict);
		swrite(`SI_DRAM_ADDR, `CPU_SIZE_4, mem_addr);
		swrite(`SI_DMA_WRITE, `CPU_SIZE_4, 'bx);
		if(conflict !== 32'd0)
			swrite(conflict, `CPU_SIZE_4, 'bx);

		// check dma start, completion and interrupt;

		si_check_dma(0, conflict, 0, 0, 0);
		si_clear_status;
	end
endtask

// test si read dma;
// triggers controller state machines;
// 32-byte dma dram <- si structures;

task si_read_dma;
	input [31:0] mem_addr;
	input [31:0] conflict;
	input rsprand;
	input ctrlrst;
	input mtx;

	begin
		// dram address is random within memory size;
		// si must force 8-byte alignment;
		// optionally, force dma conflict;

		$display("test: %M: conflict 0x%h", conflict);
		swrite(`SI_DRAM_ADDR, `CPU_SIZE_4, mem_addr);
		swrite(`SI_DMA_READ, `CPU_SIZE_4, 'bx);
		if(conflict !== 32'd0)
			swrite(conflict, `CPU_SIZE_4, 'bx);

		// check dma start, completion and interrupt;

		si_check_dma(1, conflict, rsprand, ctrlrst, mtx);
		si_clear_status;
	end
endtask

// test joychannel error detection;

task si_jc_error;
	reg [31:0] addr;		// memory dma address;
	reg [31:0] val;			// response value;
	reg [31:0] rsp [0:3];	// query responses;
	integer n;
	begin
		// jctrl1 checks no response, ie. turned off;
		// jctrl2 checks collision error;
		// jctrl3 checks frame error;
		// turn on response randomization;

		$display("test: %M: error detection");
		si_jctrl_mode(1, `JCTRL_OFF, 1, 0);
		si_jctrl_mode(2, `JCTRL_COLLIDE, 1, 0);
		si_jctrl_mode(3, `JCTRL_FRAMERR, 1, 0);

		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 1, 4, `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		si_mem_addr(addr);
		si_read_dma(addr, `SI_DMA_READ, 1, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h01234567);
		si_ctrl_cmp(addr, 1, `JRSP_NORSP, 1, 4, `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 2, `JRSP_COLLERR, 1, 4, `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 3, `JRSP_FRAMERR, 1, 4, `JCTRL_QUERY, 32'bx);

		// test recovery after error;
		// jctrl2 and jctrl3 may still be sending data,
		// new transmit has to wait for tS (separator) to expire;
		// even though the read dma has already finished due to error;
		// turn off response randomization;
		// use randoms for buttons, x and y;

		$display("test: %M: error recovery");
		si_jctrl_mode(1, `JCTRL_ON, $random, 0);
		si_jctrl_mode(2, `JCTRL_ON, $random, 0);
		si_jctrl_mode(3, `JCTRL_ON, $random, 0);
		for(n = 0; n < 4; n = n + 1) begin
			val = $random;
			if(n == 0)
				si_lctrl_xy0(val);
			rsp[n] = val;
			si_ctrl_setup(n, val[31:16], val[15:8], val[7:0]);
		end

		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 1, 4, `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		si_mem_addr(addr);
		si_read_dma(addr, `SI_DMA_WRITE, 1, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[0]);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[1]);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[2]);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[3]);
	end
endtask

// test recovery after joychannel kill by JCRST;

task si_jc_kill;
	reg [31:0] addr;		// memory dma address;
	reg [31:0] val;			// response value;
	reg [31:0] rsp [0:3];	// query responses;
	reg [31:0] rsp0;		// local ctrl responses;
	integer n;
	begin
		// start query and kill it with JCRST;

		$display("test: %M: start query");
		si_jctrl_mode(1, `JCTRL_ON, $random, 0);
		si_jctrl_mode(2, `JCTRL_ON, $random, 0);
		si_jctrl_mode(3, `JCTRL_ON, $random, 0);
		for(n = 0; n < 4; n = n + 1) begin
			val = $random;
			if(n == 0)
				si_lctrl_xy0(val);
			rsp[n] = val;
			si_ctrl_setup(n, val[31:16], val[15:8], val[7:0]);
		end

		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 1, 4, `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		$display("test: %M: kill query with reset");
		si_mem_addr(addr);
		si_read_dma(addr, 0, 1, 1, 0);
		si_ctrl_cmp(addr, 0, `JRSP_RESET, 1, 4, `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 1, `JRSP_RESET, 1, 4, `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 2, `JRSP_RESET, 1, 4, `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 3, `JRSP_RESET, 1, 4, `JCTRL_QUERY, 32'bx);

		// re-enable controllers;
		// do another query which should complete without errors;

		$display("test: %M: query after reset");
		si_jctrl_mode(1, `JCTRL_ON, $random, 0);
		si_jctrl_mode(2, `JCTRL_ON, $random, 0);
		si_jctrl_mode(3, `JCTRL_ON, $random, 0);
		si_mem_addr(addr);
		si_read_dma(addr, 0, 1, 0, 0);

		// jc_rst should have reset the xy sticks of the local controller;

		rsp0 = rsp[0];
		rsp0[15:8] = 0;
		rsp0[7:0] = 0;
		rsp[0] = rsp0;

		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[0]);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[1]);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[2]);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 4, `JCTRL_QUERY, rsp[3]);
	end
endtask

// test controller null commands;

task si_null_cmd;
	reg [31:0] addr;		// memory address;
	reg [31:0] rsp [0:3];	// random response data;
	integer n;
	begin
		// tx size of joychannel controllers are 0;
		// ctrl 0 should return very quickly;
		// rx size and command do not matter but must be legal;

		$display("test: %M: jctrls are idle");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 3, `JCTRL_STATUS);
		si_mem_setup(addr, 1, 0, 4, `JCTRL_RESET);
		si_mem_setup(addr, 2, 0, 1, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 0, 2, `JCTRL_STATUS);
		si_write_dma(addr, 32'd0);

		addr[2:0] = 'd0;
		for(n = 1; n < 4; n = n + 1)
			mem_sread(addr + 8*n + 4, `CPU_SIZE_4, rsp[n]);
		rsp[0] = 32'h00000000;

		// tx data should be unmodified;
		// except for ctrl0 which returns type/status;

		si_mem_addr(addr);
		si_read_dma(addr, 0, 0, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 3, `JCTRL_STATUS, rsp[0]);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 0, 4, `JCTRL_RESET, rsp[1]);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 0, 1, `JCTRL_QUERY, rsp[2]);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 0, 2, `JCTRL_STATUS, rsp[3]);
	end
endtask

// test illegal commands;

task si_ill_cmd;
	input rsprand;			// response randomization is on;
	reg [31:0] addr;		// memory address;
	reg [7:0] val;
	reg [7:0] cmd [0:3];	// random illegal commands;
	reg [7:0] txsz [1:3];	// tx sizes;
	reg [7:0] rxsz [1:3];	// rx sizes;
	reg [31:0] rsp [0:3];	// random response data;
	integer n;
	begin
		// ctrl 0 should return no response error;
		// turn on jctrl flag rsp_echo, so they reflect the tx data;

		$display("test: %M: unsupported commands");
		for(n = 0; n < 4; n = n + 1) begin
			si_ctrl_uncmd(val);
			cmd[n] = val;
			rxsz[n] = (val[1:0] + 1);
			txsz[n] = rxsz[n] + 1;
		end
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, cmd[0]);
		si_mem_setup(addr, 1, txsz[1], rxsz[1], cmd[1]);
		si_mem_setup(addr, 2, txsz[2], rxsz[2], cmd[2]);
		si_mem_setup(addr, 3, txsz[3], rxsz[3], cmd[3]);
		si_write_dma(addr, 32'd0);

		addr[2:0] = 'd0;
		for(n = 0; n < 4; n = n + 1)
			mem_sread(addr + 8*n + 4, `CPU_SIZE_4, rsp[n]);

		si_mem_addr(addr);
		si_read_dma(addr, 0, rsprand, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_NORSP | `JRSP_REQERR, 1, 4, cmd[0], rsp[0]);
		si_ctrl_cmp(addr, 1, `JRSP_OK, txsz[1], rxsz[1], cmd[1], rsp[1]);
		si_ctrl_cmp(addr, 2, `JRSP_OK, txsz[2], rxsz[2], cmd[2], rsp[2]);
		si_ctrl_cmp(addr, 3, `JRSP_OK, txsz[3], rxsz[3], cmd[3], rsp[3]);
	end
endtask

// test single command error detection mode;

task si_sgl_err;
	reg [31:0] addr;		// memory address;
	reg [31:0] config;		// config register;
	begin
		// byte[0] of ctrl 0 == 0x00 indicates single command;

		$display("test: %M: single error detection");
		sread(`SI_CONFIG, `CPU_SIZE_4, config);
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 3, `JCTRL_STATUS);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 1, 3, `JCTRL_RESET);
		si_mem_setup(addr, 3, 1, 4, `JCTRL_STATUS);
		addr[2:0] = 'd0;
		vsim.mem_swrite(addr, `CPU_SIZE_4, 0);
		si_write_dma(addr, 32'd0);

		// read dma should be done right away;

		si_mem_addr(addr);
		si_read_dma(addr, 0, 0, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_MASK, 8'hff, 8'hff, 8'hff, 32'bx);
		si_ctrl_cmp(addr, 1, `JRSP_MASK, 8'hff, 8'hff, 8'hff, 32'bx);
		si_ctrl_cmp(addr, 2, `JRSP_MASK, 8'hff, 8'hff, 8'hff, 32'bx);
		si_ctrl_cmp(addr, 3, `JRSP_MASK, 8'hff, 8'hff, 8'hff, 32'bx);
	end
endtask

// test illegal tx/rx sizes;
// size errors are independent of command;

task si_ill_sizes;
	input rsprand;			// response randomization is on;
	reg [31:0] addr;		// memory address;
	reg [7:0] txsz [0:3];	// tx sizes;
	reg [7:0] rxsz [0:3];	// rx sizes;
	integer n;
	begin
		$display("test: %M: illegal tx/rx sizes");
		for(n = 0; n < 4; n = n + 1) begin
			txsz[n] = 64 + $random;
			rxsz[n] = 64 + $random;
		end
		si_mem_addr(addr);
		si_mem_setup(addr, 0, txsz[0], rxsz[0], `JCTRL_QUERY);
		si_mem_setup(addr, 1, txsz[1], rxsz[1], `JCTRL_QUERY);
		si_mem_setup(addr, 2, txsz[2], rxsz[2], `JCTRL_QUERY);
		si_mem_setup(addr, 3, txsz[3], rxsz[3], `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		// only three bits of size are returned by hardware;

		for(n = 0; n < 4; n = n + 1) begin
			txsz[n] = txsz[n] & 8'h3f;
			rxsz[n] = rxsz[n] & 8'h07;
		end
		si_mem_addr(addr);
		si_read_dma(addr, 0, rsprand, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_REQERR, txsz[0], rxsz[0], `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 1, `JRSP_REQERR, txsz[1], rxsz[1], `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 2, `JRSP_REQERR, txsz[2], rxsz[2], `JCTRL_QUERY, 32'bx);
		si_ctrl_cmp(addr, 3, `JRSP_REQERR, txsz[3], rxsz[3], `JCTRL_QUERY, 32'bx);
	end
endtask

// check status of slave REQ bit;

task si_slave_req;
	input exp;			// expected value;
	reg [31:0] rdata;	// register data;
	begin
		sread(`SI_CTRL, `CPU_SIZE_4, rdata);
		if(rdata[1] !== exp)
			$display("ERROR: %t: %M: REQ bit %b exp %b", $time, rdata[1], exp);
	end
endtask

// test one si slave command;

task si_slave_proc;
	input [7:0] cmd;		// expected cmd;
	input [7:0] ecode;		// expected error code;
	input ts_exp;			// wait for tS to expire;
	reg [31:0] addr;		// memory address;
	reg [7:0] txsize;		// tx size;
	reg [7:0] rxsize;		// rx size;
	reg [31:0] cr;			// cmd/rsp bytes;
	reg [31:0] rdata;		// register data;
	begin
		$display("test: %M: cmd 0x%h", cmd);

		// setup rcv command for ctrl 1;
		// tx and rx size must not be 0;

		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 0, 0, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 0, 0, `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		// translate cmd into expected rx size;
		// for reserved commands (default), tx_size is
		// command dependent, but use same as rx size here;

		case(cmd)
			`JCTRL_STATUS: begin
				rxsize = 1;
				txsize = 3;
			end
			`JCTRL_QUERY: begin
				rxsize = 1;
				txsize = 4;
			end
			`JCTRL_READ: begin
				rxsize = 3;
				txsize = 33;
			end
			`JCTRL_WRITE: begin
				rxsize = 35;
				txsize = 1;
			end
			`JCTRL_RESET: begin
				rxsize = 1;
				txsize = 3;
			end
			default: begin
				rxsize = cmd[2:0];
				txsize = cmd[2:0];
			end
		endcase

		// read dma triggers cmd reception;
		// dma completes when rx packet has been received;

		cr = $random;
		si_master_setup(rxsize, cmd, cr, txsize);
		si_slave_req(0);
		si_mem_addr(addr);
		si_read_dma(addr, 0, 0, 0, 1); //XXX randomization;
		si_slave_req(1);
		si_slcmd_cmp(addr, 1, rxsize, cmd, cr, ecode);

		// formulate response;
		// use write dma to send command to si;

		si_mem_addr(addr);
		si_mem_setup(addr, 0, 0, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, txsize, 1, cmd);
		si_mem_setup(addr, 2, 0, 0, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 0, 0, `JCTRL_QUERY);
		addr[2:0] = 3'd0;
		vsim.mem_sread(addr + 12, `CPU_SIZE_4, cr);
		si_write_dma(addr, 32'd0);

		// kick off slave transmit phase;
		// spin on busy bit;
		// check reply in jchan master model;

		sread(`SI_CTRL, `CPU_SIZE_4, rdata);
		rdata[2] = 1;
		swrite(`SI_CTRL, `CPU_SIZE_4, rdata);
		si_slave_req(0);

		// XXX timeout
		sread(`SI_CTRL, `CPU_SIZE_4, rdata);
		while(rdata[2] === 1)
			sread(`SI_CTRL, `CPU_SIZE_4, rdata);
		si_slrsp_cmp(txsize, cr);

		// let transfer separator time expire;

		if(ts_exp) begin
			repeat(64000000 / vsim.sysclk_period) @(posedge sysclk);
		end
	end
endtask

// test si slave mode;

task si_test_slave;
	reg [31:0] rdata;		// read data;
	begin
		// turn off slave controller models;
		// switch to slave mode;

		$display("test: %M: slave on");
		si_jctrl_mode(1, `JCTRL_OFF, 0, 0);
		si_jctrl_mode(2, `JCTRL_OFF, 0, 0);
		si_jctrl_mode(3, `JCTRL_OFF, 0, 0);
		sread(`SI_CONFIG, `CPU_SIZE_4, rdata);
		rdata[31] = 1;
		swrite(`SI_CONFIG, `CPU_SIZE_4, rdata);

		// test all supported slave commands;

		si_jctrl_mode(1, `JCTRL_MASTER, 0, 0); //XXX more modes;

		si_slave_proc(`JCTRL_RESET, `JRSP_OK, 1);
		si_slave_proc(`JCTRL_STATUS, `JRSP_OK, 1);
		si_slave_proc(`JCTRL_QUERY, `JRSP_OK, 1);
		si_slave_proc(`JCTRL_READ, `JRSP_OK, 1);
		si_slave_proc(`JCTRL_WRITE, `JRSP_OK, 1);

		// XXX other cmds;
		// XXX test errors;


	end
endtask

// run all si tests sequentially;

task test_si;
	reg [31:0] addr;	// read dma memory address;
	begin
		// configure main memory;

		ri_config_ddr($random, $random);

		// run si reset test only once;
		// take joy channels out of reset;
		// enable fastest button sampling;

		si_after_reset;
		si_jcrst(0);
		si_but_config(1, 0);

		// check si dma address register;
		// addresses will be 8-byte aligned in hardware;

		si_dma_addr;

		// test dma without conflicts;
		// different command per controller;
		// the write dma just moves data to the si;

		$display("test: %M: no conflict");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 3, `JCTRL_STATUS);
		si_mem_setup(addr, 2, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 1, 3, `JCTRL_RESET);
		si_write_dma(addr, 32'd0);

		// trigger commands and compare results;
		// test error-free controller operation;
		// local controller x/y should be 0 after reset;

		si_jctrl_mode(1, `JCTRL_ON, 0, 0);
		si_jctrl_mode(2, `JCTRL_ON, 0, 0);
		si_jctrl_mode(3, `JCTRL_ON, 0, 0);
		si_ctrl_setup(0, 'h300f, 'h00, 'h00);
		si_ctrl_setup(1, 'h0ff0, 'h00, 'hff);
		si_ctrl_setup(2, 'h5a5a, 'h55, 'haa);
		si_ctrl_setup(3, 'ha5a5, 'haa, 'h55);

		si_mem_addr(addr);
		si_read_dma(addr, 32'd0, 0, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h300f0000);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 3, `JCTRL_STATUS, 32'h02000000);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h5a5a55aa);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 3, `JCTRL_RESET, 32'h02000000);

		// can only test dma conflicts with read dma,
		// because the write dma finishes too quickly;
		// the write dma is done before the cpu can do another write;
		// the read dma completes later because of the controller protocol;
		// each byte on the joychannel takes about 32 usec;

		// check SI_DRAM_ADDR conflict;
		// reuse same commands as above;
		// mod local controller

		$display("test: %M: SI_DMA_ADDR conflict");
		si_ctrl_setup(0, 'h0123, 'hfc, 'h05);
		si_ctrl_setup(1, 'h1234, 'h56, 'h78);
		si_ctrl_setup(2, 'h2345, 'h67, 'h89);
		si_ctrl_setup(3, 'h3456, 'h78, 'h9a);
		si_mem_addr(addr);
		si_read_dma(addr, `SI_DRAM_ADDR, 0, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h0123fc05);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 3, `JCTRL_STATUS, 32'h02000000);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h23456789);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 3, `JCTRL_RESET, 32'h02000000);

		// turn on jctrl response randomization;

		si_jctrl_mode(1, `JCTRL_ON, 1, 0);
		si_jctrl_mode(2, `JCTRL_ON, 1, 0);
		si_jctrl_mode(3, `JCTRL_ON, 1, 0);

		// check SI_DMA_READ conflict;
		// query all controllers;

		$display("test: %M: SI_DMA_READ conflict");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 1, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 2, 1, 4, `JCTRL_QUERY);
		si_mem_setup(addr, 3, 1, 4, `JCTRL_QUERY);
		si_write_dma(addr, 32'd0);

		si_ctrl_setup(0, 'h0123, 'h45, 'h67);
		si_ctrl_setup(1, 'h1234, 'h56, 'h78);
		si_ctrl_setup(2, 'h2345, 'h67, 'h89);
		si_ctrl_setup(3, 'h3456, 'h78, 'h9a);

		si_mem_addr(addr);
		si_read_dma(addr, `SI_DMA_READ, 1, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h01234567);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h12345678);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h23456789);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 4, `JCTRL_QUERY, 32'h3456789a);

		// check SI_DMA_WRITE conflict;
		// use status and reset commands;
		// both return the same status & type bits;

		$display("test: %M: SI_DMA_WRITE conflict");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 1, 3, `JCTRL_STATUS);
		si_mem_setup(addr, 1, 1, 3, `JCTRL_STATUS);
		si_mem_setup(addr, 2, 1, 3, `JCTRL_RESET);
		si_mem_setup(addr, 3, 1, 3, `JCTRL_RESET);
		si_write_dma(addr, 32'd0);

		si_mem_addr(addr);
		si_read_dma(addr, `SI_DMA_WRITE, 1, 0, 0);
		si_ctrl_cmp(addr, 0, `JRSP_OK, 1, 3, `JCTRL_STATUS, 32'h00000000);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 1, 3, `JCTRL_STATUS, 32'h02000000);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 1, 3, `JCTRL_RESET, 32'h02000000);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 1, 3, `JCTRL_RESET, 32'h02000000);

		// test write commands;
		// not supported on local controller;

		$display("test: %M: WRITE commands");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 35, 1, `JCTRL_WRITE);
		si_mem_setup(addr, 1, 35, 1, `JCTRL_WRITE);
		si_mem_setup(addr, 2, 35, 1, `JCTRL_WRITE);
		si_mem_setup(addr, 3, 35, 1, `JCTRL_WRITE);
		si_write_dma(addr, 32'd0);

		si_mem_addr(addr);
		si_read_dma(addr, 32'd0, 1, 0, 0);
		si_jrx_cmp(1, 35);
		si_jrx_cmp(2, 35);
		si_jrx_cmp(3, 35);
		si_ctrl_cmp(addr, 0, `JRSP_NORSP | `JRSP_REQERR, 35, 1, `JCTRL_WRITE, 32'bx);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 35, 1, `JCTRL_WRITE, { si_jcrc[1], 24'bx });
		si_ctrl_cmp(addr, 2, `JRSP_OK, 35, 1, `JCTRL_WRITE, { si_jcrc[2], 24'bx });
		si_ctrl_cmp(addr, 3, `JRSP_OK, 35, 1, `JCTRL_WRITE, { si_jcrc[3], 24'bx });

		// test read commands;
		// not supported on local controller;

		$display("test: %M: READ commands");
		si_mem_addr(addr);
		si_mem_setup(addr, 0, 3, 33, `JCTRL_READ);
		si_mem_setup(addr, 1, 3, 33, `JCTRL_READ);
		si_mem_setup(addr, 2, 3, 33, `JCTRL_READ);
		si_mem_setup(addr, 3, 3, 33, `JCTRL_READ);
		si_write_dma(addr, 32'd0);

		si_mem_addr(addr);
		si_read_dma(addr, 32'd0, 1, 0, 0);
		si_jrx_cmp(1, 3);
		si_jrx_cmp(2, 3);
		si_jrx_cmp(3, 3);
		si_jrsp_setup;
		si_ctrl_cmp(addr, 0, `JRSP_NORSP | `JRSP_REQERR, 3, 33 & 7, `JCTRL_READ, 32'bx);
		si_ctrl_cmp(addr, 1, `JRSP_OK, 3, 33 & 7, `JCTRL_READ, si_jrsp[1]);
		si_ctrl_cmp(addr, 2, `JRSP_OK, 3, 33 & 7, `JCTRL_READ, si_jrsp[2]);
		si_ctrl_cmp(addr, 3, `JRSP_OK, 3, 33 & 7, `JCTRL_READ, si_jrsp[3]);

		// test joychannel error handling;
		// test recovery after kill by controller reset;

		si_jc_error;
		si_jc_kill;

		// test ctrl 0 while jctrls are not used;
		// test unsupported commands;
		// test single command error detection mode;
		// test illegal tx/rx sizes;

		si_jctrl_mode(1, `JCTRL_ON, $random, 1);
		si_jctrl_mode(2, `JCTRL_ON, $random, 1);
		si_jctrl_mode(3, `JCTRL_ON, $random, 1);
		si_null_cmd;
		si_sgl_err;
		si_ill_cmd(1);
		si_ill_sizes(1);

		// test slave mode;

		si_test_slave;
	end
endtask