#include <sys/types.h>
#ifdef __sgi__
#include <sys/sbd.h>
#endif
#include <sys/stat.h>
#include <sys/mman.h>
#ifdef __sgi__
#include <sys/sema.h>
#endif
#include <netinet/in.h>

#include <errno.h>
#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <getopt.h>

#include <rcp.h>
#include <rsp.h>

#define DMEM_SIZE 4096
#define IMEM_SIZE 4096

#define IBIST_REG_MSK 0x0000007f
/*
 * From $ROOT/usr/include/ide, which is installed from $ROOT/PR/diags/include
 */
#include "diag.h"
#include "dbg_comm.h"

#define RSP_OTHER_TEST_BASE	1
#define RSP_TEST_BASE	7

static int rsptest(TEST_REF *test_ref);
static int NumFailures = 0;

static int rsp_Init();
static int rsp_Do(TEST_REF *test_ref);
static int imem_marching_1(void);
static int dmem_marching_1(void);
static int mem_marching_1(unsigned int start_addr, unsigned int end_addr);
static int imem_pattern(void);
static int dmem_pattern(void);
static int mem_pattern(unsigned int start_addr, unsigned int end_addr);
static int imem_bist(void);
static int pc_r_w(void);
extern int surf1();
extern int surf2();
extern int vurf1();
extern int vurfcs();
extern int prmem();
extern int add1();
extern int add2();
extern int addi1();
extern int addi2();
extern int addiu1();
extern int addiu2();
extern int addu1();
extern int addu2();
extern int slt1();
extern int slt2();
extern int slti1();
extern int slti2();
extern int sltiu1();
extern int sltiu2();
extern int sltu1();
extern int sltu2();
extern int sub1();
extern int sub2();
extern int subu1();
extern int subu2();
extern int beq1();
extern int bgez1();
extern int bgezal1();
extern int bgezal2();
extern int bgtz1();
extern int blez1();
extern int bltz1();
extern int bltzal1();
extern int bltzal2();
extern int bne1();
extern int j1();
extern int jal1();
extern int jalr1();
extern int jr1();
extern int cfc21();
extern int cfc22();
extern int ctc21();
extern int ctc22();
extern int mfc21();
extern int mfc22();
extern int mfc23();
extern int mfc24();
extern int mfc25();
extern int mfc26();
extern int mtc21();
extern int mtc22();
extern int mtc23();
extern int mtc24();
extern int mtc25();
extern int mtc26();
extern int lb1();
extern int lbu1();
extern int lh1();
extern int lhu1();
extern int lw1();
extern int and1();
extern int and2();
extern int andi1();
extern int lui1();
extern int nor1();
extern int nor2();
extern int or1();
extern int or2();
extern int ori1();
extern int xor1();
extern int xor2();
extern int xori1();
extern int sll1();
extern int sllv1();
extern int sllv2();
extern int sra1();
extern int srav1();
extern int srav2();
extern int srl1();
extern int srlv1();
extern int srlv2();
extern int sb1();
extern int sh1();
extern int sw1();
extern int vabs_h();
extern int vabs_q();
extern int vabs_v();
extern int vabs_w();
extern int vadd_h();
extern int vadd_q();
extern int vadd_v();
extern int vadd_w();
extern int vaddc_h();
extern int vaddc_q();
extern int vaddc_v();
extern int vaddc_w();
extern int veq_dbl_v();
extern int veq_h();
extern int veq_q();
extern int veq_v();
extern int veq_w();
extern int vge_dbl_v();
extern int vge_h();
extern int vge_q();
extern int vge_v();
extern int vge_w();
extern int vlt_dbl_v();
extern int vlt_h();
extern int vlt_q();
extern int vlt_v();
extern int vlt_w();
extern int vne_dbl_v();
extern int vne_h();
extern int vne_q();
extern int vne_v();
extern int vne_w();
extern int dp_recp_chain_mix();
extern int dp_recp_chain_neg();
extern int dp_recp_chain_pos();
extern int dp_recp_mix();
extern int dp_recp_neg();
extern int dp_recp_pos();
extern int dp_sqrt_chain_mix();
extern int dp_sqrt_chain_neg();
extern int dp_sqrt_chain_pos();
extern int dp_sqrt_mix();
extern int dp_sqrt_neg();
extern int dp_sqrt_pos();
extern int lbv1();
extern int lbv2();
extern int lbv3();
extern int ldv1();
extern int ldv2();
extern int ldv3();
extern int lfv1();
extern int lfv2();
extern int lhv1();
extern int lhv2();
extern int llv1();
extern int llv2();
extern int llv3();
extern int lpv1();
extern int lpv2();
extern int lpv3();
extern int lqv1();
extern int lqv2();
extern int lqv3();
extern int lrv1();
extern int lrv2();
extern int lrv3();
extern int lsv1();
extern int lsv2();
extern int lsv3();
extern int ltv1();
extern int luv1();
extern int luv2();
extern int luv3();
extern int vand();
extern int vnand();
extern int vnor();
extern int vor();
extern int vxnor();
extern int vxor();
extern int vmacf_clamp();
extern int vmacf_h();
extern int vmacf_q();
extern int vmacf_v();
extern int vmacf_w();
extern int vmacq_v();
extern int vmacq_v1();
extern int vmacq_v2();
extern int vmacu_clamp();
extern int vmacu_h();
extern int vmacu_q();
extern int vmacu_v();
extern int vmacu_w();
extern int vmadh1_h();
extern int vmadh1_q();
extern int vmadh1_v();
extern int vmadh1_w();
extern int vmadh_clamp();
extern int vmadh_h();
extern int vmadh_q();
extern int vmadh_v();
extern int vmadh_v1();
extern int vmadh_w();
extern int vmadl_clamp();
extern int vmadl_h();
extern int vmadl_q();
extern int vmadl_v();
extern int vmadl_w();
extern int vmadm_clamp();
extern int vmadm_h();
extern int vmadm_q();
extern int vmadm_v();
extern int vmadm_v1();
extern int vmadm_w();
extern int vmadn_clamp();
extern int vmadn_h();
extern int vmadn_q();
extern int vmadn_v();
extern int vmadn_v1();
extern int vmadn_w();
extern int vmov();
extern int vmrg_h();
extern int vmrg_q();
extern int vmrg_v();
extern int vmrg_w();
extern int vmudh1_h();
extern int vmudh1_q();
extern int vmudh1_v();
extern int vmudh1_w();
extern int vmudh_h();
extern int vmudh_q();
extern int vmudh_v();
extern int vmudh_v1();
extern int vmudh_w();
extern int vmudl_h();
extern int vmudl_q();
extern int vmudl_v();
extern int vmudl_v1();
extern int vmudl_w();
extern int vmudm_h();
extern int vmudm_q();
extern int vmudm_v();
extern int vmudm_v1();
extern int vmudm_w();
extern int vmudn_h();
extern int vmudn_q();
extern int vmudn_v();
extern int vmudn_v1();
extern int vmudn_w();
extern int vmulf_h();
extern int vmulf_q();
extern int vmulf_v();
extern int vmulf_v1();
extern int vmulf_w();
extern int vmulq_v();
extern int vmulu_h();
extern int vmulu_q();
extern int vmulu_v();
extern int vmulu_v1();
extern int vmulu_w();
extern int vrndn_h();
extern int vrndn_q();
extern int vrndn_v();
extern int vrndn_v1();
extern int vrndn_w();
extern int vrndp_h();
extern int vrndp_q();
extern int vrndp_v();
extern int vrndp_v1();
extern int vrndp_w();
extern int rom_test1();
extern int rom_test2();
extern int rom_test3();
extern int rom_test4();
extern int rom_test5();
extern int rom_test6();
extern int rom_test7();
extern int rom_test8();
extern int vsaw();
extern int sp_recp_mix();
extern int sp_recp_neg();
extern int sp_recp_pos();
extern int sp_sqrt_mix();
extern int sp_sqrt_neg();
extern int sp_sqrt_pos();
extern int sbv1();
extern int sbv2();
extern int sbv3();
extern int sbv4();
extern int sdv1();
extern int sdv2();
extern int sdv3();
extern int sdv4();
extern int sfv1();
extern int sfv2();
extern int shv1();
extern int shv2();
extern int slv1();
extern int slv2();
extern int slv3();
extern int slv4();
extern int spv1();
extern int spv2();
extern int spv3();
extern int spv4();
extern int sqv1();
extern int sqv2();
extern int sqv3();
extern int sqv4();
extern int srv1();
extern int srv2();
extern int srv3();
extern int srv4();
extern int ssv1();
extern int ssv2();
extern int ssv3();
extern int ssv4();
extern int stv1();
extern int suv1();
extern int suv2();
extern int suv3();
extern int suv4();
extern int swv1();
extern int vsub_h();
extern int vsub_q();
extern int vsub_v();
extern int vsub_w();
extern int vsubc_h();
extern int vsubc_q();
extern int vsubc_v();
extern int vsubc_w();
extern int vch_v();
extern int vcl_v();
extern int vcr_v();
extern int iltest1();
extern int iltest2();
extern int iltest3();
extern int iltest4();
extern int iltest5();
extern int iltest6();
extern int iltest7();
extern int iltest8();
extern int iltest9();
extern int iltest10();
extern int iltest11();
extern int iltest12();
extern int iltest13();
extern int iltest14();
extern int iltest15();
extern int iltest16();
extern int iltest17();
extern int iltest18();
extern int iltest19();
extern int iltest20();
extern int iltest21();
extern int iltest22();
extern int iltest23();
extern int iltest24();
extern int iltest25();
extern int di_ctlhz000();
extern int di_ctlhz001();
extern int di_ctlhz002();
extern int di_ctlhz010();
extern int di_ctlhz011();
extern int di_ctlhz012();
extern int di_ctlhz100();
extern int di_ctlhz101();
extern int di_ctlhz102();
extern int di_ctlhz110();
extern int di_ctlhz111();
extern int di_ctlhz112();
extern int di_ldst00();
extern int di_ldst01();
extern int di_ldst02();
extern int di_ldst03();
extern int di_ldst10();
extern int di_ldst11();
extern int di_ldst12();
extern int di_ldst13();
extern int di_ldst20();
extern int di_ldst21();
extern int di_ldst22();
extern int di_ldst23();
extern int di_ldst30();
extern int di_ldst31();
extern int di_ldst32();
extern int di_ldst33();
extern int di_norm00();
extern int di_norm01();
extern int di_norm02();
extern int di_norm03();
extern int di_norm10();
extern int di_norm11();
extern int di_norm12();
extern int di_norm13();
extern int di_norm20();
extern int di_norm21();
extern int di_norm22();
extern int di_norm23();
extern int di_norm30();
extern int di_norm31();
extern int di_norm32();
extern int di_norm33();
extern int di_reghz0();
extern int di_reghz1();
extern int di_reghz2();
extern int di_reghz3();
extern int bpmult();
extern int bptest0();
extern int bptest1();
extern int bptest2();
extern int bptest3();
extern int bptest4();
extern int dma00();
extern int dma01();
extern int dma02();
extern int dma10();
extern int dma11();
extern int dma12();
extern int dma13();
extern int dma14();
extern int dma20();
extern int dma21();
extern int dma22();
extern int dma30();
extern int dma31();
extern int dma32();
extern int dma33();
extern int dma34();
extern int dma35();
extern int dma36();
extern int dma40();
extern int dma50();
/*
extern int dma60();
extern int dma70();
*/

/*
 * Create an array of tests, each of which corresponds to a separate menu
 * item callable from the master ide menu.
 */
static TEST_REF TestRefs[] = {
  {"Sequential IMem Marching 1 Test", RSP_OTHER_TEST_BASE+0, imem_marching_1},
  {"Sequential DMem Marching 1 Test", RSP_OTHER_TEST_BASE+1, dmem_marching_1},
  {"IMem Pattern Test", RSP_OTHER_TEST_BASE+2, imem_pattern},
  {"DMem Pattern Test", RSP_OTHER_TEST_BASE+3, dmem_pattern},
  {"IMem BIST", RSP_OTHER_TEST_BASE+4, imem_bist},
  {"PC Read Write", RSP_OTHER_TEST_BASE+5, pc_r_w},
  {"surf1",		RSP_TEST_BASE+0, surf1},
  {"surf2",		RSP_TEST_BASE+1, surf2},
  {"vurf1",		RSP_TEST_BASE+2, vurf1},
  {"vurfcs",		RSP_TEST_BASE+3, vurfcs},
  {"prmem",		RSP_TEST_BASE+4, prmem},
  {"add1",		RSP_TEST_BASE+5, add1},
  {"add2",		RSP_TEST_BASE+6, add2},
  {"addi1",		RSP_TEST_BASE+7, addi1},
  {"addi2",		RSP_TEST_BASE+8, addi2},
  {"addiu1",		RSP_TEST_BASE+9, addiu1},
  {"addiu2",		RSP_TEST_BASE+10, addiu2},
  {"addu1",		RSP_TEST_BASE+11, addu1},
  {"addu2",		RSP_TEST_BASE+12, addu2},
  {"slt1",		RSP_TEST_BASE+13, slt1},
  {"slt2",		RSP_TEST_BASE+14, slt2},
  {"slti1",		RSP_TEST_BASE+15, slti1},
  {"slti2",		RSP_TEST_BASE+16, slti2},
  {"sltiu1",		RSP_TEST_BASE+17, sltiu1},
  {"sltiu2",		RSP_TEST_BASE+18, sltiu2},
  {"sltu1",		RSP_TEST_BASE+19, sltu1},
  {"sltu2",		RSP_TEST_BASE+20, sltu2},
  {"sub1",		RSP_TEST_BASE+21, sub1},
  {"sub2",		RSP_TEST_BASE+22, sub2},
  {"subu1",		RSP_TEST_BASE+23, subu1},
  {"subu2",		RSP_TEST_BASE+24, subu2},
  {"beq1",		RSP_TEST_BASE+25, beq1},
  {"bgez1",		RSP_TEST_BASE+26, bgez1},
  {"bgezal1",		RSP_TEST_BASE+27, bgezal1},
  {"bgezal2",		RSP_TEST_BASE+28, bgezal2},
  {"bgtz1",		RSP_TEST_BASE+29, bgtz1},
  {"blez1",		RSP_TEST_BASE+30, blez1},
  {"bltz1",		RSP_TEST_BASE+31, bltz1},
  {"bltzal1",		RSP_TEST_BASE+32, bltzal1},
  {"bltzal2",		RSP_TEST_BASE+33, bltzal2},
  {"bne1",		RSP_TEST_BASE+34, bne1},
  {"j1",		RSP_TEST_BASE+35, j1},
  {"jal1",		RSP_TEST_BASE+36, jal1},
  {"jalr1",		RSP_TEST_BASE+37, jalr1},
  {"jr1",		RSP_TEST_BASE+38, jr1},
  {"cfc21",		RSP_TEST_BASE+39, cfc21},
  {"cfc22",		RSP_TEST_BASE+40, cfc22},
  {"ctc21",		RSP_TEST_BASE+41, ctc21},
  {"ctc22",		RSP_TEST_BASE+42, ctc22},
  {"mfc21",		RSP_TEST_BASE+43, mfc21},
  {"mfc22",		RSP_TEST_BASE+44, mfc22},
  {"mfc23",		RSP_TEST_BASE+45, mfc23},
  {"mfc24",		RSP_TEST_BASE+46, mfc24},
  {"mfc25",		RSP_TEST_BASE+47, mfc25},
  {"mfc26",		RSP_TEST_BASE+48, mfc26},
  {"mtc21",		RSP_TEST_BASE+49, mtc21},
  {"mtc22",		RSP_TEST_BASE+50, mtc22},
  {"mtc23",		RSP_TEST_BASE+51, mtc23},
  {"mtc24",		RSP_TEST_BASE+52, mtc24},
  {"mtc25",		RSP_TEST_BASE+53, mtc25},
  {"mtc26",		RSP_TEST_BASE+54, mtc26},
  {"lb1",		RSP_TEST_BASE+55, lb1},
  {"lbu1",		RSP_TEST_BASE+56, lbu1},
  {"lh1",		RSP_TEST_BASE+57, lh1},
  {"lhu1",		RSP_TEST_BASE+58, lhu1},
  {"lw1",		RSP_TEST_BASE+59, lw1},
  {"and1",		RSP_TEST_BASE+60, and1},
  {"and2",		RSP_TEST_BASE+61, and2},
  {"andi1",		RSP_TEST_BASE+62, andi1},
  {"lui1",		RSP_TEST_BASE+63, lui1},
  {"nor1",		RSP_TEST_BASE+64, nor1},
  {"nor2",		RSP_TEST_BASE+65, nor2},
  {"or1",		RSP_TEST_BASE+66, or1},
  {"or2",		RSP_TEST_BASE+67, or2},
  {"ori1",		RSP_TEST_BASE+68, ori1},
  {"xor1",		RSP_TEST_BASE+69, xor1},
  {"xor2",		RSP_TEST_BASE+70, xor2},
  {"xori1",		RSP_TEST_BASE+71, xori1},
  {"sll1",		RSP_TEST_BASE+72, sll1},
  {"sllv1",		RSP_TEST_BASE+73, sllv1},
  {"sllv2",		RSP_TEST_BASE+74, sllv2},
  {"sra1",		RSP_TEST_BASE+75, sra1},
  {"srav1",		RSP_TEST_BASE+76, srav1},
  {"srav2",		RSP_TEST_BASE+77, srav2},
  {"srl1",		RSP_TEST_BASE+78, srl1},
  {"srlv1",		RSP_TEST_BASE+79, srlv1},
  {"srlv2",		RSP_TEST_BASE+80, srlv2},
  {"sb1",		RSP_TEST_BASE+81, sb1},
  {"sh1",		RSP_TEST_BASE+82, sh1},
  {"sw1",		RSP_TEST_BASE+83, sw1},
  {"vabs_h",		RSP_TEST_BASE+84, vabs_h},
  {"vabs_q",		RSP_TEST_BASE+85, vabs_q},
  {"vabs_v",		RSP_TEST_BASE+86, vabs_v},
  {"vabs_w",		RSP_TEST_BASE+87, vabs_w},
  {"vadd_h",		RSP_TEST_BASE+88, vadd_h},
  {"vadd_q",		RSP_TEST_BASE+89, vadd_q},
  {"vadd_v",		RSP_TEST_BASE+90, vadd_v},
  {"vadd_w",		RSP_TEST_BASE+91, vadd_w},
  {"vaddc_h",		RSP_TEST_BASE-8+100, vaddc_h},
  {"vaddc_q",		RSP_TEST_BASE-8+101, vaddc_q},
  {"vaddc_v",		RSP_TEST_BASE-8+102, vaddc_v},
  {"vaddc_w",		RSP_TEST_BASE-8+103, vaddc_w},
  {"veq_dbl_v",		RSP_TEST_BASE-8+104, veq_dbl_v},
  {"veq_h",		RSP_TEST_BASE-8+105, veq_h},
  {"veq_q",		RSP_TEST_BASE-8+106, veq_q},
  {"veq_v",		RSP_TEST_BASE-8+107, veq_v},
  {"veq_w",		RSP_TEST_BASE-8+108, veq_w},
  {"vge_dbl_v",		RSP_TEST_BASE-8+109, vge_dbl_v},
  {"vge_h",		RSP_TEST_BASE-8+110, vge_h},
  {"vge_q",		RSP_TEST_BASE-8+111, vge_q},
  {"vge_v",		RSP_TEST_BASE-8+112, vge_v},
  {"vge_w",		RSP_TEST_BASE-8+113, vge_w},
  {"vlt_dbl_v",		RSP_TEST_BASE-8+114, vlt_dbl_v},
  {"vlt_h",		RSP_TEST_BASE-8+115, vlt_h},
  {"vlt_q",		RSP_TEST_BASE-8+116, vlt_q},
  {"vlt_v",		RSP_TEST_BASE-8+117, vlt_v},
  {"vlt_w",		RSP_TEST_BASE-8+118, vlt_w},
  {"vne_dbl_v",		RSP_TEST_BASE-8+119, vne_dbl_v},
  {"vne_h",		RSP_TEST_BASE-8+120, vne_h},
  {"vne_q",		RSP_TEST_BASE-8+121, vne_q},
  {"vne_v",		RSP_TEST_BASE-8+122, vne_v},
  {"vne_w",		RSP_TEST_BASE-8+123, vne_w},
  {"dp_recp_chain_mix",	RSP_TEST_BASE-8+124, dp_recp_chain_mix},
  {"dp_recp_chain_neg",	RSP_TEST_BASE-8+125, dp_recp_chain_neg},
  {"dp_recp_chain_pos",	RSP_TEST_BASE-8+126, dp_recp_chain_pos},
  {"dp_recp_mix",	RSP_TEST_BASE-8+127, dp_recp_mix},
  {"dp_recp_neg",	RSP_TEST_BASE-8+128, dp_recp_neg},
  {"dp_recp_pos",	RSP_TEST_BASE-8+129, dp_recp_pos},
  {"dp_sqrt_chain_mix",	RSP_TEST_BASE-8+130, dp_sqrt_chain_mix},
  {"dp_sqrt_chain_neg",	RSP_TEST_BASE-8+131, dp_sqrt_chain_neg},
  {"dp_sqrt_chain_pos",	RSP_TEST_BASE-8+132, dp_sqrt_chain_pos},
  {"dp_sqrt_mix",	RSP_TEST_BASE-8+133, dp_sqrt_mix},
  {"dp_sqrt_neg",	RSP_TEST_BASE-8+134, dp_sqrt_neg},
  {"dp_sqrt_pos",	RSP_TEST_BASE-8+135, dp_sqrt_pos},
  {"lbv1",		RSP_TEST_BASE-24+152, lbv1},
  {"lbv2",		RSP_TEST_BASE-24+153, lbv2},
  {"lbv3",		RSP_TEST_BASE-24+154, lbv3},
  {"ldv1",		RSP_TEST_BASE-24+155, ldv1},
  {"ldv2",		RSP_TEST_BASE-24+156, ldv2},
  {"ldv3",		RSP_TEST_BASE-24+157, ldv3},
  {"lfv1",		RSP_TEST_BASE-24+158, lfv1},
  {"lfv2",		RSP_TEST_BASE-24+159, lfv2},
  {"lhv1",		RSP_TEST_BASE-24+160, lhv1},
  {"lhv2",		RSP_TEST_BASE-24+161, lhv2},
  {"llv1",		RSP_TEST_BASE-24+162, llv1},
  {"llv2",		RSP_TEST_BASE-24+163, llv2},
  {"llv3",		RSP_TEST_BASE-24+164, llv3},
  {"lpv1",		RSP_TEST_BASE-24+165, lpv1},
  {"lpv2",		RSP_TEST_BASE-24+166, lpv2},
  {"lpv3",		RSP_TEST_BASE-24+167, lpv3},
  {"lqv1",		RSP_TEST_BASE-24+168, lqv1},
  {"lqv2",		RSP_TEST_BASE-24+169, lqv2},
  {"lqv3",		RSP_TEST_BASE-24+170, lqv3},
  {"lrv1",		RSP_TEST_BASE-24+171, lrv1},
  {"lrv2",		RSP_TEST_BASE-24+172, lrv2},
  {"lrv3",		RSP_TEST_BASE-24+173, lrv3},
  {"lsv1",		RSP_TEST_BASE-24+174, lsv1},
  {"lsv2",		RSP_TEST_BASE-24+175, lsv2},
  {"lsv3",		RSP_TEST_BASE-24+176, lsv3},
  {"ltv1",		RSP_TEST_BASE-24+177, ltv1},
  {"luv1",		RSP_TEST_BASE-24+178, luv1},
  {"luv2",		RSP_TEST_BASE-24+179, luv2},
  {"luv3",		RSP_TEST_BASE-24+180, luv3},
  {"vand",		RSP_TEST_BASE-24+181, vand},
  {"vnand",		RSP_TEST_BASE-24+182, vnand},
  {"vnor",		RSP_TEST_BASE-24+183, vnor},
  {"vor",		RSP_TEST_BASE-24+184, vor},
  {"vxnor",		RSP_TEST_BASE-24+185, vxnor},
  {"vxor",		RSP_TEST_BASE-24+186, vxor},
  {"vmacf_clamp",	RSP_TEST_BASE-24+187, vmacf_clamp},
  {"vmacf_h",		RSP_TEST_BASE-24+188, vmacf_h},
  {"vmacf_q",		RSP_TEST_BASE-24+189, vmacf_q},
  {"vmacf_v",		RSP_TEST_BASE-24+190, vmacf_v},
  {"vmacf_w",		RSP_TEST_BASE-24+191, vmacf_w},
  {"vmacq_v",		RSP_TEST_BASE-24+192, vmacq_v},
  {"vmacq_v1",		RSP_TEST_BASE-24+193, vmacq_v1},
  {"vmacq_v2",		RSP_TEST_BASE-24+194, vmacq_v2},
  {"vmacu_clamp",	RSP_TEST_BASE-24+195, vmacu_clamp},
  {"vmacu_h",		RSP_TEST_BASE-24+196, vmacu_h},
  {"vmacu_q",		RSP_TEST_BASE-24+197, vmacu_q},
  {"vmacu_v",		RSP_TEST_BASE-24+198, vmacu_v},
  {"vmacu_w",		RSP_TEST_BASE-24+199, vmacu_w},
  {"vmadh1_h",		RSP_TEST_BASE-24+200, vmadh1_h},
  {"vmadh1_q",		RSP_TEST_BASE-24+201, vmadh1_q},
  {"vmadh1_v",		RSP_TEST_BASE-24+202, vmadh1_v},
  {"vmadh1_w",		RSP_TEST_BASE-24+203, vmadh1_w},
  {"vmadh_clamp",	RSP_TEST_BASE-24+204, vmadh_clamp},
  {"vmadh_h",		RSP_TEST_BASE-24+205, vmadh_h},
  {"vmadh_q",		RSP_TEST_BASE-24+206, vmadh_q},
  {"vmadh_v",		RSP_TEST_BASE-24+207, vmadh_v},
  {"vmadh_v1",		RSP_TEST_BASE-24+208, vmadh_v1},
  {"vmadh_w",		RSP_TEST_BASE-24+209, vmadh_w},
  {"vmadl_clamp",	RSP_TEST_BASE-24+210, vmadl_clamp},
  {"vmadl_h",		RSP_TEST_BASE-24+211, vmadl_h},
  {"vmadl_q",		RSP_TEST_BASE-24+212, vmadl_q},
  {"vmadl_v",		RSP_TEST_BASE-24+213, vmadl_v},
  {"vmadl_w",		RSP_TEST_BASE-24+214, vmadl_w},
  {"vmadm_clamp",	RSP_TEST_BASE-24+215, vmadm_clamp},
  {"vmadm_h",		RSP_TEST_BASE-24+216, vmadm_h},
  {"vmadm_q",		RSP_TEST_BASE-24+217, vmadm_q},
  {"vmadm_v",		RSP_TEST_BASE-24+218, vmadm_v},
  {"vmadm_v1",		RSP_TEST_BASE-24+219, vmadm_v1},
  {"vmadm_w",		RSP_TEST_BASE-24+220, vmadm_w},
  {"vmadn_clamp",	RSP_TEST_BASE-24+221, vmadn_clamp},
  {"vmadn_h",		RSP_TEST_BASE-24+222, vmadn_h},
  {"vmadn_q",		RSP_TEST_BASE-24+223, vmadn_q},
  {"vmadn_v",		RSP_TEST_BASE-24+224, vmadn_v},
  {"vmadn_v1",		RSP_TEST_BASE-24+225, vmadn_v1},
  {"vmadn_w",		RSP_TEST_BASE-24+226, vmadn_w},
  {"vmov",		RSP_TEST_BASE-24+227, vmov},
  {"vmrg_h",		RSP_TEST_BASE-24+228, vmrg_h},
  {"vmrg_q",		RSP_TEST_BASE-24+229, vmrg_q},
  {"vmrg_v",		RSP_TEST_BASE-24+230, vmrg_v},
  {"vmrg_w",		RSP_TEST_BASE-24+231, vmrg_w},
  {"vmudh1_h",		RSP_TEST_BASE-24+232, vmudh1_h},
  {"vmudh1_q",		RSP_TEST_BASE-24+233, vmudh1_q},
  {"vmudh1_v",		RSP_TEST_BASE-24+234, vmudh1_v},
  {"vmudh1_w",		RSP_TEST_BASE-24+235, vmudh1_w},
  {"vmudh_h",		RSP_TEST_BASE-24+236, vmudh_h},
  {"vmudh_q",		RSP_TEST_BASE-24+237, vmudh_q},
  {"vmudh_v",		RSP_TEST_BASE-24+238, vmudh_v},
  {"vmudh_v1",		RSP_TEST_BASE-24+239, vmudh_v1},
  {"vmudh_w",		RSP_TEST_BASE-24+240, vmudh_w},
  {"vmudl_h",		RSP_TEST_BASE-24+241, vmudl_h},
  {"vmudl_q",		RSP_TEST_BASE-24+242, vmudl_q},
  {"vmudl_v",		RSP_TEST_BASE-24+243, vmudl_v},
  {"vmudl_v1",		RSP_TEST_BASE-24+244, vmudl_v1},
  {"vmudl_w",		RSP_TEST_BASE-24+245, vmudl_w},
  {"vmudm_h",		RSP_TEST_BASE-24+246, vmudm_h},
  {"vmudm_q",		RSP_TEST_BASE-24+247, vmudm_q},
  {"vmudm_v",		RSP_TEST_BASE-24+248, vmudm_v},
  {"vmudm_v1",		RSP_TEST_BASE-24+249, vmudm_v1},
  {"vmudm_w",		RSP_TEST_BASE-24+250, vmudm_w},
  {"vmudn_h",		RSP_TEST_BASE-24+251, vmudn_h},
  {"vmudn_q",		RSP_TEST_BASE-24+252, vmudn_q},
  {"vmudn_v",		RSP_TEST_BASE-24+253, vmudn_v},
  {"vmudn_v1",		RSP_TEST_BASE-24+254, vmudn_v1},
  {"vmudn_w",		RSP_TEST_BASE-24+255, vmudn_w},
  {"vmulf_h",		RSP_TEST_BASE-24+256, vmulf_h},
  {"vmulf_q",		RSP_TEST_BASE-24+257, vmulf_q},
  {"vmulf_v",		RSP_TEST_BASE-24+258, vmulf_v},
  {"vmulf_v1",		RSP_TEST_BASE-24+259, vmulf_v1},
  {"vmulf_w",		RSP_TEST_BASE-24+260, vmulf_w},
  {"vmulq_v",		RSP_TEST_BASE-24+261, vmulq_v},
  {"vmulu_h",		RSP_TEST_BASE-24+262, vmulu_h},
  {"vmulu_q",		RSP_TEST_BASE-24+263, vmulu_q},
  {"vmulu_v",		RSP_TEST_BASE-24+264, vmulu_v},
  {"vmulu_v1",		RSP_TEST_BASE-24+265, vmulu_v1},
  {"vmulu_w",		RSP_TEST_BASE-24+266, vmulu_w},
  {"vrndn_h",		RSP_TEST_BASE-24+267, vrndn_h},
  {"vrndn_q",		RSP_TEST_BASE-24+268, vrndn_q},
  {"vrndn_v",		RSP_TEST_BASE-24+269, vrndn_v},
  {"vrndn_v1",		RSP_TEST_BASE-24+270, vrndn_v1},
  {"vrndn_w",		RSP_TEST_BASE-24+271, vrndn_w},
  {"vrndp_h",		RSP_TEST_BASE-24+272, vrndp_h},
  {"vrndp_q",		RSP_TEST_BASE-24+273, vrndp_q},
  {"vrndp_v",		RSP_TEST_BASE-24+274, vrndp_v},
  {"vrndp_v1",		RSP_TEST_BASE-24+275, vrndp_v1},
  {"vrndp_w",		RSP_TEST_BASE-24+276, vrndp_w},
  {"rom_test1",		RSP_TEST_BASE-24+277, rom_test1},
  {"rom_test2",		RSP_TEST_BASE-24+278, rom_test2},
  {"rom_test3",		RSP_TEST_BASE-24+279, rom_test3},
  {"rom_test4",		RSP_TEST_BASE-24+280, rom_test4},
  {"rom_test5",		RSP_TEST_BASE-24+281, rom_test5},
  {"rom_test6",		RSP_TEST_BASE-24+282, rom_test6},
  {"rom_test7",		RSP_TEST_BASE-24+283, rom_test7},
  {"rom_test8",		RSP_TEST_BASE-24+284, rom_test8},  
  {"vsaw",		RSP_TEST_BASE-26+287, vsaw},
  {"sp_recp_mix",	RSP_TEST_BASE-26+288, sp_recp_mix},
  {"sp_recp_neg",	RSP_TEST_BASE-26+289, sp_recp_neg},
  {"sp_recp_pos",	RSP_TEST_BASE-26+290, sp_recp_pos},
  {"sp_sqrt_mix",	RSP_TEST_BASE-26+291, sp_sqrt_mix},
  {"sp_sqrt_neg",	RSP_TEST_BASE-26+292, sp_sqrt_neg},
  {"sp_sqrt_pos",	RSP_TEST_BASE-26+293, sp_sqrt_pos},
  {"sbv1",		RSP_TEST_BASE-26+294, sbv2},
  {"sbv2",		RSP_TEST_BASE-26+295, sbv2},
  {"sbv3",		RSP_TEST_BASE-26+296, sbv3},
  {"sbv4",		RSP_TEST_BASE-26+297, sbv4},
  {"sdv1",		RSP_TEST_BASE-26+298, sdv1},
  {"sdv2",		RSP_TEST_BASE-26+299, sdv2},
  {"sdv3",		RSP_TEST_BASE-26+300, sdv3},
  {"sdv4",		RSP_TEST_BASE-26+301, sdv4},
  {"sfv1",		RSP_TEST_BASE-26+302, sfv1},
  {"sfv2",		RSP_TEST_BASE-26+303, sfv2},
  {"shv1",		RSP_TEST_BASE-26+304, shv1},
  {"shv2",		RSP_TEST_BASE-26+305, shv2},
  {"slv1",		RSP_TEST_BASE-26+306, slv1},
  {"slv2",		RSP_TEST_BASE-26+307, slv2},
  {"slv3",		RSP_TEST_BASE-26+308, slv3},
  {"slv4",		RSP_TEST_BASE-26+309, slv4},
  {"spv1",		RSP_TEST_BASE-26+310, spv1},
  {"spv2",		RSP_TEST_BASE-26+311, spv2},
  {"spv3",		RSP_TEST_BASE-26+312, spv3},
  {"spv4",		RSP_TEST_BASE-26+313, spv4},
  {"sqv1",		RSP_TEST_BASE-26+314, sqv1},
  {"sqv2",		RSP_TEST_BASE-26+315, sqv2},
  {"sqv3",		RSP_TEST_BASE-26+316, sqv3},
  {"sqv4",		RSP_TEST_BASE-26+317, sqv4},
  {"srv1",		RSP_TEST_BASE-26+318, srv1},
  {"srv2",		RSP_TEST_BASE-26+319, srv2},
  {"srv3",		RSP_TEST_BASE-26+320, srv3},
  {"srv4",		RSP_TEST_BASE-26+321, srv4},
  {"ssv1",		RSP_TEST_BASE-26+322, ssv1},
  {"ssv2",		RSP_TEST_BASE-26+323, ssv2},
  {"ssv3",		RSP_TEST_BASE-26+324, ssv3},
  {"ssv4",		RSP_TEST_BASE-26+325, ssv4},
  {"stv1",		RSP_TEST_BASE-26+326, stv1},
  {"suv1",		RSP_TEST_BASE-26+327, suv1},
  {"suv2",		RSP_TEST_BASE-26+328, suv2},
  {"suv3",		RSP_TEST_BASE-26+329, suv3},
  {"suv4",		RSP_TEST_BASE-26+330, suv4},
  {"swv1",		RSP_TEST_BASE-26+331, swv1},
  {"vsub_h",		RSP_TEST_BASE-26+332, vsub_h},
  {"vsub_q",		RSP_TEST_BASE-26+333, vsub_q},
  {"vsub_v",		RSP_TEST_BASE-26+334, vsub_v},
  {"vsub_w",		RSP_TEST_BASE-26+335, vsub_w},
  {"vsubc_h",		RSP_TEST_BASE-34+344, vsubc_h},
  {"vsubc_q",		RSP_TEST_BASE-34+345, vsubc_q},
  {"vsubc_v",		RSP_TEST_BASE-34+346, vsubc_v},
  {"vsubc_w",		RSP_TEST_BASE-34+347, vsubc_w},
  {"vch_v",		RSP_TEST_BASE+314, vch_v},
  {"vcl_v",		RSP_TEST_BASE+315, vcl_v},
  {"vcr_v",		RSP_TEST_BASE+316, vcr_v},
  {"iltest1", 		RSP_TEST_BASE+317+0, iltest1},
  {"iltest2", 		RSP_TEST_BASE+317+1, iltest2},
  {"iltest3", 		RSP_TEST_BASE+317+2, iltest3},
  {"iltest4", 		RSP_TEST_BASE+317+3, iltest4},
  {"iltest5", 		RSP_TEST_BASE+317+4, iltest5},
  {"iltest6", 		RSP_TEST_BASE+317+5, iltest6},
  {"iltest7", 		RSP_TEST_BASE+317+6, iltest7},
  {"iltest8", 		RSP_TEST_BASE+317+7, iltest8},
  {"iltest9", 		RSP_TEST_BASE+317+8, iltest9},
  {"iltest10", 		RSP_TEST_BASE+317+9, iltest10},
  {"iltest11", 		RSP_TEST_BASE+317+10, iltest11},
  {"iltest12", 		RSP_TEST_BASE+317+11, iltest12},
  {"iltest13", 		RSP_TEST_BASE+317+12, iltest13},
  {"iltest14", 		RSP_TEST_BASE+317+13, iltest14},
  {"iltest15", 		RSP_TEST_BASE+317+14, iltest15},
  {"iltest16", 		RSP_TEST_BASE+317+15, iltest16},
  {"iltest17", 		RSP_TEST_BASE+317+16, iltest17},
  {"iltest18", 		RSP_TEST_BASE+317+17, iltest18},
  {"iltest19", 		RSP_TEST_BASE+317+18, iltest19},
  {"iltest20", 		RSP_TEST_BASE+317+19, iltest20},
  {"iltest21", 		RSP_TEST_BASE+317+20, iltest21},
  {"iltest22", 		RSP_TEST_BASE+317+21, iltest22},
  {"iltest23", 		RSP_TEST_BASE+317+22, iltest23},
  {"iltest24", 		RSP_TEST_BASE+317+23, iltest24},
  {"iltest25", 		RSP_TEST_BASE+317+24, iltest25},
  {"di_ctlhz000", 	RSP_TEST_BASE+317+25, di_ctlhz000},
  {"di_ctlhz001", 	RSP_TEST_BASE+317+26, di_ctlhz000},
  {"di_ctlhz002", 	RSP_TEST_BASE+317+27, di_ctlhz002},
  {"di_ctlhz010", 	RSP_TEST_BASE+317+28, di_ctlhz010},
  {"di_ctlhz011", 	RSP_TEST_BASE+317+29, di_ctlhz011},
  {"di_ctlhz012", 	RSP_TEST_BASE+317+30, di_ctlhz012},
  {"di_ctlhz100", 	RSP_TEST_BASE+317+31, di_ctlhz100},
  {"di_ctlhz101", 	RSP_TEST_BASE+317+32, di_ctlhz101},
  {"di_ctlhz102", 	RSP_TEST_BASE+317+33, di_ctlhz102},
  {"di_ctlhz110", 	RSP_TEST_BASE+317+34, di_ctlhz110},
  {"di_ctlhz111", 	RSP_TEST_BASE+317+35, di_ctlhz111},
  {"di_ctlhz112", 	RSP_TEST_BASE+317+36, di_ctlhz112},
  {"di_ldst00", 	RSP_TEST_BASE+317+37, di_ldst00},
  {"di_ldst01", 	RSP_TEST_BASE+317+38, di_ldst01},
  {"di_ldst02", 	RSP_TEST_BASE+317+39, di_ldst02},
  {"di_ldst03", 	RSP_TEST_BASE+317+40, di_ldst03},
  {"di_ldst10", 	RSP_TEST_BASE+317+41, di_ldst10},
  {"di_ldst11", 	RSP_TEST_BASE+317+42, di_ldst11},
  {"di_ldst12", 	RSP_TEST_BASE+317+43, di_ldst12},
  {"di_ldst13", 	RSP_TEST_BASE+317+44, di_ldst13},
  {"di_ldst20", 	RSP_TEST_BASE+317+45, di_ldst20},
  {"di_ldst21", 	RSP_TEST_BASE+317+46, di_ldst21},
  {"di_ldst22", 	RSP_TEST_BASE+317+47, di_ldst22},
  {"di_ldst23", 	RSP_TEST_BASE+317+48, di_ldst23},
  {"di_ldst30", 	RSP_TEST_BASE+317+49, di_ldst30},
  {"di_ldst31", 	RSP_TEST_BASE+317+50, di_ldst31},
  {"di_ldst32", 	RSP_TEST_BASE+317+51, di_ldst32},
  {"di_ldst33", 	RSP_TEST_BASE+317+52, di_ldst33},
  {"di_norm00", 	RSP_TEST_BASE+317+53, di_norm00},
  {"di_norm01", 	RSP_TEST_BASE+317+54, di_norm01},
  {"di_norm02", 	RSP_TEST_BASE+317+55, di_norm02},
  {"di_norm03", 	RSP_TEST_BASE+317+56, di_norm03},
  {"di_norm10", 	RSP_TEST_BASE+317+57, di_norm10},
  {"di_norm11", 	RSP_TEST_BASE+317+58, di_norm11},
  {"di_norm12", 	RSP_TEST_BASE+317+59, di_norm12},
  {"di_norm13", 	RSP_TEST_BASE+317+60, di_norm13},
  {"di_norm20", 	RSP_TEST_BASE+317+61, di_norm20},
  {"di_norm21", 	RSP_TEST_BASE+317+62, di_norm21},
  {"di_norm22", 	RSP_TEST_BASE+317+63, di_norm22},
  {"di_norm23", 	RSP_TEST_BASE+317+64, di_norm23},
  {"di_norm30", 	RSP_TEST_BASE+317+65, di_norm30},
  {"di_norm31", 	RSP_TEST_BASE+317+66, di_norm31},
  {"di_norm32", 	RSP_TEST_BASE+317+67, di_norm32},
  {"di_norm33", 	RSP_TEST_BASE+317+68, di_norm33},
  {"di_reghz0", 	RSP_TEST_BASE+317+69, di_reghz0},
  {"di_reghz1", 	RSP_TEST_BASE+317+70, di_reghz1},
  {"di_reghz2", 	RSP_TEST_BASE+317+71, di_reghz2},
  {"di_reghz3", 	RSP_TEST_BASE+317+72, di_reghz3},
  {"bpmult", 		RSP_TEST_BASE+317+73, bpmult},
  {"bptest0", 		RSP_TEST_BASE+317+74, bptest0},
  {"bptest1", 		RSP_TEST_BASE+317+75, bptest1},
  {"bptest2", 		RSP_TEST_BASE+317+76, bptest2},
  {"bptest3", 		RSP_TEST_BASE+317+77, bptest3},
  {"bptest4", 		RSP_TEST_BASE+317+78, bptest4},
  {"dma00", 	RSP_TEST_BASE+71+325, dma00},
  {"dma01", 	RSP_TEST_BASE+71+326, dma01},
  {"dma02", 	RSP_TEST_BASE+71+327, dma02},
  {"dma10", 	RSP_TEST_BASE+71+328, dma10},
  {"dma11", 	RSP_TEST_BASE+71+329, dma11},
  {"dma12", 	RSP_TEST_BASE+71+330, dma12},
  {"dma13", 	RSP_TEST_BASE+71+331, dma13},
  {"dma14", 	RSP_TEST_BASE+71+332, dma14},
  {"dma20", 	RSP_TEST_BASE+71+333, dma20},
  {"dma21", 	RSP_TEST_BASE+71+334, dma21},
  {"dma22", 	RSP_TEST_BASE+71+335, dma22},
  {"dma30", 	RSP_TEST_BASE+71+336, dma30},
  {"dma31", 	RSP_TEST_BASE+71+337, dma31},
  {"dma32", 	RSP_TEST_BASE+71+338, dma32},
  {"dma33", 	RSP_TEST_BASE+71+339, dma33},
  {"dma34", 	RSP_TEST_BASE+71+340, dma34},
  {"dma35", 	RSP_TEST_BASE+71+341, dma35},
  {"dma36", 	RSP_TEST_BASE+71+342, dma36},
  {"dma40", 	RSP_TEST_BASE+71+343, dma40},
  {"dma50", 	RSP_TEST_BASE+71+344, dma50},
/* wait till these are working
  {"dma60", 	RSP_TEST_BASE+71+345, dma60},
  {"dma70", 	RSP_TEST_BASE+71+346, dma70},
*/
    {"",0,0}
};

/*
 * diagnostic entry point:
 *
 * Each separately invokable ide diagnostic command corresponds to an
 * independent ".c" module; the entry point herein must match
 * the test name as specified in the rspcmd.awk script.  These command
 * names correspond to the names you see from the ide menu.  For this
 * module, there will be an ide command "rsp_other".
 */

static int rsp_Init()
{
    errlog(INFO, "Starting test %s ... ", ideTestName);
    NumFailures = 0;
    dgInitComm();
    return(0);
}

static int rsp_Do(TEST_REF *test_ref)
{
    int rc;

    errlog(INFO,
        "%s: starting subtest %s (%d) ...",
        ideTestName, test_ref->name, test_ref->num);

    /*
     * Invoke the actual test from the "TEST_REF" array statically declared
     * as a global within this test module.
     */
    if (rc = test_ref->fnc(test_ref)) NumFailures++;

    if (rc == 0) errlog(INFO, "--- subtest %s PASSED", test_ref->name);
    else {
      errlog(ERR_SEVERE, "--- subtest %s FAILED", test_ref->name);
    }
    
    return(NumFailures);
}

/*
 * Simple sequential write/read of IMem/DMem with marching 1.
 *** Not to be run if monitor is in IMem/DMem. ***
 */

int
imem_marching_1(void)
{
  int error_count = 0;

  error_count = mem_marching_1(RSP_IMEM_BASE, RSP_IMEM_BASE + IMEM_SIZE - 4);
  return error_count;
}

int
dmem_marching_1(void)
{
  int error_count = 0;

  error_count = mem_marching_1(RSP_DMEM_BASE, RSP_DMEM_BASE + DMEM_SIZE - 4);
  return error_count;
}

int
mem_marching_1(start_addr, end_addr)
  unsigned int start_addr, end_addr;
{
  int error_count = 0;
  int i;
  unsigned int read_data;
  unsigned int write_data;
  int msb;
  
  write_data = 1;
  errlog(DEBUG, "Fill Mem from %08x to %08x with marching 1",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    errlog(DEBUG, "Writing data 0x%08x to Mem[0x%08x]", write_data, i);
    dgWriteWord(i, write_data);
    msb = (write_data == 0x80000000);
    write_data = (write_data << 1) | msb;
  }

  write_data = 1;
  errlog(DEBUG, "Test Mem from %08x to %08x for marching 1",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    dgReadWord(i, &read_data);
    errlog(DEBUG, "Read data 0x%08x from Mem[0x%08x]", read_data, i);
    if (write_data != read_data) {
      errlog(ERR_SEVERE,
             "data miscompare - ad = %08x, wr = %08x, rd = %08x",
             i, write_data, read_data);
      error_count++;
    }
    msb = (write_data == 0x80000000);
    write_data = (write_data << 1) | msb;
  }
  return error_count;
}


int imem_bist(void)
{
   int errcount = 0;
   unsigned read_data;

   /* clear bist status */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_CLEAR);
   errcount += dgRdTestWordMsk(SP_IBIST_REG, 0x00000000, IBIST_REG_MSK);

   /* bist_check 1 */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_CHECK);
   while (!(errcount += dgReadWord(SP_IBIST_REG, &read_data)))
   {
     if (read_data & SP_IBIST_DONE) break;
   }
   errcount += dgRdTestWordMsk(SP_IBIST_REG, (SP_IBIST_FAILED | SP_IBIST_DONE | SP_IBIST_CHECK), 
			       IBIST_REG_MSK);

   /* clear bist, bist_check 0 */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_CLEAR);
   while (!(errcount += dgReadWord(SP_IBIST_REG, &read_data)))
   {
     if (read_data & SP_IBIST_DONE) break;
   }
   errcount += dgRdTestWordMsk(SP_IBIST_REG, (SP_IBIST_FAILED | SP_IBIST_DONE), IBIST_REG_MSK);

   /* clear bist status */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_CLEAR);
   errcount += dgRdTestWordMsk(SP_IBIST_REG, 0x00000000, IBIST_REG_MSK);

   /* bist_go */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_GO);
   while (!(errcount += dgReadWord(SP_IBIST_REG, &read_data)))
   {
     if (read_data & SP_IBIST_DONE) break;
   }
   errcount += dgRdTestWordMsk(SP_IBIST_REG, (SP_IBIST_DONE | SP_IBIST_GO), IBIST_REG_MSK);

   /* clear bist status */
   errcount += dgWriteWord(SP_IBIST_REG, SP_IBIST_CLEAR);
   errcount += dgRdTestWordMsk(SP_IBIST_REG, 0x00000000, IBIST_REG_MSK);

   if (errcount)
      errlog(ERR_SEVERE, "IMem BIST errcount = %d", errcount);

   return(errcount);
}

/*
 * Simple sequential write/read of IMem/DMem with "aaa..." and "555" pattern.
 *** Not to be run if monitor is in IMem/DMem. ***
 */

int
imem_pattern(void)
{
  int error_count = 0;

  error_count = mem_pattern(RSP_IMEM_BASE, RSP_IMEM_BASE + IMEM_SIZE - 4);
  return error_count;
}

int
dmem_pattern(void)
{
  int error_count = 0;

  error_count = mem_pattern(RSP_DMEM_BASE, RSP_DMEM_BASE + DMEM_SIZE - 4);
  return error_count;
}

int
mem_pattern(start_addr, end_addr)
  unsigned int start_addr, end_addr;
{
  int error_count = 0;
  int i;
  unsigned int read_data;
  unsigned int write_data;
  int msb;
  
  write_data = 0xaaaaaaaa;
  errlog(DEBUG, "Fill Mem from %08x to %08x with 0xaaa...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    errlog(DEBUG, "Writing data 0x%08x to Mem[0x%08x]", write_data, i);
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test Mem from %08x to %08x for 0xaaa...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    dgReadWord(i, &read_data);
    errlog(DEBUG, "Read data 0x%08x from Mem[0x%08x]", read_data, i);
    if (write_data != read_data) {
      errlog(ERR_SEVERE, 
             "data miscompare - ad = %08x, wr = %08x, rd = %08x",
             i, write_data, read_data);
      error_count++;
    }
  }

  write_data = 0x55555555;
  errlog(DEBUG, "Fill Mem from %08x to %08x with 0x555...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    errlog(DEBUG, "Writing data 0x%08x to Mem[0x%08x]", write_data, i);
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test Mem from %08x to %08x for 0x555...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    dgReadWord(i, &read_data);
    errlog(DEBUG, "Read data 0x%08x from Mem[0x%08x]", read_data, i);
    if (write_data != read_data) {
      errlog(ERR_SEVERE, 
             "data miscompare - ad = %08x, wr = %08x, rd = %08x",
             i, write_data, read_data);
      error_count++;
    }
  }
  
  write_data = 0xaaaaaaaa;
  errlog(DEBUG, "Fill Mem from %08x to %08x with 0xaaa...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    errlog(DEBUG, "Writing data 0x%08x to Mem[0x%08x]", write_data, i);
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test Mem from %08x to %08x for 0xaaa...",
         start_addr, end_addr);
  for (i = start_addr; i < end_addr; i += 4) {
    dgReadWord(i, &read_data);
    errlog(DEBUG, "Read data 0x%08x from Mem[0x%08x]", read_data, i);
    if (write_data != read_data) {
      errlog(ERR_SEVERE, 
             "data miscompare - ad = %08x, wr = %08x, rd = %08x",
             i, write_data, read_data);
      error_count++;
    }
  }

  return error_count;
}


int
pc_r_w()
{
  int error_count = 0;
  int i;
  unsigned int read_data;
  unsigned int write_data;
  
  write_data = 0x4;
  for (i = 2; i < 12; i ++) {
    dgWriteWord(SP_PC_REG, write_data);
    dgReadWord(SP_PC_REG, &read_data);
    errlog(DEBUG, "Read data 0x%08x from PC", read_data);
    if (write_data != read_data) {
      errlog(ERR_SEVERE, 
             "PC data miscompare - wr = %08x, rd = %08x",
             write_data, read_data);
      error_count++;
    }
    write_data = write_data << 1;
  }
  return error_count;
}

int rsp(void) {rsp_regr(TestRefs);}