/*************************************************************************
 *
 *  File: iotestcmd.c
 *
 *  This file contains the main test command table.
 *
 *  $Header: /root/leakn64/depot/rf/sw/bbplayer/iosim/src/iotestcmd.c,v 1.41 2003/01/31 03:03:13 whs Exp $
 *
 */

#include <stdio.h>
#include "trace.h"
#include "bcp.h"
#include "iomap.h"
#include "iotest.h"
#include "bcptest.h"
#include "bcp_util.h"
#include "simipc.h"
#include "bcp_usb.h"
#include "bcptestsi.h"
#include "bcp_rand_tests.h"

/***********************************************************************
 * Global definitions
 */
int	errorTotal = 0;
int	errorCount = 0;


/***********************************************************************
 * Global variables
 */

/*
 * Test Command Table
 *	- This is the main command table where each test/task from the
 *	  input file gets executed.
 */
int test_bcp_time(int a1, int a2, int a3, int a4)
{
	unsigned long long tt;
	unsigned int d1, d2;
	
	SIM_TIME(&tt);
    d1 = (unsigned int)((tt >> 32) & 0xffffffff);
	d2 = (unsigned int)(tt & 0xffffffff);
    printf("Sim time= %u %u %x %x \n", d1, d2, d1, d2);

	return 1;
}

TstCmd	TstCmdTbl[] = {
   /*
    *  Test  Description		Routine		RoutineName 
    *   ID   
    *  ===================================================================
    */

    {   0,   "Config RDRAM",		rdramConfig,	"rdramConfig" },
    {   1,   "Config PI Domain 1",	piConfigDom1,	"piConfigDom1" },
    {   2,   "Config PI Domain 2",	piConfigDom2,	"piConfigDom2" },
    {   3,   "Config AI",		AiTestInit,	"AiTestInit" },
    
    {   5,   "W/R RDRAM (1B)",		rdramTestSglRw,	"rdramTestSglRw" },
    {   6,   "W/R RDRAM (2B)",		rdramTestSglRw,	"rdramTestSglRw" },
    {   7,   "W/R RDRAM (3B)",		rdramTestSglRw,	"rdramTestSglRw" },
    {   8,   "W/R RDRAM (4B)",		rdramTestSglRw,	"rdramTestSglRw" },
    
    {   9,   "W/R RDRAM (2-word)",	rdramTestBlkRw,	"rdramTestBlkRw" },
    {  10,   "W/R RDRAM (4-word)",	rdramTestBlkRw,	"rdramTestBlkRw" },
    {  11,   "W/R RDRAM (8-word)",	rdramTestBlkRw,	"rdramTestBlkRw" },
    
    {  12,   "W/R RDRAM (4B) to pages",	rdramTestPgRw,	"rdramTestPgRw" },
    {  13,   "Init RDRAM",		rdramInit,	"rdramInit" },
    {  14,   "Cpu Wait",		CpuWait,	"CpuWait" },
    {  15,    "Ebus R/W to pages",	EbusTestPgRw,	"EbusTestPgRw" },
    
    {  20,   "W/R PI Reg",		PiTestReg,	"PiTestReg" },
    {  21,   "PI IO Read",		PiTestIoRead,	"PiTestIoRead" },
    {  22,   "PI IO Write",		PiTestIoWrite,	"PiTestIoWrite" },
    {  23,   "PI DMA",			PiTestDma,	"PiTestDma" },
    {  24,   "PI IO Dump",		MemDump,	"MemDump" },
    {  25,   "PI Compare",		MemCompare,	"MemCompare" },
    {  26,   "PI Status",		PiTestStatus,	"PiTestStatus" },
    {  27,   "PI DMA Pages",		PiTestDmaPg,	"PiTestDmaPg" },

    /* N64 Legacy SI tests */
    {  30,   "W/R SI Reg",		SiTestReg,	"SiTestReg" },
    {  31,   "SI IO Read",		SiTestIoRead,	"SiTestIoRead" },
    {  32,   "SI IO Write",		SiTestIoWrite,	"SiTestIoWrite" },
    {  33,   "SI DMA",			SiTestDma,	"SiTestDma" },
    {  34,   "SI Dump",			MemDump,	"MemDump" },
    {  35,   "SI Compare",		MemCompare,	"MemCompare" },
    {  36,   "SI Status",		SiTestStatus,	"SiTestStatus" },
    {  37,   "SI DMA Pages",		SiTestDmaPg,	"SiTestDmaPg" },

    {  40,   "W/R AI Reg",		AiTestReg,	"AiTestReg" },
    {  43,   "AI DMA",			AiTestDma,	"AiTestDma" },
    {  45,   "AI Compare",		AiCompareData,	"AiCompareData" },
    {  46,   "AI Status",		AiTestStatus,	"AiTestStatus" },
    {  47,   "AI DMA Pages",		AiTestDmaPg,	"AiTestDmaPg" },
    {  48,   "AI Start DMA",		AiStartDma,"AiStartDma" },
    {  49,   "AI Length Decrement",	AiCompareLength,"AiCompareLength" },


    
    /* 50 is reserved for VI */

    {  60,   "W/R SP Reg",		SpTestReg,	"SpTestReg" },
    {  61,   "SP IO Read",		SpTestIoRead,	"SpTestIoRead" },
    {  62,   "SP IO Write",		SpTestIoWrite,	"SpTestIoWrite" },
    {  63,   "SP DMA",			SpTestDma,	"SpTestDma" },
    {  64,   "SP IO Dump",		MemDump,	"MemDump" },
    {  65,   "SP Compare",		MemCompare,	"MemCompare" },
    {  66,   "SP Status",		SpTestStatus,	"SpTestStatus" },
    {  67,   "SP DMA Pages",		SpTestDmaPg,	"SpTestDmaPg" },
    
    /* 70 is reserved for DP CMD */
    {  70,    "RDP List", 		RDPList, 	"RDPList" },
    {  71,    "RDP List Loop", 		RDPListLoop, 	"RDPListLoop" },
    {  72,    "RDP List Counter",       RDPListCounter, "RDPListCounter"},
    
    /* 80 is reserved for DP SPAN */

    { 100,    "Mem Read", 		MemRead, 	"MemRead" },
    { 101,    "Mem Read-Compare", 	MemReadCompare, "MemReadCompare" },
    { 102,    "Mem Write", 		MemWrite,	"MemWrite" },
    { 103,    "Mem Write-Read",		MemWriteRead,	"MemWriteRead" },
    { 104,    "Mem Poll Status", 	MemPollStatus,	"MemPollStatus" },
    { 105,    "Mem Compare",		MemCompare,	"MemCompare" },
    { 106,    "Mem Dump",		MemDump,	"MemDump" },
    { 107,    "Mem Read-Until",		MemReadUntil,	"MemReadUntil" },
    { 108,    "Mem Read-Compare-Masked",MemReadCompMask,"MemReadCompMask" },
    { 109,    "Mem Read-Write",         MemReadWrite,   "MemReadWrite" },
    { 110,    "Mem Read-Write Mask",    MemReadWriteMask,"MemReadWriteMask" },

    /* 200~299 Special BCP setup function */
    { 200,    "Init BCP DDR",              InitDDR,        "InitDDR"},
    { 201,    "BCP simulator time",        test_bcp_time,  "bcp_time"},
    { 202,    "BCP register test",         register_test,  "register_test"},
    { 203,    "BCP sram test",         sram_test,  "sram_test"},
    { 210,    "Extented Read and compare", ExtMemReadComp, "ExtMemReadComp"},
    { 211,    "Extented Write", 		   ExtMemWrite,    "ExtMemWrite"},
    { 212,    "Extented Read and mask compare", ExtMemReadMaskComp, "ExtMemReadMaskComp"},
    { 216,    "Extented Read/write(per bit)test",  rwExtReadComp, "rwExtReadComp"},
    { 230,    "BCP single walk",  		   regMemSglWalk,  "regMemSglWalk"},
    { 231,    "xz BCP single walk",  	   ExtMemSglWalk,  "ExtMemSglWalk"},
    { 232,    "BCP block walk",  		   regMemBlkWalk,  "regMemBlkWalk"},
    { 233,    "xz BCP block walk",  	   ExtMemBlkWalk,  "ExtMemBlkWalk"},

    /* 300~399 BCP RI test */
    { 300,    "Backdoor DDR Read",          BDMemReadComp,    "BDMemReadComp"},
    { 301,	  "Backdoor DDR Write",         BDMemWrite,       "BDMemWrite"},
    { 302,	  "Bdoor rd and mask compare",  BDMemReadMaskComp,"BDMemReadMaskComp"},
	
    { 312,    "BD DDR Read test", 			BDMemReadTest,    "BDMemReadTest"},
	{ 313,    "BD DDR Write test", 			BDMemWriteTest,   "BDMemWriteTest"},     
	
        /* memory walk but checked by memory backdoor */
	{ 330,    "BD BCP single walk",         BDregMemSglWalk,  "BDregMemSglWalk"},
    { 331,    "BD xz BCP single walk",      BDExtMemSglWalk,  "BDExtMemSglWalk"},
    { 332,    "BD BCP block walk",          BDregMemBlkWalk,  "BDregMemBlkWalk"},
    { 333,    "BD xz BCP block walk",       BDExtMemBlkWalk,  "BDExtMemBlkWalk"},
    { 350,    "BCP_RI_RAND",      			bcp_ri_rand,  "bcp_ri_rand"},

	/* 400~410 BCP RSP CTRACE test */
	{400,	  "BCP RSP CTRACE ONE PASS",    RspCtraceRun, 		  "RspCtraceRun" },
	{401,     "BCP RSP CTRACE SINGLE STEP", RspCtraceSingle,      "RspCtraceSingle"}, 

	/* 420 SI backdoor */
	{420,	"BCP SI BDoor", bd_si_ctrl_setup, "bd_si_ctrl_setup"},

	/* 500 -- 520 USB test */
	{500,   "USB reg read", usb_read_reg_test, "usb_read_reg_test"},
	{501,   "USB reg write", usb_reg_write_test, "usb_reg_write_test"},
	{502,   "USB BDT test", usb_bdt_sram, "usb_bdt_sram"},	

	{510,   "USB reset reg value", usb_reset_test , "USB reset reg value"},
	{511,   "USB register read/write", usb_reg_rw, "USB reg r/w"},
	{512,   "USB device test", usb_device_test, "USB device test"},
	{513,   "USB line test",  usb_line_state_test, "USB Linestate"},
	{514,   "USB otg test", usb_otg_test, "USB OTG"},
	{515,   "USB host echo", usb_simple_host_echo, "USB HOST ECHO"},
	{516,   "USB hosts test", hosts_test, "USB HOSTS TEST"}, 
	{517,   "USB hosts single test", hosts_one_test, "USB HOSTS TEST"}, 

    /* 600 -- 649 BCP SI test */
    {600,   "SI run set of tests",			SiRunTests,				"SiRunTests" },
    {601,   "SI valid Ctrlr Cmds",			SiTestValidCtrlCmds,	"SiTestValidCtrlCmds" },
    {602,   "SI invalid Ctrlr Cmds",		SiTestInvalidCtrlrCmds,	"SiTestInvalidCtrlrCmds" },
    {603,   "SI force Ctrlr error via BD",	SiTestCtrlrErrViaBD,	"SiTestCtrlrErrViaBD" },
    {604,   "SI DMA busy error",			SiTestDmaBusyError,		"SiTestDmaBusyError" },
    {605,   "SI LC single command dectect",	SiTestSingleCmdDetection,"SiTestSingleCmdDetection" },
    {606,   "SI JChannel reset(JCRST)",		SiTestJChannelReset,	"SiTestJChannelReset" },
    {607,   "SI DMA from/to specific addr",	SiTestDmaSpecificAddrs,	"SiTestDmaSpecificAddrs" },
    {608,   "SI DMA from/to walk bits",		SiTestDmaWalkBits,		"SiTestDmaWalkBits" },
    {609,   "SI DMA with random params",	SiTestRandom,			"SiTestRandom" },
    {610,   "SI LC joystick reset ref",		SiTestLCtrlJSRST,		"SiTestLCtrlJSRST" },
    {611,   "SI LC button sample rate",		SiTestLCtrlButRate,		"SiTestLCtrlButRate" },
    {612,   "SI LC joystick x,y",			SiTestLCtrlJsxy,		"SiTestLCtrlJsxy" },

    {700,   "Write a single line luma ramp",	write_luma_ramp,		"write_luma_ramp"},
    {701,   "Write a single line of color bars",write_color_bar,		"write_color_bar"},

	/* 800 -- 900 for BCP random test */
	{800, "BCP RI SINGLE r/w",   bcp_ri_single_rw, "bcp_ri_single_rw"},
	{810, "BCP AI DMA",   bcp_ai_dma, "bcp_ai_dma"},
	{820, "BCP SI tests in random env",   SiTestRandEnv,   "SiTestRandEnv" },

	{840, "BCP SP PIO",   bcp_sp_rand_pio, "bcp_sp_rand_pio"},
	{841, "BCP SP DMA",   bcp_sp_rand_dma, "bcp_sp_rand_dma"},

	{830, "BCP UI SETUP", hosts_setup, "hosts_setup"},
	{831, "BCP UI PIO",   bcp_ui_rand_pio, "bcp_ui_rand_pio"},
	{832, "BCP UI TRANSACTION", bcp_ui_rand_trans, "bcp_ui_rand_trans"},

	{900, "BCP CLEAR STAT", bcp_unit_clear_stat, "bcp_unit_clear_stat"},
	{901, "BCP DISPLAY STAT", bcp_unit_disp_stat, "bcp_unit_disp_stat"},
	{902, "BCP CHECK Bits 9", bcp_check_9th, "bcp_check_9th"},
};


/***********************************************************************
 * Routines
 */
int
rdramConfig(int rdram1, int size, int a3, int a4)
{
	if (size == 0) {
		size = (rdram1) ? 4 : 2;
	}
	RdramInit(size);
	return(1);
}

int 
InitDDR(int a1, int a2, int a3, int a4)
{
    unsigned int sysclk_period, memclk;
    int refcnt = 0x1e0;
    int trdel, twdel, tras, trp, trcdr, trfc, tcl, tcl_b;
	int mem_info;

    bcp_sysclk_period(&sysclk_period);
	mem_info = BCP_MEM_INFO;
	
    if (sysclk_period > 16000 || sysclk_period < 10000) {
	_TRACE(DERROR, fprintf(LogFp, "System clk wrong"));
	sysclk_period=16000;
    }
    memclk = 2000000 / sysclk_period;

    trdel = 3;
    twdel = 1;
    tras = (memclk >= 150)?1:0;
    trp = (memclk > 150)?1:0;
    trcdr = (memclk > 150)?1:0;
    trfc = (memclk > 150)?0xE:0xC;

	if ((mem_info & BCP_MEM_DDR_MASK) == 0x1000) { /* 16 bits */ 
		trfc = 0xf;
		trcdr = (memclk >= 160)?1:0;
		trp = (memclk >= 160)?1:0;
		tcl = (memclk >= 160) ? 6 : 2;
		tcl_b = tcl;
	} else {
		tcl = 3;
		tcl_b = 4;
	}
    
#if 0
    IO_WRITE(0x04700020, 0x80000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x00002002);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x0000013a);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x80000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x40000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700030, 0x00001000 | refcnt);
    //IO_WRITE(0x04700030, 0x00000000);
    IO_READ(0x04700030);

    //IO_WRITE(0x04700040, 0x0006000fa);
    IO_WRITE(0x04700040, 0x001111e3);

    IO_READ(0x04700030);
    IO_READ(0x04700030);
#else
    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_PRECHARGE_ALL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_EX|RI_NMODE_EX_DRIVE_STR_HALF);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_MX_BURST_ILV|
			   RI_NMODE_MX_BURST_LEN_4|
			   RI_NMODE_MX_CL(tcl)|
			   RI_NMODE_MX_RESET_DLL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_PRECHARGE_ALL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_AUTO_REFRESH);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NREFRESH_REG, RI_NREFRESH_ENABLE | refcnt);
    IO_READ(RI_NREFRESH_REG);

    IO_WRITE(RI_DDR_CONFIG_REG, (trdel<<RI_DDR_CONFIG_TRDEL_SHIFT)|
				(twdel<<RI_DDR_CONFIG_TWDEL_SHIFT)|
				(tras<<RI_DDR_CONFIG_TRAS_SHIFT)|
				(trp<<RI_DDR_CONFIG_TRP_SHIFT)|
				(trcdr<<RI_DDR_CONFIG_TRCD_SHIFT)|
				(trfc<<RI_DDR_CONFIG_TRFC_SHIFT)|
				(tcl_b<<RI_DDR_CONFIG_TCL_SHIFT));

    IO_READ(RI_NREFRESH_REG);
    IO_READ(RI_NREFRESH_REG);
	
	if ((mem_info & BCP_MEM_DDR_MASK) == 0x1000) /* 16 bits */
		IO_WRITE(RI_XMEM_REG, 1);
	else {
		IO_WRITE(RI_STROBE_REV_REG, 1);
		IO_WRITE(RI_AUTO_PRE_CHG_REG, 1);
	}
#endif

    cpuWait(100);
}

int 
InitDDRBypass(int tcl0, int tcl1, int a3, int a4)
{
    unsigned int sysclk_period, memclk;
    int refcnt = 0x1e0;
    int trdel, twdel, tras, trp, trcdr, trfc, tcl;
	int mem_info;

    bcp_sysclk_period(&sysclk_period);
	mem_info = BCP_MEM_INFO;
	
    if (sysclk_period > 16000 || sysclk_period < 10000) {
	_TRACE(DERROR, fprintf(LogFp, "System clk wrong"));
	sysclk_period=16000;
    }
    memclk = 2000000 / sysclk_period;

    trdel = 3;
    twdel = 1;
    tras = (memclk >= 150)?1:0;
    trp = (memclk > 150)?1:0;
    trcdr = (memclk > 150)?1:0;
    trfc = (memclk > 150)?0xE:0xC;
    
	if ((mem_info & BCP_MEM_DDR_MASK) == 0x1000) { /* 16 bits */ 
		trfc = 0xf;
		trcdr = (memclk >= 160)?1:0;
		trp = (memclk >= 160)?1:0;
		tcl = (memclk >= 160) ? 6 : 2;
	} else tcl = 3;

#if 0
    IO_WRITE(0x04700020, 0x80000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x00002002);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x0000013a);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x80000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700020, 0x40000000);
    IO_READ(0x04700020);

    IO_WRITE(0x04700030, 0x00001000 | refcnt);
    //IO_WRITE(0x04700030, 0x00000000);
    IO_READ(0x04700030);

    //IO_WRITE(0x04700040, 0x0006000fa);
    IO_WRITE(0x04700040, 0x001111e3);

    IO_READ(0x04700030);
    IO_READ(0x04700030);
#else
    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_PRECHARGE_ALL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_EX|RI_NMODE_EX_DRIVE_STR_HALF);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_MX_BURST_ILV|
			   RI_NMODE_MX_BURST_LEN_4|
			   RI_NMODE_MX_CL(tcl0)|
			   RI_NMODE_MX_RESET_DLL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_PRECHARGE_ALL);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NMODE_REG, RI_NMODE_CMD_AUTO_REFRESH);
    IO_READ(RI_NMODE_REG);

    IO_WRITE(RI_NREFRESH_REG, RI_NREFRESH_ENABLE | refcnt);
    IO_READ(RI_NREFRESH_REG);

    IO_WRITE(RI_DDR_CONFIG_REG, (trdel<<RI_DDR_CONFIG_TRDEL_SHIFT)|
				(twdel<<RI_DDR_CONFIG_TWDEL_SHIFT)|
				(tras<<RI_DDR_CONFIG_TRAS_SHIFT)|
				(trp<<RI_DDR_CONFIG_TRP_SHIFT)|
				(trcdr<<RI_DDR_CONFIG_TRCD_SHIFT)|
				(trfc<<RI_DDR_CONFIG_TRFC_SHIFT)|
				(tcl1<<RI_DDR_CONFIG_TCL_SHIFT));

    IO_READ(RI_NREFRESH_REG);
    IO_READ(RI_NREFRESH_REG);
	
	if ((mem_info & BCP_MEM_DDR_MASK) == 0x1000) /* 16 bits */
		IO_WRITE(RI_XMEM_REG, 1);
	else {
		IO_WRITE(RI_STROBE_REV_REG, 0);
		//IO_WRITE(RI_AUTO_PRE_CHG_REG, 1);
	}
#endif

    cpuWait(120);
}

int
piConfigDom1(int lat, int pwd, int pgs, int rls)
{
	_TRACE(DLOG, printf(
		"\tPI Config Dom1: lat=%x, pwd=%x, pgs=%x, rls=%x\n",
		lat, pwd, pgs, rls));

	PiConfigDomain(PI_DOMAIN1_REG, lat, pwd, pgs, rls);

	return(1);
}

int
piConfigDom2(int lat, int pwd, int pgs, int rls)
{
	_TRACE(DLOG, printf(
		"\tPI Config Dom2: lat=%x, pwd=%x, pgs=%x, rls=%x\n",
		lat, pwd, pgs, rls));

	PiConfigDomain(PI_DOMAIN2_REG, lat, pwd, pgs, rls);

	return(1);
}


/*
 * Stub routine to delay CPU clock cycles
 */
int
CpuWait(int count, int a2, int a3, int a4)
{
	int i;

	/* This generates a 4 clock delay in verilog model */
	/* for (i = 0; i < count; i++)
		IO_WRITE(MI_NOOP_REG, 0); */
	BCP_STALL(count*4);

	return(1);
}