bcp_rdp2MB.tst
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//*********************************************************
//
// rdp iosim test
//********************************************************
//Init DDR first
k 1
//D Init DDR first
//t 0200 00000000 00000000 00000000 0000000
#t 0070 00000000 00000000 00000000 00000000
//********************************************************
// Load rdram images
D Load rdram images tmp.iosim.rdram
dr 2 tmp.iosim.rdram
// Do a mem dump to make sure rdram was loaded correctly
t 0106 00001000 00000002 00000000 00000000
t 0106 00001555 00000002 00000000 00000000
t 0106 00001aaa 00000002 00000000 00000000
t 0106 00001fff 00000002 00000000 00000000
// Read VI_CTRL, make sure is zeroed out
t 0101 04400000 00000000 00000000 00000000
// Write-Read VI_ORIGIN
t 0103 04400004 00001080 00001080 00000000
// Write-Read VI_WIDTH
t 0103 04400008 00000020 00000020 00000000
// Write-Read VI_V_INT
t 0103 0440000c 000003ff 000003ff 00000000
// Write-Read VI_BURST
t 0103 04400014 00820404 00820404 00000000
// Write-Read VI_V_SYNC
t 0103 04400018 0000002A 0000002A 00000000
// Write-Read VI_H_SYNC
t 0103 0440001c 00000110 00000110 00000000
// Write-Read VI_LEAP
t 0103 04400020 01100110 01100110 00000000
// Write-Read VI_H_START
t 0103 04400024 00200044 00200044 00000000
// Write-Read VI_V_START
t 0103 04400028 00050025 00050025 00000000
// Write-Read VI_V_BURST
t 0103 0440002c 00050025 00050025 00000000
// Write-Read VI_X_SCALE
t 0103 04400030 00000200 00000200 00000000
// Write-Read VI_Y_SCALE
t 0103 04400034 01000400 01000400 00000000
// Write-Read VI_CTRL
t 0103 04400000 00000053 00000053 00000000
// Write VI_V_CURRENT
t 0102 04400010 00000000 00000000 00000000
// Read VI_V_CURRENT
t 0100 04400010 00000000 00000000 00000000
// Loop until we hit line number
t 0107 04400010 ffffffff 00000028 00000000
// Write-Read VI_Y_SCALE
t 0103 04400034 03000400 03000400 00000000
// Write-Read VI_V_START
t 0103 04400028 00070027 00070027 00000000
// Write-Read VI_V_BURST
t 0103 0440002c 00070027 00070027 00000000
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// DMA 20 Bytes (RDRAM -> AI) (8 byte aligned address & data)
// do as many of these as needed to introduce stalls
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
// Run DP list
D Start to run DP list
t 0070 00000000 00000000 00000000 00000000
//*******************************************************
// Dump ddr into rdram images
D Dump rdram image into
dw 2 tmp.iosim.rdram
k 0
//q