bootu.s
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#include <regdef.h>
#include <asm.h>
#include <PR/R4300.h>
#include <PR/bcp.h>
#include "boot.h"
// XXX: t7 is reserved for use in TRACE macros, do not use.
.text
.align 2
.set noreorder
.globl __start
__start:
# write config register
mfc0 t1, C0_CONFIG
and t1, t1, ~CONFIG_K0
and t1, t1, ~CONFIG_CU
mtc0 t1, C0_CONFIG
# other initialization
mtc0 zero, C0_INX
mtc0 zero, C0_ENTRYHI
mtc0 zero, C0_ENTRYLO0
mtc0 zero, C0_ENTRYLO1
mtc0 zero, C0_PAGEMASK
mtc0 zero, C0_LLADDR
# two lines below now done in entry.s
# mtc0 zero, C0_WATCHLO
# mtc0 zero, C0_WATCHHI
mtc0 zero, C0_CAUSE
mtc0 zero, C0_COUNT
mtc0 zero, C0_COMPARE
li t0, (SR_CU0 | SR_CU1 | SR_FR | SR_BEV)
mtc0 t0, C0_SR
nop
// XXX: maximum sysclk*mult is 150 MHz. This is
// not being checked here.
# check div mode and set if needed
li t0, PHYS_TO_K1(MI_CTRL_REG)
lw t1, 0(t0)
move t4, t1 # save MI_CTRL_REG
TRACE_REG(t1)
li t2, PHYS_TO_K1(PI_GPIO_REG)
lw t3, 0(t2)
TRACE_REG(t3)
and t1, MI_CTRL_DIV_MODE_MASK
srl t1, MI_CTRL_DIV_MODE_SHIFT
and t3, PI_ID_CLOCK_MULT_MASK
srl t3, PI_ID_CLOCK_MULT_SHIFT
beq t1, t3, 1f
nop
# must set div mode and reset
or t4, MI_CTRL_HARD_RESET
sll t3, MI_CTRL_DIV_MODE_SHIFT
or t4, t3
TRACE_VAL(0x20)
TRACE_REG(t4)
sw t4, 0(t0)
nop
1:
TRACE_VAL(0x24)
# Invalidate I cache
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
la t0,K0BASE
addu t1,t0,ICACHE_SIZE
subu t1,8*ICACHE_LINESIZE
init_icache:
cache CACH_PI|C_IST,0(t0)
cache CACH_PI|C_IST,ICACHE_LINESIZE(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*2)(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*3)(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*4)(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*5)(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*6)(t0)
cache CACH_PI|C_IST,(ICACHE_LINESIZE*7)(t0)
bltu t0,t1,init_icache # on entire cache
addu t0,(8*ICACHE_LINESIZE)
# indicate progress
TRACE_VAL(0x26)
# Invalidate D cache
la t0,K0BASE
addu t1,t0,DCACHE_SIZE
subu t1,8*DCACHE_LINESIZE
init_dcache:
cache CACH_PD|C_IST,0(t0)
cache CACH_PD|C_IST,DCACHE_LINESIZE(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*2)(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*3)(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*4)(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*5)(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*6)(t0)
cache CACH_PD|C_IST,(DCACHE_LINESIZE*7)(t0)
bltu t0,t1,init_dcache # on entire cache.
addu t0,(8*DCACHE_LINESIZE)
# setup stack pointer and gp
li sp, PHYS_TO_K0(INTERNAL_RAM_END-16)
la gp, _gp
# setup jump to cached space
la t0, __start_cached
and t0, t0, 0xdfffffff
# debug output
TRACE_REG(t0)
# jump to cached space
j t0
nop