#include <os_bb.h>
#include <osint.h>
#include <bbint.h>
#include <bcp.h>
#include <arcusb.h>
#include "host.h"
#include "device.h"
#include <assert.h>

/*
 * Pointers to state structures required by ARC API code
 */
_usb_host_handle		__osArcHostHandle[OS_USB_MAX_CONTROLLERS];
static _usb_device_handle	__osArcDeviceHandle[OS_USB_MAX_CONTROLLERS];

/*
 * State structure per controller
 */
_usb_ctlr_state_t _usb_ctlr_state[OS_USB_MAX_CONTROLLERS] = {
	{ UCS_MODE_IDLE, UCS_MODE_HOST|UCS_MODE_DEVICE },
	{ UCS_MODE_IDLE, UCS_MODE_HOST|UCS_MODE_DEVICE }
};

static void __usbDeviceMode(s32);
static void __usbHostMode(s32);
static void __usbOtgStateChange(s32);

/*
 * Routines that access the BCP USB Interface (UI)
 */

/*
 * Interrupt masking for mutual exclusion.
 *
 * These routines need to be nestable since the ARC
 * code nests them.
 */
static OSIntMask save_im;
static int save_im_level = 0;

void
__usb_splhigh(void)
{
	OSIntMask im;

	/* heavy handed for now */
	im = __osDisableInt();
	if (save_im_level++ == 0)
		save_im = im;
}

void
__usb_splx(void)
{
	if (--save_im_level == 0)
		(void)__osRestoreInt(save_im);
}

/*
 * Handle Device Interrupt
 */
s32
__usbDevInterrupt(s32 which)
{
extern void _usb_host_state_machine(_usb_host_handle);
extern void _usb_device_state_machine(_usb_device_handle);
	u32 val, mask;

	/*
	 * Check OTG interrupts
	 */
	val = IO_READ(USB_REG_ADDR(which, USB0_OTG_INT_STAT_REG));
	mask = IO_READ(USB_REG_ADDR(which, USB0_OTG_INT_EN_REG));
        val &= mask;
	if (val != 0) {
		if ((val & OTG_INT_STATUS_A_VBUS) != 0) {
			PRINTF("OTG_INT: A_VBUS\n");
			__usbOtgStateChange(which);
		}
		if ((val & OTG_INT_STATUS_B_SESS) != 0) {
			PRINTF("OTG_INT: B_SESS\n");
			__usbOtgStateChange(which);
		}
		if ((val & OTG_INT_STATUS_SESS_VLD) != 0) {
			PRINTF("OTG_INT: SESS_VLD\n");
			__usbOtgStateChange(which);
		}
		if ((val & OTG_INT_STATUS_LINE_STATE_CHANGE) != 0) {
			PRINTF("OTG_INT: LINE_STATE_CHANGE\n");
			__usbOtgStateChange(which);
		}
		if ((val & OTG_INT_STATUS_1_MSEC) != 0) {
			static int msec_count = 0;
			PRINTF("OTG_INT: 1_MSEC\n");
			/* after the first few, disable them XXX */
			if (++msec_count > 4)
				IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_EN_REG), 0xae);
		}
		if ((val & OTG_INT_STATUS_ID) != 0) {
			PRINTF("OTG_INT: ID_CHG\n");
			__usbOtgStateChange(which);
		}
		/* Clear the interrupts in HW */
		IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_STAT_REG), val);
	}

	/*
	 * Now process normal host and device interrupts
	 */
	val = IO_READ(USB_REG_ADDR(which, USB0_INT_STAT_REG));
	mask = IO_READ(USB_REG_ADDR(which, USB0_INT_ENB_REG));
        val &= mask;
	if (_usb_ctlr_state[which].ucs_mode == UCS_MODE_HOST) {
#ifdef USB_HOST
		_usb_hci_vusb11_isr(__osArcHostHandle[which]);
		_usb_host_state_machine(__osArcHostHandle[which]);
#endif /* USB_HOST */
	} else if (_usb_ctlr_state[which].ucs_mode == UCS_MODE_DEVICE) {
		_usb_dci_vusb11_isr(__osArcDeviceHandle[which]);
		//_usb_device_state_machine(__osArcDeviceHandle[which]);
	}

	/*
	 * After interrupts have been handled, unmask the MI EINTR level
	 */
	IO_WRITE(MI_INTR_EMASK_REG, 
		(which ? MI_INTR_MASK_SET_USB1 : MI_INTR_MASK_SET_USB0));
	return(0);
}

/*
 * Read from Device
 */
void
__usbDevRead(_usb_ext_handle *uhp)
{
#ifdef USB_HOST
	HOST_GLOBAL_STRUCT_PTR hgp = &host_global_struct[uhp->uh_which];
	_usb_host_handle handle = __osArcHostHandle[uhp->uh_which];
	
	if (hgp->curhandle != NULL) {
		PRINTF("--usbDevRead curhandle already set\n");
		return;
	}

	hgp->curhandle = uhp;
	hgp->driver->funcs->recv(handle, uhp->uh_rd_buffer,
		    uhp->uh_rd_len, uhp->uh_rd_offset);
	return;
#endif /* USB_HOST */
}

/*
 * Write to Device
 */
void
__usbDevWrite(_usb_ext_handle *uhp)
{
#ifdef USB_HOST
	HOST_GLOBAL_STRUCT_PTR hgp = &host_global_struct[uhp->uh_which];
	_usb_host_handle handle = __osArcHostHandle[uhp->uh_which];
	
	if (hgp->curhandle != NULL) {
		PRINTF("--usbDevWrite curhandle already set\n");
		return;
	}

	hgp->curhandle = uhp;
	hgp->driver->funcs->send(handle, uhp->uh_wr_buffer,
		    uhp->uh_wr_len, uhp->uh_wr_offset);
	return;
#endif /* USB_HOST */
}

#ifdef USB_MEMTEST
/*
 * Simpleminded memory test
 */
static void
__usbMemTest(u32 *addr, s32 size, u32 pattern)
{
	int i, j;

	PRINTF("__usbMemTest 0x%x %d 0x%x\n", (int)addr, size, pattern);

	/*
	 * Note that the BDT only support 4 byte aligned writes,
	 * so all transactions are in 32 bit words.
	 *
	 * Convert size from bytes to 32 bit words
	 */
	assert(((u32)addr & 0x3) == 0);
	assert((size & 0x3) == 0);
	size >>= 2;

	for (i = 0; i < size; i++) {
		IO_WRITE(addr+i, 0);
	}

	/*
	 * For each memory position, slam the value in and then
	 * verify that no other locations were corrupted.
	 *
	 * XXX if we keep this, then replace assert with something real
	 */
	for (i = 0; i < size; i++) {
		IO_WRITE(addr+i, pattern);
		if (pattern != IO_READ(addr+i)) {
PRINTF("__usbMemTest 0x%x should be 0x%x, is 0x%x\n", addr+i, pattern, IO_READ(addr+i));
		}
		for (j = 0; j < size; j++) {
			if (j != i) {
				if (0 != IO_READ(addr+j)) {
PRINTF("__usbMemTest 0x%x should be 0, is 0x%x\n", addr+j, IO_READ(addr+j));
				}
			}
		}
		IO_WRITE(addr+i, 0);
	}

}
#endif /* USB_MEMTEST */

/*
 * Run a basic sanity test on the hardware
 */
static void
__usbCtlrTest(s32 which)
{
#ifdef USB_MEMTEST
	u32 val;

	/*
	 * XXX if we keep this, then replace assert with something real
	 */
	val = IO_READ(USB_REG_ADDR(which, USB0_PER_ID_REG));
	PRINTF("__usbCtlrTest %d: PER_ID_REG value 0x%x\n", which, val);
	assert(val == 0x4);
	val = IO_READ(USB_REG_ADDR(which, USB0_ID_COMP_REG));
	PRINTF("__usbCtlrTest %d: ID_COMP_REG value 0x%x\n", which, val);
	assert(val == 0xfb);
	val = IO_READ(USB_REG_ADDR(which, USB0_REV_REG));
	PRINTF("__usbCtlrTest %d: REV_REG value 0x%x\n", which, val);
	val = IO_READ(USB_REG_ADDR(which, USB0_ADD_INFO_REG));
	PRINTF("__usbCtlrTest %d: ADD_INFO_REG value 0x%x\n", which, val);
	assert((val & 0x1) == 0x1);

	/*
	 * Run a minimal memory test on the BDT SRAM at least checking
	 * for "stuck ats"
	 */
	__usbMemTest((u32 *)USB_BDT_BASE(which), USB_BDT_SIZE, 0xa5a5a5a5);
	__usbMemTest((u32 *)USB_BDT_BASE(which), USB_BDT_SIZE, 0x5a5a5a5a);
#endif /* USB_MEMTEST */
}

/*
 * Called at startup for USB1 and whenever USB0 is put into Host mode
 */
static void
__usbHostMode(s32 which)
{
#ifdef USB_HOST
extern void __usb_arc_host_setup(s32, _usb_host_handle *);

	/* 
	 * Set the configuration for Host Mode using the
	 * OTG CTL register for pullup/pulldown signalling,
	 * as opposed to the normal CTL register.
	 */ 
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_CTRL_REG),
		OTG_CTL_OTG_ENABLE|
		OTG_CTL_VBUS_ON|
		OTG_CTL_DM_LOW|
		OTG_CTL_DP_LOW);

	/*
	 * Use ARC initialization code for now
	 */
	__usb_arc_host_setup(which, &__osArcHostHandle[which]);

	/* Unmask OTG interrupts */
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_EN_REG), 0xff);
	/* Unmask the USB interrupt to the MIPS cpu */
	IO_WRITE(MI_INTR_EMASK_REG,
		(which ? MI_INTR_MASK_SET_USB1 : MI_INTR_MASK_SET_USB0));
#endif /* USB_HOST */
}

/*
 * Called whenever USB0 is put into Device mode
 */
static void
__usbDeviceMode(s32 which)
{
extern void __usb_arc_device_setup(s32, _usb_device_handle *);

	__usb_arc_device_setup(which, &__osArcDeviceHandle[which]);

	/*
	 * Release Pull Ups on both D+ and D- momentarily, so that
	 * the host will get a detach and reattach if the
	 * device is reset without losing power.  This allows
	 * osBbUsbInit to be called a second time and have the
	 * host get a detach/reattach sequence.
	 */
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_CTRL_REG),
		OTG_CTL_OTG_ENABLE);

	/* wait for the host to notice */
	__osBbDelay(1000);

	/* Use OTG CTL for pullup/pulldown signalling and set Full Speed */
	if (which) {
		/*
		 * For USB1 in device mode pull down on both
		 * D+ and D- in order to work around a problem
		 * with the circuit.  This change gets the
		 * voltages in the proper ranges without having
		 * to update the board.
		 */
		IO_WRITE(USB_REG_ADDR(which, USB0_OTG_CTRL_REG),
		       OTG_CTL_OTG_ENABLE|OTG_CTL_DP_HIGH|OTG_CTL_DP_LOW|
		       OTG_CTL_DM_LOW);
	} else {
		IO_WRITE(USB_REG_ADDR(which, USB0_OTG_CTRL_REG),
		       OTG_CTL_OTG_ENABLE|OTG_CTL_DP_HIGH);
	}

	/* wait for things to settle */
	__osBbDelay(500);

	/* Unmask OTG interrupts */
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_EN_REG), 0xff);
	/* Unmask the USB interrupt to the MIPS cpu */
	IO_WRITE(MI_INTR_EMASK_REG,
		(which ? MI_INTR_MASK_SET_USB1 : MI_INTR_MASK_SET_USB0));
}

/*
 * Recheck OTG state on significant interrupts
 */
static void
__usbOtgStateChange(s32 which)
{
	u32 val;

	val = IO_READ(USB_REG_ADDR(which, USB0_OTG_STATUS_REG));
	PRINTF("__usbOtgState %d: OTG_STAT 0x%x OTG_ID %s\n", which, val,
		((val & OTG_STAT_ID_VLD) == 0) ? "host" : "device/none");

	/*
	 * If the controller is disabled, do nothing
	 */
	if (_usb_ctlr_state[which].ucs_mask == 0) {
		_usb_ctlr_state[which].ucs_mode = UCS_MODE_IDLE;
		return;
	}

	/*
	 * USB1 can be either host or device depending on whether it
	 * is connected through the breakout box or the special
	 * iQue-At-Home cable.
	 *
	 * Hardwire device mode for now.  Need to implement heuristic
	 * determination (try device mode first and then try host if
	 * no host enumerates us within a reasonable time) if we
	 * ever really support host mode on USB1.
	 */
	if (which) {
		if ((_usb_ctlr_state[which].ucs_mask & UCS_MODE_DEVICE) &&
	    	    (_usb_ctlr_state[which].ucs_mode != UCS_MODE_DEVICE)) {
			_usb_ctlr_state[which].ucs_mode = UCS_MODE_DEVICE;
			__usbDeviceMode(which);
		}
		return;
	}

	/*
	 * USB0 uses the ID bit in the OTG_STAT register to tell
	 * which type of connector is inserted (mini-A or mini-B)
	 * and chooses to be a Host or Device as appropriate.
	 */
	if ((val & OTG_STAT_ID_VLD) == 0) {
		/*
		 * A mini-A connector is already inserted, so initialize
		 * for host mode if that is allowed.
		 */
		if ((_usb_ctlr_state[which].ucs_mask & UCS_MODE_HOST) &&
		    (_usb_ctlr_state[which].ucs_mode != UCS_MODE_HOST)) {
			_usb_ctlr_state[which].ucs_mode = UCS_MODE_HOST;
			__usbHostMode(which);
		}
		return;
	}
       
	if ((_usb_ctlr_state[which].ucs_mask & UCS_MODE_DEVICE) &&
	    (_usb_ctlr_state[which].ucs_mode != UCS_MODE_DEVICE)) {
		_usb_ctlr_state[which].ucs_mode = UCS_MODE_DEVICE;
		__usbDeviceMode(which);
	}

}

/*
 * Keep track of number of USB resets since the last osBbUsbInit
 */
u32 __Usb_Reset_Count[OS_USB_MAX_CONTROLLERS];

u32
osBbUsbGetResetCount(s32 which)
{
	return __Usb_Reset_Count[which];
}

/*
 * Initialize one USB controller
 */
static void
__usbCtlrInit(s32 which)
{
	u32 addr = USB_BDT_BASE(which);

	PRINTF("__usbCtlrInit %d, bdt 0x%x\n", which, (int)addr);

	/*
	 * Common hardware initialization for both host and device modes.
	 * Make sure device is quiesced before proceeding.
	 */

	/* Mask the USB interrupt to the MIPS cpu */
	IO_WRITE(MI_INTR_EMASK_REG,
	        (which ? MI_INTR_MASK_CLR_USB1 : MI_INTR_MASK_CLR_USB0));

	/* Disable the VUSB */
	IO_WRITE(USB_REG_ADDR(which, USB0_CTL_REG), 0x00);
	/* Mask all interrupts and errors */
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_EN_REG), 0x00);
	IO_WRITE(USB_REG_ADDR(which, USB0_ERR_ENB_REG), 0x00);
	IO_WRITE(USB_REG_ADDR(which, USB0_INT_ENB_REG), 0x00);
	/* Clear all interrupts and errors */
	IO_WRITE(USB_REG_ADDR(which, USB0_OTG_INT_STAT_REG), 0xff);
	IO_WRITE(USB_REG_ADDR(which, USB0_ERR_STAT_REG), 0xff);
	IO_WRITE(USB_REG_ADDR(which, USB0_INT_STAT_REG), 0xff);
	/* Reset BDT bank */
	IO_WRITE(USB_REG_ADDR(which, USB0_CTL_REG), VUSB_CTRL_ODD_RST);
	/* Clear address reg */
	IO_WRITE(USB_REG_ADDR(which, USB0_ADDR_REG), 0x00);

	/*
	 * Set BDT pointer registers
	 */
	IO_WRITE(USB_REG_ADDR(which, USB0_BDT_PAGE_01_REG), (addr>>8) & 0xff);
	IO_WRITE(USB_REG_ADDR(which, USB0_BDT_PAGE_02_REG), (addr>>16) & 0xff);
	IO_WRITE(USB_REG_ADDR(which, USB0_BDT_PAGE_03_REG), (addr>>24) & 0xff);

	/*
	 * BBPLAYER does not support full OTG operation
	 *
	 * USB0 can be either Host or Device (mini-AB connector).
	 * This is the connector on the BB itself.
	 * 
	 * On USB0, SRP and HNP are not supported.  Mode is
	 * determined by the ID bit in the OTG_STAT register and
	 * an ID_CHG interrupt is generated by hardware on state
	 * change.
	 *
	 * USB1 can also be either Device or Host, but there
	 * is nothing wired to the ID bit.  This port is externalized
	 * either through the breakout box (in which case it is
	 * a host) or the special BB-to-PC iQue-At-Home cable
	 * (in which case it is a device).  There is no way in
	 * software to distinguish these two cases.  If we ever
	 * reach the point of supporting a USB device on the breakout
	 * box, we'll need to play a heuristic game:  try to be a
	 * device and if no host is there to enumerate us, then 
	 * try being a host.
	 *
	 * Execute the code to determine OTG state.
	 */
	__usbOtgStateChange(which);

        __Usb_Reset_Count[which] = 0;
}

/*
 * Initialize the two ARC USB cores
 */
s32
__usbHwInit()
{
	s32 i;

	PRINTF("__usbHwInit\n");

	/*
	 * The USB Access Control register must be set to allow
	 * insecure access.
	 */
	PRINTF("__usbHwInit: set USB Secure Mode OFF\n");
	IO_WRITE(USB0_SECURE_MODE_REG, USB_SECURE_MODE_OFF);
	IO_WRITE(USB1_SECURE_MODE_REG, USB_SECURE_MODE_OFF);

	/*
	 * Just assume the devices are there, but
	 * run tests to check that things are sane
	 */
	for (i = 0; i <  OS_USB_MAX_CONTROLLERS; i++) {
		__usbCtlrTest(i);
		__usbCtlrInit(i);
	}

	return(i);
}