tc.h
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/*
* tc.h - types, macros, prototypes for texture coordinate
* unit.
*
*
*/
#ifndef TEX_COORD_INCLD
#define TEX_COORD_INCLD
#include "ints.h"
#define DUMPLOD 1
#define DUMPTC 2
#define DUMPTM 4
/*
* Tile Texel Size Decode
*/
typedef enum {
TILE_4BIT,
TILE_8BIT,
TILE_16BIT,
TILE_32BIT
} TileTexSizes;
/*
* Tile Texel Type Decode
*/
typedef enum {
TILE_RGBA,
TILE_YUV,
TILE_CI,
TILE_IA,
TILE_I
} TileTexTypes;
/*
* Texture Lookup Table Type decode
*/
typedef enum {
TLUT_RGBA_16b,
TLUT_IA_16b
} TlutType;
/*
* Texture Sample Type
*/
typedef enum {
TC_POINT_SAMPLE,
TC_FILTER
} TcSampleType;
/*
* Texture Coordinate Unit Memory structure
*/
typedef struct tc
{
/* R e q u i r e d by C-sim */
char *label;
char **argv;
int argc;
int gclk_old;
/* I N P U T signals */
int gclk;
int st_span; /* start span signal */
int ncyc; /* 0: 1-cycle mode, 1: 2-cycle mode*/
/* per pixel data */
int s; /* clock 2, s,0.15 perspective divided tex image coord. */
int t; /* clock 2, s,0.15 perspective divided tex image coord. */
int w; /* clock 0, s,0.15 inverse normalized depth */
/* new, for LOD fix */
int s_dy; /* s+dy[15:0], s,10.5 from stepper */
int t_dy; /* t+dy[15:0], s,10.5 from stepper */
int w_dy; /* w+dy[15:0], s,0.15 from stepper */
int sel_s_dy; /* select either s or s+dy */
int sel_t_dy; /* select either t or s+dy */
int sel_w_dy; /* select either w or s+dy */
/* attribute data */
int min_level; /* clock 1, 5 bits, min lod fraction clamp */
int detail_en; /* clock 1, enable detail texture */
int sharp_en; /* clock 1, enable sharpened texture */
int lod_en; /* clock 1, use lod in tile indicies determination */
int persp_en; /* clock 0, enable perspective correction */
int copy; /* clock 4, copy */
int samp_type; /* clock 5, filter enabled */
int tlut_en; /* clock 6, enable texture lookup table */
/* primitive data */
int max_level; /* clock 1, 3 bits, number of mipmaps -1 or -2 */
int prim_tile; /* clock 1, 3 bits, base tile index of primitive */
int load; /* clock 0, load_tile, load_block, or load_tlut */
int shift_coord; /* clock 4, flag, indicates load_block prim active */
/* from command interface unit */
int tile_adrs; /* [2:0], tile write address */
int64 tile_data; /* [47:0], tile data */
int we_tile_size; /* write enable for tile size */
int we_tile_attr; /* write enable for tile attribute data */
/* from texture memory unit */
int clr_ind_a; /* color index texel a */
int clr_ind_b; /* color index texel b */
int clr_ind_c; /* color index texel c */
int clr_ind_d; /* color index texel d */
/* Video Memory Color LUT */
int vm_in; /* [7:0], index of pixel */
int vm_dv; /* pixel index data valid */
/* O U T P U T signals */
/* to color combine unit */
int l_fraction; /* lod fraction for 3rd axis interpolation */
int l_frac; /* l_frac out */
int l_frac_d1; /* l_frac delayed */
int l_frac_d2; /* l_frac delayed */
int l_frac_d3; /* l_frac delayed */
int l_frac_d4; /* l_frac delayed */
int l_frac_d5; /* l_frac delayed */
int l_frac_d6; /* l_frac delayed */
int l_frac_d7; /* l_frac delayed */
int l_frac_d8; /* l_frac delayed */
int tlut_en_d1; /* tlut_en delayed */
int tlut_en_d2; /* tlut_en delayed */
int lod_g_o; /* lod >= 1 */
int lod_ge_one; /* lod_ge_one out */
int lod_ge_one_d1; /* lod_ge_one delayed */
int lod_ge_one_d2; /* lod_ge_one delayed */
int lod_ge_one_d3; /* lod_ge_one delayed */
int lod_ge_one_d4; /* lod_ge_one delayed */
int lod_ge_one_d5; /* lod_ge_one delayed */
int lod_ge_one_d6; /* lod_ge_one delayed */
int lod_ge_one_d7; /* lod_ge_one delayed */
int lod_ge_one_d8; /* lod_ge_one delayed */
/* to texture filter unit */
int s_frac_ba; /* clock 7, 0.8, 3 lsbs are zero */
int s_frac_ba_d1; /* clock 8 */
int s_frac_ba_d2; /* clock 9 */
int s_frac_ba_d3; /* clock 10 */
int s_frac_ba_d4; /* clock 11 */
int s_frac_rg; /* clock 7, 0.8, 3 lsbs are zero */
int s_frac_rg_d1; /* clock 8 */
int s_frac_rg_d2; /* clock 9 */
int s_frac_rg_d3; /* clock 10 */
int s_frac_rg_d4; /* clock 11 */
int t_frac_ba; /* clock 7, 0.8, 3 lsbs are zero */
int t_frac_ba_d1; /* clock 8 */
int t_frac_ba_d2; /* clock 9 */
int t_frac_ba_d3; /* clock 10 */
int t_frac_ba_d4; /* clock 11 */
int t_frac_rg; /* clock 7, 0.8, 3 lsbs are zero */
int t_frac_rg_d1; /* clock 8 */
int t_frac_rg_d2; /* clock 9 */
int t_frac_rg_d3; /* clock 10 */
int t_frac_rg_d4; /* clock 11 */
/* to texture memory unit */
int adrs_bnk0l; /* clock 7, sorted address to low bank 0 */
int adrs_bnk1l; /* clock 7, sorted address to low bank 1 */
int adrs_bnk2l; /* clock 7, sorted address to low bank 2 */
int adrs_bnk3l; /* clock 7, sorted address to low bank 3 */
int adrs_bnk0h; /* clock 7, sorted address to high bank 0 */
int adrs_bnk1h; /* clock 7, sorted address to high bank 1 */
int adrs_bnk2h; /* clock 7, sorted address to high bank 2 */
int adrs_bnk3h; /* clock 7, sorted address to high bank 3 */
int adrs_a; /* clock 7, <12>,<3:0> address of texel a */
int adrs_b_ba; /* clock 7, <12>,<3:0> address of texel b (ba banks) */
int adrs_c; /* clock 7, <12>,<3:0> address of texel c */
int adrs_d_ba; /* clock 7, <12>,<3:0> address of texel d (ba banks) */
int adrs_b_rg; /* clock 7, <12>,<3:0> address of texel b (rg banks) */
int adrs_d_rg; /* clock 7, <12>,<3:0> address of texel d (rg banks) */
int swap_rg; /* clock 7, flag, swap texels (RG) */
int swap_ba; /* clock 7, flag, swap texels (BA) */
int tile_tex_type_1d; /* clock 6, tile format */
int tile_tex_size_1d; /* clock 6, tile size */
int palette; /* clock 7, 4 bits, upper bits of 4-bit color index pixel */
unsigned int a_three; /* clock 6, 3rd bit of address of texel a */
unsigned int a_twelve; /* clock 6, 12th bit of address of texel a */
unsigned int copy_2d; /* clock 6, copy signal delayed */
int vm_dv_d1; /* clock 7 */
int vm_dv_d2; /* clock 8 */
/* I n t e r m e d i a t e Signals */
unsigned int cycle: 1; /* clock 1, cycle signal */
unsigned int cycle2: 1; /* clock 2, cycle signal */
unsigned int cycle3: 1; /* clock 3, cycle signal */
unsigned int cycle4: 1; /* clock 4, cycle signal */
unsigned int cycle5: 1; /* clock 5, cycle signal */
unsigned int cycle6: 1; /* clock 6, cycle signal */
unsigned int st_span1: 1; /* clock 1, st_span signal */
unsigned int st_span2: 1; /* clock 2, st_span signal */
unsigned int st_span3: 1; /* clock 3, st_span signal */
unsigned int st_span4: 1; /* clock 4, st_span signal */
/* tcu perspective divide function */
unsigned int inv_w: 16; /* clock 1, 16.0 */
unsigned int inv_w_d1: 16; /* clock 2, 16.0 */
unsigned int inv_w_shift: 4; /* clock 1 */
unsigned int inv_w_shift_d1: 4; /* clock 2 */
unsigned int s_over_w: 19; /* clock 3, <over><under>,s,11.5 */
unsigned int t_over_w: 19; /* clock 3, <over><under>,s,11.5 */
unsigned int persp_dis: 1; /* clock 1, perspective disable */
unsigned int w_under: 1; /* clock 1, w underflowed */
unsigned int w_under_d1: 1; /* clock 2, w underflowed */
unsigned int w_under_d2: 1; /* clock 3, w underflowed */
/* lod module */
unsigned int l_tile: 3; /* clock 2, current tile */
unsigned int s_curr: 19; /* clock 4, hold s for delta calc. */
unsigned int t_curr: 19; /* clock 4, hold t for delta calc. */
unsigned int s_curr_d1: 19; /* clock 5, delay s_curr */
unsigned int t_curr_d1: 19; /* clock 5, delay t_curr */
unsigned int s_prev: 19; /* clock 6, */
unsigned int t_prev: 19; /* clock 6, */
unsigned int s_clamp: 16; /* clock 7, s clamped, s,10.5 */
unsigned int t_clamp: 16; /* clock 7, t clamped, s,10.5 */
unsigned int s_out: 16; /* clock 8, s clamped, s,10.5 */
unsigned int t_out: 16; /* clock 8, t clamped, s,10.5 */
unsigned int delta_y_max: 17; /* clock 4, delta Y max 12.5 */
unsigned int lod: 17; /* clock 6, 12.5,
level of detail @ pixel */
unsigned int clamp_max_lod: 1; /* clamp LOD */
unsigned int y_clamp: 1; /* clamp LOD */
/* tcu tile module */
unsigned int s_max: 1; /* clock 4 (flag) */
unsigned int t_max: 1; /* clock 4 (flag) */
unsigned int s_tile_diff: 10; /* clock 4, 10.0 */
unsigned int t_tile_diff: 10; /* clock 4, 10.0 */
unsigned int s_tile: 17; /* clock 4, s,11.5 or s,13.3 (load) */
unsigned int t_tile: 17; /* clock 4, s,11.5 or s,13.3 (load) */
/* tcu_wrap_mirror_clamp function */
unsigned int s_addr: 13; /* clock 5, tile address */
unsigned int t_addr: 13; /* clock 5, tile address */
unsigned int s_all_one: 1; /* clock 5, s_masked all ones */
unsigned int s_all_one_m1: 1; /* clock 5, s_masked all ones - 1 */
unsigned int s_all_one_m2: 1; /* clock 5, s_masked all ones - 2 */
unsigned int s_all_one_m3: 1; /* clock 5, s_masked all ones - 3 */
unsigned int s_all_zero: 1; /* clock 5, s_masked all zeros */
unsigned int s_all_zero_p1: 1; /* clock 5, s_masked all zeros + 1 */
unsigned int s_all_zero_p2: 1; /* clock 5, s_masked all zeros + 2 */
unsigned int s_all_zero_p3: 1; /* clock 5, s_masked all zeros + 3 */
unsigned int t_all_one: 1; /* clock 5, t_masked all ones */
unsigned int t_all_zero: 1; /* clock 5, t_masked all zeros */
unsigned int wrap_bit_s: 1; /* clock 5, */
unsigned int wrap_bit_t: 1; /* clock 5, */
unsigned int s_mask_en: 1; /* clock 5, */
unsigned int t_mask_en: 1; /* clock 5, */
/* tcu_fraction */
unsigned int s_frac: 5; /* clock 5, 0.5 */
unsigned int t_frac: 5; /* clock 5, 0.5 */
/* tcu_address */
unsigned int base_A: 13; /* clock 6, address */
unsigned int odd_t: 1; /* clock 6, odd line */
unsigned int flip: 1; /* clock 6, */
unsigned int b_addr: 13; /* clock 6, sign extend before using */
unsigned int c_addr: 13; /* clock 6, sign extend before using */
unsigned int d_addr: 13; /* clock 6, sign extend before using */
unsigned int shift: 1; /* clock 6 */
unsigned int yuv_tex: 1; /* clock 6 */
/* tcu_fraction */
unsigned int s_frac_d1: 5; /* clock 6, 0.5 */
unsigned int t_frac_d1: 5; /* clock 6, 0.5 */
unsigned int load_d1: 1; /* clock 1, load signal delayed */
unsigned int load_d2: 1; /* clock 2, load signal delayed */
unsigned int load_d3: 1; /* clock 3, load signal delayed */
unsigned int load_d4: 1; /* clock 4, load signal delayed */
unsigned int load_d5: 1; /* clock 5, load signal delayed */
unsigned int load_d6: 1; /* clock 6, load signal delayed */
unsigned int load_d7: 1; /* clock 7, load signal delayed */
unsigned int load_d8: 1; /* clock 8, load signal delayed */
unsigned int load_d9: 1; /* clock 9, load signal delayed */
unsigned int load_d10: 1; /* clock 10, load signal delayed */
unsigned int load_d11: 1; /* clock 11, load signal delayed */
unsigned int copy_d1: 1; /* clock 5, copy signal delayed */
/* tcu tile memory module */
unsigned int tile_adrs_d1: 3; /* [2:0], tile write address */
int64 tile_data_d1; /* [47:0], tile data */
unsigned int we_tile_size_d1: 1; /* write enable for tile size */
unsigned int we_tile_attr_d1: 1; /* write enable for tile attribute data */
/* delayed tile values */
unsigned int format: 3; /* clock 3, tile format */
unsigned int format_d1: 3; /* clock 4, tile format delayed */
unsigned int format_d2: 3; /* clock 5, tile format delayed */
unsigned int size: 2; /* clock 3, tile size */
unsigned int size_d1: 2; /* clock 4, tile size delayed */
unsigned int size_d2: 2; /* clock 5, tile size delayed */
unsigned int line: 9; /* clock 3, tile line */
unsigned int line_d1: 9; /* clock 4, tile line delayed */
unsigned int line_d2: 9; /* clock 5, tile line delayed */
unsigned int pal: 4; /* clock 3, tile palette */
unsigned int pal_d1: 4; /* clock 4, tile palette delayed */
unsigned int pal_d2: 4; /* clock 5, tile palette delayed */
unsigned int pal_d3: 4; /* clock 6, tile palette delayed */
unsigned int tmem_adrs: 9; /* clock 3, Tmem address */
unsigned int tmem_adrs_d1: 9; /* clock 4, Tmem address delayed */
unsigned int tmem_adrs_d2: 9; /* clock 5, Tmem address delayed */
unsigned int mirror_t: 1; /* clock 3, tile mirror t */
unsigned int mirror_t_d1: 1; /* clock 4, tile mirror t delayed */
unsigned int mirror_t_d2: 1; /* clock 5, tile mirror t delayed */
unsigned int mask_t: 4; /* clock 3, tile mask t */
unsigned int mask_t_d1: 4; /* clock 4, tile mask t delayed */
unsigned int mask_t_d2: 4; /* clock 5, tile mask t delayed */
unsigned int shift_t: 4; /* clock 3, tile shift t */
unsigned int mirror_s: 1; /* clock 3, tile mirror s */
unsigned int mirror_s_d1: 1; /* clock 4, tile mirror s delayed */
unsigned int mirror_s_d2: 1; /* clock 5, tile mirror s delayed */
unsigned int mask_s: 4; /* clock 3, tile mask s */
unsigned int mask_s_d1: 4; /* clock 4, tile mask s delayed */
unsigned int mask_s_d2: 4; /* clock 5, tile mask s delayed */
unsigned int shift_s: 4; /* clock 3, tile shift s */
unsigned int sl: 12; /* clock 3, tile s low */
unsigned int tl: 12; /* clock 3, tile t low */
unsigned int sh: 12; /* clock 3, tile s high */
unsigned int th: 12; /* clock 3, tile t high */
unsigned int clamp_s: 12; /* clock 3, tile s clamp */
unsigned int clamp_s_d1: 12; /* clock 4, tile s clamp delayed */
unsigned int clamp_t: 12; /* clock 3, tile s clamp */
unsigned int clamp_t_d1: 12; /* clock 4, tile s clamp delayed */
} tc_t;
/*
* Tile memory definition
*/
typedef struct {
unsigned format: 3, /* texel type */
size: 2, /* texel size */
line: 9, /* number of 64b words per row */
tmem_adrs: 9, /* tile offset in Tmem */
palette: 4, /* palette for 4b color index */
mirror_t: 1, /* mirror enable */
mirror_s: 1, /* mirror enable */
clamp_t: 1, /* clamp enable */
clamp_s: 1, /* clamp enable */
mask_t: 4, /* wrap bit t */
mask_s: 4, /* wrap bit s */
shift_t: 4, /* right shift code */
shift_s: 4, /* right shift code */
sl: 12, /* starting texel column in image space */
sh: 12, /* ending texel column in image space */
tl: 12, /* starting texel row in image space */
th: 12; /* ending texel row in image space */
} TcTileMemory;
/*
* Prototypes
*/
TcTileMemory *read_tile_memory(int tile);
void load_tile_memory(int tile, TcTileMemory *tp);
void tc(tc_t **pp0, tc_t **pp1);
void tc_init(tc_t *p0, tc_t *p1);
void set_tile(char *file);
#endif /* TEX_COORD_INCLD */