`timescale 10ps / 10ps  //1unit = 0.01ns

module ri_test(reset_l, ri_cbus_read_enable, ri_cbus_write_enable,
	      cbus_command, ri_read_grant, bus_clk,
	      dma_ready, dma_start, dma_last, ri_read_request,
	      sp_dbus_read_enable, mi_dbus_read_enable, span_dbus_read_enable,
	      sp_dbus_write_enable, mi_dbus_write_enable,
	      pi_dbus_write_enable, si_dbus_write_enable,
	      span_dbus_write_enable,
	      cbus_data, dbus_data, ebus_data,
	      clock,
	      c_ctl_ld);

`include "rcp.vh"

// ri inputs

input reset_l;					// from pad
input ri_cbus_read_enable;			// from arb
input ri_cbus_write_enable;			// from arb
input [CBUS_COMMAND_SIZE-1:0] cbus_command;	// from arb
input ri_read_grant;				// from arb

// rac inputs

input bus_clk;

// ri outputs

output dma_ready;				// to arb
output dma_start;				// to rsp
output dma_last;				// to rsp
output ri_read_request;				// to arb
output sp_dbus_read_enable;			// to rsp
output mi_dbus_read_enable;			// to mi
output span_dbus_read_enable;			// to rdp
output sp_dbus_write_enable;			// to rsp
output mi_dbus_write_enable;			// to mi
output pi_dbus_write_enable;			// to pi
output si_dbus_write_enable;			// to si
output span_dbus_write_enable;			// to rdp

// ri inouts

inout [CBUS_DATA_SIZE-1:0] cbus_data;
inout [DBUS_DATA_SIZE-1:0] dbus_data;
inout [EBUS_DATA_SIZE-1:0] ebus_data;

// rac outputs

output clock;

// interesting intermediate signals

output c_ctl_ld;

// rac signals
wire syn_clk_fd;
wire bist_flag, scan_out;
wire syn_clk_in;
wire [RAC_RECEIVE_DATA_SIZE-1:0] r_data_7, r_data_6, r_data_5, r_data_4;
wire [RAC_RECEIVE_DATA_SIZE-1:0] r_data_3, r_data_2, r_data_1, r_data_0;
wire [RAC_TRANSMIT_DATA_SIZE-1:0] t_data_7, t_data_6, t_data_5, t_data_4;
wire [RAC_TRANSMIT_DATA_SIZE-1:0] t_data_3, t_data_2, t_data_1, t_data_0;
wire ack, nack;
wire rac_reset;

// rbus signals
wire [RBUS_DATA_SIZE-1:0] rbus_data_in;
wire [RBUS_EXTEND_SIZE-1:0] rbus_extend_in;
wire [RBUS_CONTROL_SIZE-1:0] rbus_control_in;
wire [RBUS_DATA_SIZE-1:0] rbus_data_out;
wire [RBUS_EXTEND_SIZE-1:0] rbus_extend_out;
wire [RBUS_CONTROL_SIZE-1:0] rbus_control_out;
wire [RBUS_ENABLE_SIZE-1:0] rbus_enable_out;

// ri <> rac wires

wire [RAC_SELECT_SIZE-1:0] rac_sel_in;
wire [RAC_SELECT_SIZE-1:0] rac_sel_out;
wire c_ctl_en, c_ctl_ld;
wire stop_r, stop_t;
wire [RAC_CURRENT_SIZE-1:0] c_ctl_i;

// rac <> rdram wires

wire bus_enable_rac;
wire bus_ctrl_rac;
wire [RAMBUS_DATA_SIZE-1:0] bus_data_rac;

// rac <> rdram wires

wire s0, s1, s2, s3;

supply0 gnd;
supply1 vcc;

ri ri_0(
   .clock(clock),
   .reset_l(reset_l),
   .cbus_read_enable(ri_cbus_read_enable),
   .cbus_write_enable(ri_cbus_write_enable),
   .cbus_command(cbus_command),
   .read_grant(ri_read_grant),
   .rbus_data_in(rbus_data_in),
   .rbus_extend_in(rbus_extend_in),
   .ack(ack),
   .nack(nack),
   .tst_c_ctl_en(gnd),
   .tst_c_ctl_ld(gnd),
   .tst_c_ctl_i(gnd),
   .ready(dma_ready),
   .start(dma_start),
   .last(dma_last),
   .read_request(ri_read_request),
   .sp_dbus_read_enable(sp_dbus_read_enable),
   .mi_dbus_read_enable(mi_dbus_read_enable),
   .span_dbus_read_enable(span_dbus_read_enable),
   .sp_dbus_write_enable(sp_dbus_write_enable),
   .mi_dbus_write_enable(mi_dbus_write_enable),
   .pi_dbus_write_enable(pi_dbus_write_enable),
   .si_dbus_write_enable(si_dbus_write_enable),
   .span_dbus_write_enable(span_dbus_write_enable),
   .rbus_data_out(rbus_data_out),
   .rbus_extend_out(rbus_extend_out),
   .rbus_control_out(rbus_control_out),
   .rbus_enable_out(rbus_enable_out),
   .c_ctl_en(c_ctl_en),
   .c_ctl_ld(c_ctl_ld),
   .c_ctl_i(c_ctl_i),
   .rac_sel_in(rac_sel_in),
   .rac_sel_out(rac_sel_out),
   .stop_t(stop_t),
   .stop_r(stop_r),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data),
   .ebus_data(ebus_data));

rac rac_0(
   .RData7(r_data_7),
   .RData6(r_data_6),
   .RData5(r_data_5),
   .RData4(r_data_4),
   .RData3(r_data_3),
   .RData2(r_data_2),
   .RData1(r_data_1),
   .RData0(r_data_0),
   .SynClk(syn_clk),
   .SynClkFd(syn_clk_fd),
   .BusEnable(bus_enable_rac),
   .BISTFlag(bist_flag),
   .SCANOut(scan_out),
   .BusCtrl(bus_ctrl_rac),
   .BusData(bus_data_rac),
   .BusClk(bus_clk),
   .BDSel(rac_sel_out),
   .BCSel(rac_sel_out),
   .BESel(rac_sel_out),
   .RDSel(rac_sel_in),
   .RCSel(rac_sel_in),
   .Reset(rac_reset),
   .TData7(t_data_7),
   .TData6(t_data_6),
   .TData5(t_data_5),
   .TData4(t_data_4),
   .TData3(t_data_3),
   .TData2(t_data_2),
   .TData1(t_data_1),
   .TData0(t_data_0),
   .Vref(vcc),
   .BISTMode(gnd),
   .IOSTMode(gnd),
   .SCANMode(gnd),
   .SCANClk(gnd),
   .SCANEn(gnd),
   .SCANIn(gnd),
   .SynClkIn(syn_clk_in),
   .CCtlEn(c_ctl_en),
   .CCtlLd(c_ctl_ld),
   .CCtlI(c_ctl_i),
   .CCtlPgm(vcc),
   .PwrUp(vcc),
   .ExtBE(gnd),
   .StopR(stop_r),
   .StopT(stop_t),
   .ByPass(gnd),
   .ByPSel(gnd),
   .rclkASIC(gnd),
   .tclkASIC(gnd),
   .PhStall(gnd));

rdram rdram_0(.RxClk(bus_clk), .TxClk(bus_clk),
	      .BusEnable(bus_enable_rac),
	      .BusCtrl(bus_ctrl_rac), .BusData(bus_data_rac),
	      .SIn(vcc), .SOut(s_0), .VRef(vcc));

rdram rdram_1(.RxClk(bus_clk), .TxClk(bus_clk),
	      .BusEnable(bus_enable_rac), .BusCtrl(bus_ctrl_rac),
	      .BusData(bus_data_rac),
	      .SIn(s_0), .SOut(s_1), .VRef(vcc));

rdram rdram_2(.RxClk(bus_clk), .TxClk(bus_clk),
	      .BusEnable(bus_enable_rac), .BusCtrl(bus_ctrl_rac),
	      .BusData(bus_data_rac),
	      .SIn(s_1), .SOut(s_2), .VRef(vcc));

rdram rdram_3(.RxClk(bus_clk), .TxClk(bus_clk),
	      .BusEnable(bus_enable_rac), .BusCtrl(bus_ctrl_rac),
	      .BusData(bus_data_rac),
	      .SIn(s_2), .SOut(s_3), .VRef(vcc));

// Rambus pull up resistors

pullup (bus_data_rac[0]);
pullup (bus_data_rac[1]);
pullup (bus_data_rac[2]);
pullup (bus_data_rac[3]);
pullup (bus_data_rac[4]);
pullup (bus_data_rac[5]);
pullup (bus_data_rac[6]);
pullup (bus_data_rac[7]);
pullup (bus_data_rac[8]);
pullup (bus_ctrl_rac);
pullup (bus_enable_rac);

assign syn_clk_in = syn_clk;
assign clock = syn_clk;
assign rac_reset = ~reset_l;

assign {rbus_control_in[0], rbus_extend_in[0], rbus_data_in[ 7: 0]} = r_data_7;
assign {rbus_control_in[1], rbus_extend_in[1], rbus_data_in[15: 8]} = r_data_6;
assign {rbus_control_in[2], rbus_extend_in[2], rbus_data_in[23:16]} = r_data_5;
assign {rbus_control_in[3], rbus_extend_in[3], rbus_data_in[31:24]} = r_data_4;
assign {rbus_control_in[4], rbus_extend_in[4], rbus_data_in[39:32]} = r_data_3;
assign {rbus_control_in[5], rbus_extend_in[5], rbus_data_in[47:40]} = r_data_2;
assign {rbus_control_in[6], rbus_extend_in[6], rbus_data_in[55:48]} = r_data_1;
assign {rbus_control_in[7], rbus_extend_in[7], rbus_data_in[63:56]} = r_data_0;

assign t_data_7 = {rbus_enable_out[0], rbus_control_out[0], rbus_extend_out[0], rbus_data_out[ 7: 0]};
assign t_data_6 = {rbus_enable_out[1], rbus_control_out[1], rbus_extend_out[1], rbus_data_out[15: 8]};
assign t_data_5 = {rbus_enable_out[2], rbus_control_out[2], rbus_extend_out[2], rbus_data_out[23:16]};
assign t_data_4 = {rbus_enable_out[3], rbus_control_out[3], rbus_extend_out[3], rbus_data_out[31:24]};
assign t_data_3 = {rbus_enable_out[4], rbus_control_out[4], rbus_extend_out[4], rbus_data_out[39:32]};
assign t_data_2 = {rbus_enable_out[5], rbus_control_out[5], rbus_extend_out[5], rbus_data_out[47:40]};
assign t_data_1 = {rbus_enable_out[6], rbus_control_out[6], rbus_extend_out[6], rbus_data_out[55:48]};
assign t_data_0 = {rbus_enable_out[7], rbus_control_out[7], rbus_extend_out[7], rbus_data_out[63:56]};

assign ack = rbus_control_in[7];
assign nack = rbus_control_in[2];

endmodule