test000.v
2.88 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
//
// test000 Vary bus device and ensure correct *dbus_write_enable
// and *dbus_read_enable lines go high
task test000;
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 'h00000000, BUS_DEVICE_SP, -1, 8);
while (!dma_last)
@(posedge clock);
if (sp_dbus_write_enable !== 1'b1)
begin
$write("test000: sp_dbus_write_enable expected: %d ",
1'b1, "was: %d ", sp_dbus_write_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 'h00000000, BUS_DEVICE_MI, -1, 8);
while (!dma_last)
@(posedge clock);
if (mi_dbus_write_enable !== 1'b1)
begin
$write("test000: mi_dbus_write_enable expected: %d ",
1'b1, "was: %d ", mi_dbus_write_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 'h00000000, BUS_DEVICE_PI, -1, 8);
while (!dma_last)
@(posedge clock);
if (pi_dbus_write_enable !== 1'b1)
begin
$write("test000: pi_dbus_write_enable expected: %d ",
1'b1, "was: %d ", pi_dbus_write_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 'h00000000, BUS_DEVICE_SI, -1, 8);
while (!dma_last)
@(posedge clock);
if (si_dbus_write_enable !== 1'b1)
begin
$write("test000: si_dbus_write_enable expected: %d ",
1'b1, "was: %d ", si_dbus_write_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 'h00000000,
BUS_DEVICE_DP_SPAN, -1, 8);
while (!dma_last)
@(posedge clock);
if (span_dbus_write_enable !== 1'b1)
begin
$write("test000: span_dbus_write_enable expected: %d ",
1'b1, "was: %d ", span_dbus_write_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, 'h00000000, BUS_DEVICE_SP, 3, 8);
while (!dma_last)
@(posedge clock);
if (sp_dbus_read_enable !== 1'b1)
begin
$write("test000: sp_dbus_read_enable expected: %d ",
1'b1, "was: %d ", sp_dbus_read_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, 'h00000000, BUS_DEVICE_MI, 3, 8);
while (!dma_last)
@(posedge clock);
if (mi_dbus_read_enable !== 1'b1)
begin
$write("test000: mi_dbus_read_enable expected: %d ",
1'b1, "was: %d ", mi_dbus_read_enable,
" at time", $time, "\n");
errors = errors + 1;
end
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, 'h00000000,
BUS_DEVICE_DP_SPAN, 3, 8);
while (!dma_last)
@(posedge clock);
if (span_dbus_read_enable !== 1'b1)
begin
$write("test000: span_dbus_read_enable expected: %d ",
1'b1, "was: %d ", span_dbus_read_enable,
" at time", $time, "\n");
errors = errors + 1;
end
end
endtask