test002.v
1.51 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
//
// test002 Vary start_delay values on dma read operation
//
`define LO_DELAY -3
`define HI_DELAY 3
task test002;
fork
test002_check;
test002_cmddata;
join
endtask
task test002_check;
integer i;
begin
for (i = 0; i < 6; i = i + 1)
begin
while (!dma_start)
@(posedge clock);
if (!dma_last)
begin
$write("test001: dma_last expected: %d was %d at time %d\n",
1'b1, dma_last, $time);
errors = errors + 1;
end
@(posedge clock);
end
end
endtask
task test002_cmddata;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
reg [EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;
reg [DMA_DELAY_SIZE-1:0] start_delay;
integer i;
begin
address = 0;
for (i = `LO_DELAY; i <= `HI_DELAY; i = i + 1)
begin
start_delay = i;
expected_d_data = {8{start_delay}};
expected_e_data = start_delay;
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address, BUS_DEVICE_MI, -2, 8);
dbus_put_data(expected_d_data, expected_e_data, -2);
address = address + 8;
end
address = 0;
for (i = `LO_DELAY; i <= `HI_DELAY; i = i + 1)
begin
start_delay = i;
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, i, 8);
dbus_get_data(actual_d_data, actual_e_data, i);
expected_d_data = {8{start_delay}};
expected_e_data = start_delay;
check_data("test002", expected_d_data, actual_d_data,
expected_e_data, actual_e_data);
address = address + 8;
end
end
endtask